WO1999053527A3 - Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice - Google Patents

Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice Download PDF

Info

Publication number
WO1999053527A3
WO1999053527A3 PCT/US1999/001450 US9901450W WO9953527A3 WO 1999053527 A3 WO1999053527 A3 WO 1999053527A3 US 9901450 W US9901450 W US 9901450W WO 9953527 A3 WO9953527 A3 WO 9953527A3
Authority
WO
WIPO (PCT)
Prior art keywords
assemblies
bond pads
dice
wire bonding
tests
Prior art date
Application number
PCT/US1999/001450
Other languages
French (fr)
Other versions
WO1999053527A2 (en
Inventor
Rich Fogal
Steve Heppler
Original Assignee
Micron Technology Inc
Rich Fogal
Steve Heppler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Rich Fogal, Steve Heppler filed Critical Micron Technology Inc
Priority to AU23388/99A priority Critical patent/AU2338899A/en
Publication of WO1999053527A2 publication Critical patent/WO1999053527A2/en
Publication of WO1999053527A3 publication Critical patent/WO1999053527A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Abstract

A method and system (68) for fabricating electronic assemblies (22), such as multi chip modules, which include wire bonded semiconductor dice (12), are provided. Initially, dice (12) having bond pads (14), and a substrate (10) having corresponding bond pads (20), are provided. Using a wire bonding process, bonded connections (34, 36) are made between the bond pads (14) on the dice, and the bond pads (20) on the substrate (10). During the wire bonding process, electrical continuity in the bonded connections (34, 36) can be evaluated. Following wire bonding, but prior to subsequent processing of the assemblies (22), quick functionality tests can be performed to evaluate other electrical characteristics of the assemblies (22) (e.g., gross fucntionality, open/short, pad leakage, cell defects). This permits defective assemblies (22) to be identified prior to further processing. Once the assemblies (22) have been completed, full functionality and parametric tests can be performed. A system (68) for performing the method includes a conventional wire bonder (70); a tester (24) having test circuitry (46) for performing the required tests; and an electrical connector (26) for establishing temporary electrical communication with the assembly (22).
PCT/US1999/001450 1998-04-13 1999-01-25 Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice WO1999053527A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU23388/99A AU2338899A (en) 1998-04-13 1999-01-25 Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/059,245 US5918107A (en) 1998-04-13 1998-04-13 Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice
US09/059,245 1998-04-13

Publications (2)

Publication Number Publication Date
WO1999053527A2 WO1999053527A2 (en) 1999-10-21
WO1999053527A3 true WO1999053527A3 (en) 2002-05-10

Family

ID=22021743

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/001450 WO1999053527A2 (en) 1998-04-13 1999-01-25 Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice

Country Status (3)

Country Link
US (2) US5918107A (en)
AU (1) AU2338899A (en)
WO (1) WO1999053527A2 (en)

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US6085962A (en) * 1997-09-08 2000-07-11 Micron Technology, Inc. Wire bond monitoring system for layered packages
US5918107A (en) * 1998-04-13 1999-06-29 Micron Technology, Inc. Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice
US6677776B2 (en) * 1998-05-11 2004-01-13 Micron Technology, Inc. Method and system having switching network for testing semiconductor components on a substrate
FI990375A (en) * 1999-02-22 2000-12-07 Nokia Networks Oy Procedure for testing circuit board mounts and a circuit board
JP3388202B2 (en) * 1999-05-26 2003-03-17 ローム株式会社 Semiconductor integrated circuit device and device assembling method
US6054721A (en) * 1999-07-14 2000-04-25 Advanced Micro Devices, Inc. Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer
US6251695B1 (en) * 1999-09-01 2001-06-26 S3 Graphics Co., Ltd. Multichip module packaging process for known good die burn-in
US6342399B1 (en) * 1999-11-08 2002-01-29 Agere Systems Guardian Corp. Testing integrated circuits
US7173444B2 (en) * 2000-04-04 2007-02-06 Ali Pourkeramati Structure and method for parallel testing of dies on a semiconductor wafer
US6323639B1 (en) * 2000-04-04 2001-11-27 Azalea Microelectronics Corporation Powering dies on a semiconductor wafer through wafer scribe line areas
JP4583581B2 (en) * 2000-11-07 2010-11-17 ルネサスエレクトロニクス株式会社 Method for manufacturing solid-state imaging device
JP2002270759A (en) 2001-03-14 2002-09-20 Matsushita Electric Ind Co Ltd Semiconductor chip and multi-chip module
JP3794942B2 (en) * 2001-07-09 2006-07-12 松下電器産業株式会社 Multichip module and connection test method thereof
US7064447B2 (en) * 2001-08-10 2006-06-20 Micron Technology, Inc. Bond pad structure comprising multiple bond pads with metal overlap
TW513795B (en) * 2001-12-31 2002-12-11 Siliconware Precision Industries Co Ltd Wire bonding method and system for fabricating semiconductor package
US6853202B1 (en) 2002-01-23 2005-02-08 Cypress Semiconductor Corporation Non-stick detection method and mechanism for array molded laminate packages
US7041516B2 (en) * 2002-10-10 2006-05-09 Lsi Logic Corporation Multi chip module assembly
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
JP2005302809A (en) * 2004-04-07 2005-10-27 Toshiba Corp Semiconductor device
US7250311B2 (en) * 2005-02-23 2007-07-31 International Business Machines Corporation Wirebond crack sensor for low-k die
US9482879B2 (en) * 2012-02-28 2016-11-01 Johnson & Johnson Vision Care, Inc. Methods of manufacture and use of energized ophthalmic devices having an electrical storage mode
TWI572941B (en) 2012-02-28 2017-03-01 壯生和壯生視覺關懷公司 Methods and apparatus to form electronic circuitry on ophthalmic devices
US8919632B2 (en) * 2012-11-09 2014-12-30 Asm Technology Singapore Pte. Ltd. Method of detecting wire bonding failures
CN104813457B (en) * 2012-11-16 2017-08-04 株式会社新川 Throwing device and routing method
IL231344B (en) * 2013-03-13 2018-08-30 Johnson & Johnson Vision Care Methods of manufacture and use of energized ophthalmic devices having an electrical storage mode
KR102254026B1 (en) * 2014-08-18 2021-05-20 삼성전자주식회사 Method of manufacturing a semiconductor package
RU2660020C1 (en) * 2017-06-05 2018-07-04 Акционерное общество "НПО "Орион" Method of on-line inspection of the docking quality
RU2686882C1 (en) * 2018-09-26 2019-05-06 Акционерное общество "НПО "Орион" Method to increase accuracy of docking quality control
US11017877B2 (en) 2019-01-11 2021-05-25 Samsung Electronics Co., Ltd. Multi-chip package
US11244738B2 (en) 2019-01-11 2022-02-08 Samsung Electronics Co., Ltd. Multi-chip package

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US5514912A (en) * 1987-01-30 1996-05-07 Tanaka Denshi Kogyo Kabushiki Kaisha Method for connecting semiconductor material and semiconductor device used in connecting method
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Also Published As

Publication number Publication date
US5918107A (en) 1999-06-29
AU2338899A (en) 1999-11-01
WO1999053527A2 (en) 1999-10-21
US6117693A (en) 2000-09-12

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