WO1999054883A2

WO1999054883A2 - Method for writing and reading digital information values

Info

Publication number: WO1999054883A2
Application number: PCT/DE1999/000572
Authority: WO
Inventors: Claus Schneider
Original assignee: Infineon Technologies Ag
Priority date: 1998-04-22
Filing date: 1999-03-03
Publication date: 1999-10-28
Also published as: EP1074023A2; WO1999054883A3; JP2002512410A

Abstract

The invention relates to a method for writing and reading digital information values in and out of the storage cells of a memory, said storage cells being organized in lines and columns. The information values are both written and read line by line and column by column in an alternating manner. A complete cycle of a writing and reading operation comprises the following steps. Starting from an initial cell of the memory, the information values are written line by line/column by column in the memory. After the information values are completely written line by line and column by column in the memory, the memory reads out in a line by line/column by column manner. The initial cell is displaced around a position within a line/column by inserting a column/line. All columns/lines of the memory are read out starting from the displaced initial cell.

Description

description

Process for writing and reading digital information values.

The invention relates to a method for writing and reading digital information values in and from the memory cells of a memory, which memory cells are organized in rows and columns.

In matrix operations, for example matrix-matrix multiplication in digital filters, matrices often have to be transposed, i.e. the elements of the matrix are calculated line by line, but must be processed in columns. To carry out such matrix operations, it is common to use a buffer that is written line by line and then read column by column. Removable memories are often used to decouple write and read operations, with one of the memories being written line by line and the other being read in columns.

An integrated circuit for row and column addition for matrices is known from US Pat. No. 4,872,134, in which a memory is read and written row by row and column, with a read operation being carried out for each address before the write operation on the same memory cell , whereby the two operations are rigidly coupled and each have the same data rate.

A device for bit block transfer is known from US Pat. No. 4,763,251, in which multi-dimensionally stored data is accessed row by row and in column and in which an area of a large additional memory is modified only once.

The invention is based on the object of specifying a method in which the best possible decoupling of write and read operations is achieved with as little outlay on auxiliary memory as possible.

This object is achieved by a method according to claim 1.

An advantageous development is specified in the subclaim.

The invention is explained in more detail below with reference to several exemplary embodiments shown in the drawing. It shows:

FIGS. 1A to 1D show a schematic representation of successive steps in carrying out the method according to the invention;

FIG. 2 shows a schematic representation of how the original cell shifts per cycle and finally moves back to the starting position;

Figure 3 is a schematic representation of a matrix with indices for physical addresses and logical rows and columns;

FIGS. 4A and 4B show a schematic representation of the matrix according to FIG. 3 after six cycles with a shift in the logical origin by three rows and three columns and one cycle later; and

Figure 5 is a schematic representation for explaining a Application of the method according to the invention in the multiplication of matrices.

FIG. 1A schematically shows a semiconductor memory 1 for use in the calculation of matrix operations, the memory cells of which are organized in rows ZI to Z9 and columns S1 to S8. It is a memory with eight x eight memory cells and an additional row Z9 with eight memory cells, which serves to better decouple the write and read operations, as explained below. According to FIG. 1A, the original memory cell 2 (matrix cell 0.0) is located at the top left, the information values are written into the memory m line by line in the direction of the solid arrow 3. At the beginning, the memory according to FIG. 1A is then written line by line, the additional buffer line Z9 initially remaining empty. After the matrix has been written completely line by line, it can be read out column by column in the direction of the dashed arrow 4 according to FIG. 1B. The additional buffer line Z9 is now added as column S9 on the left of the matrix, and starting from the new column S9, parallel to column-by-column reading, it is now also possible to write column-by-column. After the matrices have been read and written in columns, the right column S8 is added to the top of the matrix as line ZO and the matrix is read and written line by line, as is shown schematically in FIG. In FIG. 1D the cycle begins again, based on the principle as explained in FIG. 1B.

It can be seen from the schematic illustration in FIG. 2 how the original cell 2 shifts per cycle and finally moves back to the starting position.

In Figure 3, the initial mapping of the logical rows ZI ... Z9 and the logical columns Sl ... S8 is schematic to the physical addresses (indices) 00, 01, 02, ... etc.

FIG. 4A shows the matrix after six cycles with a shift in the origin by three rows and three columns. The area 5 corresponds to the original matrix, the area 6 was created by adding columns of the rows removed below, and the area 7 by adding rows of the columns removed on the right. FIG. 4B shows the matrix one cycle later, the origin 00 having moved from column S3 to column S4 by adding a column on the left-hand matrix edge. The solid arrows 8 m in FIGS. 4A and 4B schematically show the order of the write operations, the dashed arrows 9 correspond to the order of the read operations. It should be noted that the control suitable for performing the method should generate a physical memory address for the write and read operation depending on the logical position of the origin, the write and read pointer.

FIG. 5 shows an application example of the invention. The matrix X is multiplied by the matrix C, the intermediate result matrix Y is transposed (Y ^τ ) and then multiplied by the matrix C, resulting in the final result matrix Z.

If the two matrix operations write and read follow the same timing scheme, they can be coupled directly without an additional buffer line, i.e. a memory cell that is being read can be overwritten in the next cycle.

If the write and read operations are to be decoupled more, any number of additional buffer lines can be inserted. For the control, however, it is to select integer divisors of the matrix dimension so that after a small number of cycles the origin is transferred back to the starting position, as is shown schematically in FIG.

Claims

claims

1. A method for writing and reading digital information values in and from the memory cells of a memory, which memory cells are organized in rows and columns, in which both writing and reading of the information values takes place alternately in rows and columns, in which a additional memory cell area of the memory is written as an additional row / column and is read as an additional column / row and in which a complete cycle of a write and read operation comprises the following steps:

starting from an original cell of the memory, the information values are written into the memory in rows / columns,

after the information values have been written completely to the memory in rows / columns, the memory is read in columns / rows, the original cell being shifted by one position within a row / column by adding a column / row,

- All columns / rows of the memory are read out, starting from the moved source cell.

2. The method according to claim 1, wherein the additional area is shifted as a row / column after writing into a column / row for reading.