WO1999060479A1 - Single and multiple channel memory detection and sizing - Google Patents
Single and multiple channel memory detection and sizing Download PDFInfo
- Publication number
- WO1999060479A1 WO1999060479A1 PCT/US1999/004720 US9904720W WO9960479A1 WO 1999060479 A1 WO1999060479 A1 WO 1999060479A1 US 9904720 W US9904720 W US 9904720W WO 9960479 A1 WO9960479 A1 WO 9960479A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- group
- counter
- channel
- memory
- incrementing
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title description 2
- 238000004513 sizing Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000010586 diagram Methods 0.000 description 12
- 230000007334 memory performance Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0027775A GB2353884B (en) | 1998-05-18 | 1999-03-03 | Single and multiple channel memory detection and sizing |
DE19983256T DE19983256T1 (en) | 1998-05-18 | 1999-03-03 | Single and multi-channel memory acquisition and sizing |
AU28014/99A AU2801499A (en) | 1998-05-18 | 1999-03-03 | Single and multiple channel memory detection and sizing |
HK01102409A HK1031931A1 (en) | 1998-05-18 | 2001-04-04 | Single and multiple channel memory detection and sizing |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/080,872 | 1998-05-18 | ||
US09/080,872 US6003121A (en) | 1998-05-18 | 1998-05-18 | Single and multiple channel memory detection and sizing |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999060479A1 true WO1999060479A1 (en) | 1999-11-25 |
Family
ID=22160187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/004720 WO1999060479A1 (en) | 1998-05-18 | 1999-03-03 | Single and multiple channel memory detection and sizing |
Country Status (6)
Country | Link |
---|---|
US (1) | US6003121A (en) |
AU (1) | AU2801499A (en) |
DE (1) | DE19983256T1 (en) |
GB (1) | GB2353884B (en) |
HK (2) | HK1031931A1 (en) |
WO (1) | WO1999060479A1 (en) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6633947B1 (en) * | 1998-09-16 | 2003-10-14 | Intel Corporation | Memory expansion channel for propagation of control and request packets |
US6378056B2 (en) * | 1998-11-03 | 2002-04-23 | Intel Corporation | Method and apparatus for configuring a memory device and a memory channel using configuration space registers |
US6226729B1 (en) * | 1998-11-03 | 2001-05-01 | Intel Corporation | Method and apparatus for configuring and initializing a memory device and a memory channel |
US6442698B2 (en) * | 1998-11-04 | 2002-08-27 | Intel Corporation | Method and apparatus for power management in a memory subsystem |
US6272567B1 (en) * | 1998-11-24 | 2001-08-07 | Nexabit Networks, Inc. | System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed |
EP1153395A4 (en) | 1998-12-30 | 2002-04-17 | Intel Corp | Memory array organization |
US6357018B1 (en) * | 1999-01-26 | 2002-03-12 | Dell Usa, L.P. | Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system |
US6636943B1 (en) * | 1999-07-30 | 2003-10-21 | Hewlett-Packard Development Company, L.P. | Method for detecting continuity modules in a direct Rambus DRAM subsystem |
US6366983B1 (en) * | 1999-09-14 | 2002-04-02 | Intel Corporation | Method and system for symmetric memory population |
US7010629B1 (en) * | 1999-12-22 | 2006-03-07 | Intel Corporation | Apparatus and method for coupling to a memory module |
US6298006B1 (en) * | 1999-12-30 | 2001-10-02 | Intel Corporation | Method and apparatus to automatically determine the size of an external EEPROM |
US6886105B2 (en) | 2000-02-14 | 2005-04-26 | Intel Corporation | Method and apparatus for resuming memory operations from a low latency wake-up low power state |
US6545875B1 (en) * | 2000-05-10 | 2003-04-08 | Rambus, Inc. | Multiple channel modules and bus systems using same |
KR100335504B1 (en) * | 2000-06-30 | 2002-05-09 | 윤종용 | 2 Channel memory system having shared control and address bus and memory modules used therein |
US6446174B1 (en) | 2000-07-11 | 2002-09-03 | Intel Corporation | Computer system with dram bus |
KR100929143B1 (en) * | 2002-12-13 | 2009-12-01 | 삼성전자주식회사 | Computer and its control method |
US7539800B2 (en) * | 2004-07-30 | 2009-05-26 | International Business Machines Corporation | System, method and storage medium for providing segment level sparing |
US7389375B2 (en) | 2004-07-30 | 2008-06-17 | International Business Machines Corporation | System, method and storage medium for a multi-mode memory buffer device |
US7296129B2 (en) | 2004-07-30 | 2007-11-13 | International Business Machines Corporation | System, method and storage medium for providing a serialized memory interface with a bus repeater |
US7305574B2 (en) * | 2004-10-29 | 2007-12-04 | International Business Machines Corporation | System, method and storage medium for bus calibration in a memory subsystem |
US7299313B2 (en) | 2004-10-29 | 2007-11-20 | International Business Machines Corporation | System, method and storage medium for a memory subsystem command interface |
US7277988B2 (en) * | 2004-10-29 | 2007-10-02 | International Business Machines Corporation | System, method and storage medium for providing data caching and data compression in a memory subsystem |
US7331010B2 (en) | 2004-10-29 | 2008-02-12 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US7512762B2 (en) | 2004-10-29 | 2009-03-31 | International Business Machines Corporation | System, method and storage medium for a memory subsystem with positional read data latency |
US7395476B2 (en) | 2004-10-29 | 2008-07-01 | International Business Machines Corporation | System, method and storage medium for providing a high speed test interface to a memory subsystem |
US7356737B2 (en) | 2004-10-29 | 2008-04-08 | International Business Machines Corporation | System, method and storage medium for testing a memory module |
US7441060B2 (en) | 2004-10-29 | 2008-10-21 | International Business Machines Corporation | System, method and storage medium for providing a service interface to a memory system |
US8607328B1 (en) | 2005-03-04 | 2013-12-10 | David Hodges | Methods and systems for automated system support |
US8253751B2 (en) | 2005-06-30 | 2012-08-28 | Intel Corporation | Memory controller interface for micro-tiled memory access |
US7478259B2 (en) | 2005-10-31 | 2009-01-13 | International Business Machines Corporation | System, method and storage medium for deriving clocks in a memory system |
US7685392B2 (en) | 2005-11-28 | 2010-03-23 | International Business Machines Corporation | Providing indeterminate read data latency in a memory system |
US7636813B2 (en) * | 2006-05-22 | 2009-12-22 | International Business Machines Corporation | Systems and methods for providing remote pre-fetch buffers |
US7640386B2 (en) * | 2006-05-24 | 2009-12-29 | International Business Machines Corporation | Systems and methods for providing memory modules with multiple hub devices |
US7594055B2 (en) | 2006-05-24 | 2009-09-22 | International Business Machines Corporation | Systems and methods for providing distributed technology independent memory controllers |
US7584336B2 (en) | 2006-06-08 | 2009-09-01 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
US7493439B2 (en) | 2006-08-01 | 2009-02-17 | International Business Machines Corporation | Systems and methods for providing performance monitoring in a memory system |
US7669086B2 (en) | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
US7581073B2 (en) * | 2006-08-09 | 2009-08-25 | International Business Machines Corporation | Systems and methods for providing distributed autonomous power management in a memory system |
US7587559B2 (en) | 2006-08-10 | 2009-09-08 | International Business Machines Corporation | Systems and methods for memory module power management |
US7539842B2 (en) | 2006-08-15 | 2009-05-26 | International Business Machines Corporation | Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables |
US7490217B2 (en) | 2006-08-15 | 2009-02-10 | International Business Machines Corporation | Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables |
US7477522B2 (en) | 2006-10-23 | 2009-01-13 | International Business Machines Corporation | High density high reliability memory module with a fault tolerant address and command bus |
US7870459B2 (en) | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
US8878860B2 (en) * | 2006-12-28 | 2014-11-04 | Intel Corporation | Accessing memory using multi-tiling |
US7721140B2 (en) | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
US7603526B2 (en) | 2007-01-29 | 2009-10-13 | International Business Machines Corporation | Systems and methods for providing dynamic memory pre-fetch |
US7606988B2 (en) * | 2007-01-29 | 2009-10-20 | International Business Machines Corporation | Systems and methods for providing a dynamic memory bank page policy |
US9336387B2 (en) * | 2007-07-30 | 2016-05-10 | Stroz Friedberg, Inc. | System, method, and computer program product for detecting access to a memory device |
US8375173B2 (en) * | 2009-10-09 | 2013-02-12 | Qualcomm Incorporated | Accessing a multi-channel memory system having non-uniform page sizes |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5390308A (en) * | 1992-04-15 | 1995-02-14 | Rambus, Inc. | Method and apparatus for address mapping of dynamic random access memory |
US5701438A (en) * | 1995-09-29 | 1997-12-23 | Intel Corporation | Logical relocation of memory based on memory device type |
US5748554A (en) * | 1996-12-20 | 1998-05-05 | Rambus, Inc. | Memory and method for sensing sub-groups of memory elements |
US5799209A (en) * | 1995-12-29 | 1998-08-25 | Chatter; Mukesh | Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration |
US5913046A (en) * | 1995-10-19 | 1999-06-15 | Rambus Inc. | Protocol for communication with dynamic memory |
-
1998
- 1998-05-18 US US09/080,872 patent/US6003121A/en not_active Expired - Lifetime
-
1999
- 1999-03-03 WO PCT/US1999/004720 patent/WO1999060479A1/en active Application Filing
- 1999-03-03 DE DE19983256T patent/DE19983256T1/en not_active Ceased
- 1999-03-03 AU AU28014/99A patent/AU2801499A/en not_active Abandoned
- 1999-03-03 GB GB0027775A patent/GB2353884B/en not_active Expired - Fee Related
-
2001
- 2001-04-04 HK HK01102409A patent/HK1031931A1/en not_active IP Right Cessation
- 2001-04-04 HK HK03106048A patent/HK1053722A1/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5390308A (en) * | 1992-04-15 | 1995-02-14 | Rambus, Inc. | Method and apparatus for address mapping of dynamic random access memory |
US5701438A (en) * | 1995-09-29 | 1997-12-23 | Intel Corporation | Logical relocation of memory based on memory device type |
US5913046A (en) * | 1995-10-19 | 1999-06-15 | Rambus Inc. | Protocol for communication with dynamic memory |
US5799209A (en) * | 1995-12-29 | 1998-08-25 | Chatter; Mukesh | Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration |
US5748554A (en) * | 1996-12-20 | 1998-05-05 | Rambus, Inc. | Memory and method for sensing sub-groups of memory elements |
Also Published As
Publication number | Publication date |
---|---|
AU2801499A (en) | 1999-12-06 |
DE19983256T1 (en) | 2001-04-26 |
GB0027775D0 (en) | 2000-12-27 |
GB2353884A (en) | 2001-03-07 |
HK1053722A1 (en) | 2003-10-31 |
HK1031931A1 (en) | 2001-06-29 |
US6003121A (en) | 1999-12-14 |
GB2353884B (en) | 2003-02-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6003121A (en) | Single and multiple channel memory detection and sizing | |
US7171526B2 (en) | Memory controller useable in a data processing system | |
US4951248A (en) | Self configuring memory system | |
CN109313620B (en) | Memory protocol | |
US4926314A (en) | Method and apparatus for determining available memory size | |
US5848258A (en) | Memory bank addressing scheme | |
WO2017123413A1 (en) | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory | |
US6252821B1 (en) | Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices | |
US20110271036A1 (en) | Phased nand power-on reset | |
US4138720A (en) | Time-shared, multi-phase memory accessing system | |
US11586384B2 (en) | Overhead reduction in data transfer protocol for data storage devices | |
US6421765B1 (en) | Method and apparatus for selecting functional space in a low pin count memory device | |
EP0712083A1 (en) | Memory system comprising parallel connected memory system devices | |
WO2005010890A1 (en) | Programmable chip select | |
EP0626650A1 (en) | Devices, systems and methods for implementing a Kanerva memory | |
CN110780803A (en) | Improving read performance on SATA storage devices behind a host bus adapter | |
US7345914B2 (en) | Use of flash memory blocks outside of the main flash memory array | |
CN112513824A (en) | Memory interleaving method and device | |
US11221931B2 (en) | Memory system and data processing system | |
EP3931704B1 (en) | Accelerating access to memory banks in a data storage system | |
US6622196B1 (en) | Method of controlling semiconductor memory device having memory areas with different capacities | |
US5732280A (en) | Method and apparatus for dynamically assigning programmable option select identifiers | |
GB2380027A (en) | Single and multiple channel memory detection and sizing | |
US9678911B2 (en) | System for distributed computing and storage | |
EP0619546A1 (en) | Programmable memory controller and method for configuring same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AT AU AZ BA BB BG BR BY CA CH CN CU CZ CZ DE DE DK DK EE EE ES FI FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SK SL TJ TM TR TT UA UG US UZ VN YU ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
ENP | Entry into the national phase |
Ref document number: 200027775 Country of ref document: GB Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: KR |
|
RET | De translation (de og part 6b) |
Ref document number: 19983256 Country of ref document: DE Date of ref document: 20010426 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 19983256 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase | ||
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8607 |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8607 |