WO1999067733A1 - Hybrid circuit model simulator for accurate timing and noise analysis - Google Patents

Abstract

A system and method for analyzing timing and noise effects in a hybrid circuit which contains a plurality of electrical components (201, 203, 205). The timing and noise effects for the hybrid circuit are generated by simulating electrical conditions within a hybrid circuit model (223). The hybrid circuit model is constructed by creating and integrating analog and behavioral models from a plurality of electrical components (219). The timing and noise effects remain accurate even at high printed circuit/multi-chip module clock speeds, thereby ensuring that a user is able to construct an optimal design for any one of the plurality of electrical components.

Description

HYBRID CIRCUIT MODEL SIMULATOR FOR ACCURATE TIMING

AND NOISE ANALYSIS

BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuit design, and more particularly to a system and method for analyzing analog characteristics of an integrated circuit design.

DESCRIPTION OF BACKGROUND ART

In designing an integrated circuit chip (source chip), the source chip design effectively must interact with a plurality of integrated circuit chips (target chips), which, like the source chip are electrically coupled to a printed circuit board (PCB)/multi-chip module (MCM). Typically, a conventional analog simulation software tool, such as SPICE, is used to attempt to identify an optimal design for the source chip. Prior to initiating the SPICE simulation, however, the logic design (package) and the input/output (I/O) pin configuration (I/O ring) of each integrated circuit chip as well as the PCB/MCM is transformed into at least one analog circuit model. In addition, input stimuli and specific routes (output circuit blocks) between the I/O ring of the source chip and the I/O ring of the target chips must be defined.

Based upon the SPICE simulation results, the performance of the source chip design can be analyzed and alterations to the source chip design can be made. When the source chip design is altered, a new analog circuit model is generated and a new SPICE simulation is executed. The new performance results again are analyzed and a decision must again be made as to whether the source chip design must be further modified. Prior to finalizing the design of the source chip, several iterations of redesigning and resimulating the source chip design may be performed.

Even though conventional SPICE simulations are relatively helpful for optimizing the performance of the source chip with regard to the PCB/MCM and the target chips, SPICE still possesses certain limitations, which preclude the optimal design of a source chip from truly being realized. Utilizing an ideal analog circuit analysis tool, a conventional system would be able to simulate in its entirety a single integrated analog circuit model, which included the source chip, the target chips and the PCB/MCM. Unfortunately, since conventional analog simulation tools, such as SPICE, can only simulate circuits with approximately 10,000 transistors, typical analog circuit models, which contain well above that number of transistors, cannot be analyzed as a whole. Rather, a conventional system must deconstruct the analog circuit model into smaller discrete sub-components, which each are separately simulated. The results of each of these simulations then are interpolate to determine the overall performance characteristics of the combined analog circuit model, which result in the development of the optimal source chip design. Unfortunately, with interpolative techniques having inherent inaccuracies, the optimal source chip design is not usually fully realized.

Another limitation with simulating a combined analog circuit model is that in addition to not being able to simulate all of the components of an analog circuit model together, the user also cannot solely rely upon SPICE simulations for real-time circuit analysis of certain integrated circuits, such as the target chips. For example, since the source chip often is designed at the same time as the target chips, the attempt to construct an optimal source chip design must be accomplished without full information regarding the target chips. Since SPICE simulations require extensive information concerning the design of the integrated circuit chip, an alternative software simulation tool, which relies upon behavioral circuit models, such as Input/Output (I/O) Buffer Information Specification (IBIS), must be used to approximate the final design of the integrated circuit chips, which have not yet been fully designed.

One such conventional software simulation package, which approximates real-time conditions of IBIS behavioral circuit models, is the BoardQuest by Cadence Design System of San Jose, California. Such conventional IBIS-based simulators rely upon an electronic lookup table, rather than upon the physical layout design of the chip, to simulate a behavioral circuit model with specific current and voltage I/O behavioral characteristics. Like SPICE, after an IBIS-based simulator constructs the circuit model, specific input stimuli is defined in order for the output results to be generated. Unlike SPICE, however, the IBIS-based simulator does not directly take into consideration the PCB/MCM. Rather, the focus is upon predefined I/O behavioral characteristics of the target chip. Any PCB/MCM effects upon the source chip or the target chips must be approximated by integrating estimate voltage and current I/O behavioral characteristics into the source chip or the target chip behavioral circuit models. Such rough approximations of the interaction of the PCB/MCM with the source chip and target chips further add to the inaccuracy of the output results of the simulation.

Additionally, as the clock speed of the PCB/MCM increases, the IBIS-based simulator is unable to adequately compensate for the source chip and the target chips becoming more sensitive to noise and timing problems. Should the IBIS-based simulations be attempted at PCB/MCM speeds above approximately 100 MHz, IBIS-based simulations will fail to produce satisfactory results that account for such subtle, but influential analog effects as simultaneous switching noise, ground bounce, signal integrity and timing issues. Furthermore, since IBIS- based circuit models and SPICE circuit models are incompatible, the limitations of IBIS-based simulators cannot be circumvented by utilizing SPICE to simulate IBIS-based behavioral models. Without these subtle high speed analog effects included within the software simulation of the behavioral circuit model, the results of these higher clock speed simulations results in merely idealized results, which do not reflect real-time effects on the source chip.

To ensure more accurate simulation results for designing an optimal source chip, what is needed is a system and method for more accurately simulating the behavioral and analog characteristics of the source chip integrated with the PCB/MCM and the target chips including the timing and noise effects which are attributable to high speed PCB/MCM clock speeds.

SUMMARY OF THE INVENTION Accordingly, the present invention provides a method and system for analyzing the operation of a source chip design in conjunction with the PCB/MCM and the target chips through the construction and simulation of a hybrid circuit model. In this manner, the operation of each component of the circuit model, including the source chip and the associated PCB/MCM and target chips, can be jointly observed, measured, and adjusted during the design process of each component.

In order to accomplish such a simulation, it is useful to extract the essential analog characteristics of the PCB/MCM and the source chip and construct a hybrid circuit model framework. A plurality of target chip behavioral models then are integrated with the hybrid circuit model framework to create the hybrid circuit model. A software simulation tool then accurately measures and analyzes the hybrid circuit model for real-time conditions, which will assist in optimizing the source chip.

Unlike previous attempts at analyzing the combined circuit model, the simulation of the hybrid circuit model account for, even at high PCB/MCM clock speeds, the following electrical characteristics: 1) timing effects, including intra- and inter-component delays for various PCB/MCM components, 2) noise effects, including ground bounce, reflections, crosstalks and other effects that may be generated by the interaction of various PCB/MCM components, and 3) signal integrity and degradation.

With such factors considered by this method, the optimal design for the source chip can more easily be realized. Even without complete information as to the target chips, the present invention still is able to utilize both behavioral and analog models to obtain more accurate electrical characteristics of the combined circuit. Furthermore, as the clock speed of the PCB/MCM increases, the present invention, unlike conventional systems and methods, can accurately obtain performance characteristics which will ensure that the source chip is optimally designed for the PCB/MCM and the target chips. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is an illustration of a computer system in which a preferred embodiment operates.

Figure 2 is an embodiment of the HCM simulator for generating and analyzing a hybrid circuit model in accordance with a preferred embodiment.

Figure 3 is an illustration of the PCB/MCM modeler module of Figure 2 in accordance with a preferred embodiment.

Figure 4 is an illustration of the source chip modeler of Figure 2 in accordance with a preferred embodiment. Figure 5 is an illustration of the target chip modeler module of Figure 2 in accordance with a preferred embodiment.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENTS

A preferred embodiment of the present invention is now described with reference to the figures where like reference numbers indicate identical or functionally similar devices. Also, in the figures, the left most digits of each reference number correspond to the figure in which the reference number is first used.

A preferred embodiment of the present invention is directed to a method and system for simulating the operation of a source chip design in conjunction with the PCB/MCM and the target chips. In this manner, the operation of each component of the circuit model, including the source chip and the associated PCB/MCM and target chips, can be analyzed and adjusted during the design process of each component. In order to accomplish such a simulation, the essential analog characteristics of the PCB/MCM and the source chip and the behavioral characteristics of the target chip must be integrated into a single hybrid circuit model. A software simulation tool then analyzes the hybrid circuit model for real-time conditions, which reflect the performance level of each component. Unlike conventional systems, the present invention accounts for, even at high PCB/MCM clock speeds 1) the timing effects, including intra- and inter-component delays for various PCB/MCM components, 2) the noise effects, including ground bounce, reflections, crosstalks and other effects that may be generated by the interaction of various PCB/MCM components, and 3) the signal integrity and degradation.

Figure 1 is an illustration of a computer system 100 in which a preferred embodiment operates. The system 100 includes an input device 104, a central processing unit (CPU) 108, a display 106, a printer 110, a storage device 112 and a random access memory (RAM) 116. The CPU 108 is coupled to the input device 104, the display monitor 106, the printer 110, the storage device 112 and the RAM 116. During computer operation, the RAM 116 includes an operating system 118, e.g., UNIX, and the hybrid circuit model simulator 150. The input device 104, CPU 108, display 106, printer 110, and mass storage 112 all are part of a conventional computing system, e.g., a Sun Micro Workstation. In alternative embodiments the computer system also is coupled to a network 114.

Figure 2 is a more detailed illustration of the hybrid circuit model (HCM) simulator 150 according to a preferred embodiment. The HCM simulator 150 comprises, a PCB/MCM modeler module 201, a source chip modeler module 203, a target chip modeler module 205, an integrator preprocessor module 213, an integrator module 219, a simulator module 223, an analyzer module 239, a timing processor module 225 and a waveform processor module 227. In a preferred embodiment, to initiate the processing and simulating of the circuit information relating to the source chip, the target chip and the PCB/MCM, the user executes a PERL script within UNIX, entitled OBAT, which is attached to the appendix.

The PCB/MCM modeler module 201 generates a PCB/MCM analog circuit model to symbolically represent the analog characteristics of the physical layout of the PCB/MCM design. In a preferred embodiment, the PCB/MCM analog circuit model is a SPICE netlist. The source chip modeler module 203 generates a source chip analog circuit model to symbolically represent the analog characteristics of the physical layout of the source chip design. In a preferred embodiment, the source chip analog circuit model is a SPICE netlist. The target chip modeler module 205 generates a plurality of target chip behavioral circuit models to symbolically represent the behavioral characteristics of the electrical and functional specifications of each of the plurality of target chips. In a preferred embodiment, the behavioral circuit models are analog high-level description language (AHDL) models.

The integrator preprocessor module 213, coupled to the PCB/MCM modeler module 201 and the source chip modeler module 203, assembles the PCB/MCM analog circuit model and the source chip analog circuit model into a hybrid circuit model framework. In a preferred embodiment the hybrid circuit framework is a SPICE netlist.

The integrator module 219, coupled to the integrator preprocessor module 213 and the target chip modeler module 205, constructs a hybrid circuit model by integrating the target chip behavioral circuit model into the hybrid circuit model framework. The simulator module 223, coupled to the integrator module 219, provides user-defined input stimuli to the hybrid circuit model and generates analog and digital output results. The analyzer module 239 summarizes the minimum and maximum timing delays from the source chip to the target chip. The timing processor module 225 coupled to the analyzer module 239, generates standard delay format (SDF) files, which contain source chip and target chip delay timing information. The waveform processor module 227, coupled to the simulator, transforms the output results from the simulator module 223 into individual noise waveform signals for each critical signal within the hybrid circuit model.

If the timing effects and noise effects are not within a predefined range, which represents the optimum design for the source chip, the source chip design will be altered, a new hybrid circuit model will be constructed and a new simulation for generating new timing and noise effects will be executed. The HCM simulator 150 can perform numerous iterations of redesigning and reanalyzing the source chip design until the timing effects and noise effects are within the intended range of values. In a preferred embodiment, the redesigning of the source chip is manually performed by the chip designer.

Figure 3 is a more detailed view of the PCB/MCM modeler module 201 of figure 2. In particular, the PCB/MCM modeler module 201 includes a PCB/MCM preprocessor module 305, an extractor module 320 and a joiner module 319. From PCB/MCM interconnect information and a PCB/MCM trace symbol library, the PCB/MCM preprocessor module 305 creates a physical layout schematic of the PCB/MCM. In a preferred embodiment, the PCB/MCM preprocessor module 305 is part of a commercial software package such as Unisolve by Unicad of Ontario, Canada.

The extractor module 320, coupled to the PCB/MCM preprocessor module 305, includes a signal processor module 311 and a PCB/MCM processor module 315. Since the PCB/MCM physical layout schematic usually contains over the maximum number of transistors that the PCB/MCM processor 315 can process at any one time, the signal processor 311 deconstructs the PCB/MCM physical layout schematic into a plurality of subgroups of PCB/MCM transmission line signals. Once the size of the number of transistors is reduced to a manageable level, the PCB/MCM processor 315 then extracts a parasitic SPICE netlist from each of the plurality of sub-groups of PCB/MCM transmission line signals to create corresponding PCB/MCM analog circuit sub-models. In a preferred embodiment, the extractor module 320 is a software modeling tool such as Unisolve by Unicad of Ontario, Canada, which generates raw extraction files that represent the PCB/MCM analog circuit submodels for the PCB/MCM. Once the plurality of PCB/MCM analog circuit sub-models are constructed, a joiner module 319 combines the plurality of PCB/MCM analog circuit sub-models to create a composite PCB/MCM analog circuit model. In a preferred embodiment of the present invention, the joiner module 319 is two PERL software scripts executed in the UNIX operating system. OBATunicadjoin is a PERL script, which is used to join all of the separate files from the extraction process. OBATpcb is a PERL script that rearranges the file for the integrator preprocessor 213. Both of these scripts are attached to the appendix. As was previously discussed with regard to conventional systems, by deconstructing a circuit model, inaccuracies in the simulation of the circuit model occur. In a preferred embodiment, however, since the PCB/MCM is the only aspect of the circuit model, which is deconstructed, and the PCB/MCM is the least complex aspect of the hybrid circuit model, the errors, which are introduced by the deconstruction and reconstruction of the PCB/MCM circuit model results in only slight inaccuracies in the final results generated by simulating the hybrid circuit model. Referring now to figure 4, the source chip modeler module 203 includes a source chip preprocessor 401, a library generator 403, a source chip processor 407 and a schematic manager 415. The source chip preprocessor 401 receives a pin location table, which provides the I/O circuit placement information for the source chip, parasitic information of the package and configured I/O data for specific functions. In a preferred embodiment, the parasitic information of the package is generated from an electronic package drawing by a commercial software package such as TurboPackage by Pacific Numberix of Scottsdale, Arizona. The source chip preprocessor 401 uses the pin location table to construct a uniform format for the table, which reflects the aspects of the schematic relating to the source chip I/O ring. In a preferred embodiment, this procedure is executed in the UNIX operating system by a software PERL script entitled OBATplt, which has been attached to the appendix. The parasitic package parameter table is transformed by the source chip preprocessor 401 into a package parameter table file, which reflects the aspects of the schematic relating to the bonding wires and package parasites associated with each pin. In a preferred embodiment, this procedure is executed in the UNIX operating system by a software PERL script entitled OBATpnc2pak, which has been attached to the appendix. The I/O data is configured to reflect the function of each I/O cell. In a preferred embodiment, this procedure is executed in the UNIX operating system by a software PERL script entitled OBATio, which has been attached to the appendix. By simplifying a plurality of circuit blocks for the source chip I O schematic with identifiers, the source chip preprocessor 401 is able to reduce the size of the final source chip analog circuit model without having to deconstruct the model, thereby ensuring the highest efficiency and the most accurate timing and noise effects in the hybrid circuit model simulation. In particular, the source chip preprocessor 401 identifies and replaces a plurality of I/O cell sub-circuits in the source chip I/O schematic with subcircuit library identifiers. The source chip preprocessor 401 also modifies the cell parameters directly from the schematic to set up default parameters for simulation purposes. Lastly, the source chip preprocessor 401 configures the source chip I/O functions, such as the input, output or tri-state characteristics, through modifying simple configuration files.

The library generator 403, which is coupled to the source chip preprocessor 401 and the integrator preprocessor module 213, receives a flat SPICE compatible netlist, which reflects the transistor level of the I/O design, and performs cell library characterization upon the I/O cell subcircuits to create a source chip sub-circuit library with each I/O cell sub-circuit associated with a sub-circuit library identifier. In a preferred embodiment, the library generator 403 is comprised of a PERL script executed by the UNIX operating system, entitled OBATlib, which is attached to the appendix.

After both the source chip sub-circuit library and the source chip I/O schematic are generated, the source chip processor 407 generates a source chip analog circuit model from the source chip I O schematic by extracting a SPICE netlist. In a preferred embodiment, the source chip modeling processor 407 is a PERL software script executed by UNIX, entitled OBATsch and OBATconfigure, which are attached to the appendix. To graphically present the source chip analog circuit model for possible manual alterations by the chip designer, a schematic manager module 415 receives and displays a graphical representation of the source chip analog circuit model. In a preferred embodiment, the schematic manager module 415 is a commercial software package such as Powerview by Viewlogic System Inc. of Marlborough, Massachusetts.

Once the source chip analog circuit model is finalized, the integrator preprocessor module 213, which is coupled to the PCB/MCM processor 201 and the source chip processor 203, integrates the source chip analog circuit model with the PCB/MCM analog circuit model by utilizing the source chip sub-circuit library and pin names. The final composite analog circuit (hybrid circuit model framework) is a netlist. In a preferred embodiment, the integrator preprocessor module 213 is a commercial software package such as WSPICE by Viewlogic Systems, Inc. of Marlborough, Massachusetts. Referring now to figure 5, the target chip modeler module 205 includes a target chip translator module 503 and a target chip processor module 507. As previously discussed, if the vendor is unable to provide the completed target chip designs because the target chips are being designed at the same time as the source chip, behavioral models are used. In the conventional system, the use of behavioral models were problematic because IBIS behavioral models were incompatible with analog circuit models, thereby precluding the generation of an integrated hybrid circuit model. Without the integrated hybrid circuit model, the convention system experienced inherent inaccuracies due to having to interpolate how the IBIS behavioral models interacted with the analog circuit models. In a preferred embodiment, by utilizing electrical and functional target chip information to generate an analog high-level description language (AHDL) behavioral circuit model, which is compatible with analog (SPICE-based) circuit models, more accurate results are achieved because the behavioral circuit model can be integrated into the hybrid circuit model. AHDL is a high-level description language, which encapsulates high-level behavioral descriptions of integrated circuits without requiring knowledge of the low-level circuit schematic of the integrated circuit. In particular, AHDL is a functional description text file, which mathematically describes the input and output terminal behavior of the electrical circuits in terms of the connections, the parameters and the relationships between the integrated circuits.

If only an IBIS model of the target chip is available, the target chip translator 503, which is coupled to the integrator module 219, will convert the target chip behavioral model from the IBIS format to the AHDL format. In a preferred embodiment, the target chip translator module 503 and the target chip processor module 507 are part of the same PERL software script executed by UNIX, entitled obat4.mod, which is included in the appendix. The integrator module 219, which is coupled to both the target chip modeler module 205 and the integrator preprocessor module 213. constructs the hybrid circuit model by integrating each of the target chip behavioral circuit models with the hybrid circuit model framework and then converting this composite netlist into a worst case and a best case scenario hybrid circuit model. In a preferred embodiment, the integrator module 219 is a PERL software script executed by UNIX, entitled OB AT splits, which is attached to the appendix. In addition, the hybrid circuit model is in a format, which can be simulated by a commercial software package such as Spectre by Cadence Design System of San Jose, California.

Referring back to figure 2, the simulator module 223, which is coupled to the integrator 219, receives the hybrid circuit model and integrates device models, a plurality of circuit monitoring blocks, and the highest and lowest current and voltage input levels into the hybrid circuit model. The device models define the low-level properties of each transistor within the source chip. The circuit monitoring blocks identify the specific routes to be monitored between pins on the source chip and pins on the target chips. From this information, the simulator module 223 generates real-time output results for the hybrid circuit model, which include timing effects and noise effects. In a preferred embodiment, the simulator module 223 is another functional aspect of a software simulation package such as Spectre manufactured by Cadence Design System of San Jose, California.

The analyzer module 239, which is coupled to the simulator module 223, receives the output results for the best and worst case scenarios of the hybrid circuit model simulations and summarizes the minimum and maximum timing delays from the source chip to the target chips. In a preferred embodiment, the output results can be converted into HTML format and viewed on a web browser such as Netscape Communicator by Netscape Communication Corporation of Mountain View, California by utilizing a PERL script, executed by UNLX, entitled OBATsim2html, which is attached to the appendix.

The analyzer module 239 also will check if certain pre-defined requirements are met. Should the output results not fall within these predefined values, the source chip design is altered and a new simulation of the new hybrid circuit design is performed. By proceeding through possibly several iterations of redesigning the source chip design and simulating the operation of the new source chip design in conjunction with the PCB/MCM design and the target chip designs, an optimal design for the source chip can be better achieved. In a preferred embodiment, the analyzer module 239 is a PERL executed by UNIX, entitled OBAT summary, which is attached to the appendix.

The timing processor module 225, which is coupled to the analyzer module 239, converts the timing effects into a standard delay format (SDF) file, which contains source chip to target chip delay timing information. This timing information is embedded into logic behavior models (VHDL) for accurate system level verifications by a VHDL logic simulator (not shown). For example, the VHDL logic simulator utilizes this timing information to generate a board-level logic simulation. Since the timing information from the source chip to the target chip is embedded in the library, no estimations of the loading of the signals on the PCB/MCM are needed in order to successfully perform such board-level simulations. In a preferred embodiment, the timing processor module 225 is a PERL script executed by UNIX, entitled OBATsdf_wln, which is attached to the appendix.

The waveform processor module 227, which is coupled to the simulator 223, formats the noise effects results into individual files, which reflect each critical signal. These individual files then are generated into waveform plots. In a preferred embodiment, the waveform processor module 227 is two PERL script executed by UNIX, entitled OBATtran2dats and OBATprints, which are attached to the appendix.

Having described the present invention with reference to a specific embodiment, the above description is not meant to limit the scope of the invention. For example, the PCB/MCM design or the target chip designs, rather than the source chip design, can be the sole or joint focus of the simulations and the subsequent design iterations. Furthermore, as previously discussed, the scope of the invention is to be limited only by the following claims. From the above discussion, many variations will be apparent to one skilled in the art that would yet be encompassed by the true spirit and scope of the present invention.

APPENDIX OBAT

# ! /USR/LOC AL/BIN/PERL5 5 #

################ SET UP THE ARGUMENT INTERFACE FOR THE OBAT #### IF(S#ARGV+1 != 6)

{

PRINT"USAGE:$0 DESIGN_NAME PROCESSED DESTINATION_DIRECTORY

/ 0 PIN_LOCATION_FILE PACKAGE_FILE CONFIGURE_FILE \N\N" ;

PRINT"EXAMPLE::SO GX3 UMC025 ./ GX3.PLOC.REV5 GX3.PL0C.PACKAGE GX3. CONFIGURE

\N"; EXIT(l);

} 15 $DSN_NAME = $ARGV[0]; # DESIGN NAME

SPROCESSID = $ARGV[1]; # PROCESS ID

$DST_DIR = $ARGV[2] ; # DESTINATION DIRECTORY NAME #

#GET RID OF THE EXTRA "/" IF EXISTING IN THE DST_DIR NAME' 20 #

IF( ($CHK= SUBSTR($DST_DIR, -1 , 1)) EQ "/")

{

SUBSTR($DST_DIR, -1, 1) = "";

} 25 $PLT_FILE = $ARGV[3] ; # PIN LOCATION FILE

$PACK_FILE = $ARGV[4]; # PACKAGE PARAMETER FILE

$CONF_FILE = $ARGV[5]; # CONFIGURE FILE

#

$OBATVIEWLOGIC="/NFS/PROTON/HOME/S3LIB/VIEWLOGIC/OBAT"; 30 $OBATBlN="/NFS/PROTON/HOME/S3Lffi/OBAT/BIN";

$PLT2θBATPLT="$OBATBIN/OBATPLT";

$IOGEN="$OBATBIN/OBATlO";

$SCHGEN="$OBATBIN/OB ATSCH" ;

$CONFIGURE="$OBATBIN/OBATCONFIGURE" ; 5 #

STIMESTAMP=&GETTIMESTAMP;

PRINT " M i l 14 I I I M I I I I I 1 OBAT PREPARATION SCRIPT VER. 2.1

+ 1 I 1 I 1 1 1 I I I I 1 1 I I ++++\N";

PRINT "+++ +++\N";

40 PRINT "+++++++ 1 I hi I 1 - ENHANCED VERSION I I 1 I I I I I I 1 I I I I I I I I I l \N";

PRINT "+++ $TIMESTAMP +++\N";

PRINT "+ 1 I I I I I I 1 I I I I I I I I I I I I I I 14 I 1 +++ I I I I 1 1 I I +-H- I I I I l -H I I I I I I M--I 1 I 1 + 144 I I

-H-H-\N";

45

PRINT "+++ CHECK THE DIRECTORY \N";

$C_WD = ^'PWD^';

PRINT "+++ CURRENT WORKING DIRECTORY IS $C_WD \N";

50

## THE NEWLY GENERATED DIRECTORY NAMES $SCH = $DST_DIR . "/SCH"; $SYM = $DST_DIR . SYM"; $ANALYSIS = $DST_DIR . "/ANALYSIS";

JJ

IF (OPENDIR(DΓR, SSCH)) { CLOSE(DIR); }ELSE {

PRINT "+++ THE DIRECTORY SCH DOES NOT EXIST. I WILL CREATE IT FOR

YOU \N"; IF( (SRTN = SYSTEM("MKDIR SSCH")) != 0)

{

PRINT "MKDIR $SCH FAIL, PROGRAM ABORT ...". EXIT(l);

} }

IF (OPENDIR(DIR, SSYM)) {

CLOSE(DIR); }ELSE {

PRINT "444- THE DIRECTORY SYM DOES NOT EXIST. I WILL CREATE IT FOR YOU \N";

IF( ($RTN = SYSTEM("MKDIR $SYM")) != 0)

{

PRINT "MKDIR $SYM FAIL, PROGRAM ABORT ..."; EXIT(l); }

}

IF (OPENDIR(DLR, $ANALYSIS)) {

CLOSE(DIR);

}ELSE { PRINT "444- THE DIRECTORY ANALYSIS DOES NOT EXIST. I WILL CREATE IT FOR

YOU \N";

IF( ($RTN = SYSTEM("MKDIR SANALYSIS")) != 0)

{

PRINT "MKDIR SANALYSIS FAIL, PROGRAM ABORT ... \N"; EXIT(l);

}

PRINT "MKDIR ANALYSIS \N";

}

IF (!(-E "$DST_DIR/VIEWDRAW.INI")) { PRINT "444- THE FILE VIEWDRAW.INI DOES NOT EXIST, I WILL COPY IT FOR YOU. \N";

IF (SPROCESSID =~ /025/ ) {

$VIEWDRAWINI="$OBATVIEWLOGIC/VIEWDRAW.rNI_025 " ; } ELSIF (SPROCESSID =~ /022/) { $VIEWDRAWINI="$OBATVIEWLOGIC/VIEWDRAW.INI_025";

} ELSIF (SPROCESSID =~ /031/) {

$VffiWDRAWIM="$OBATVIEWLOGIC/VIEWDRAW.INI_031 " ; } ELSIF (SPROCESSID =~ /035/) {

$VIEWDRAWINI="$OBATVIEWLOGIC/VIEWDRAW.INI_035"; } ELSIF (SPROCESSID =~ /018 ) {

$VIEWDRAWΓNI="$OBATVIEWLOGIC/VIEWDRAW.INI_018";

}

IF( ($RTN = SYSTEM(" CP SVIEWDRAWINI $DST_DIR/VIEWDRAW.INI")) != 0) {

PRINT" CP SVIEWDRAWINI $DST_DIR/VIEWDRAW.INI FAIL, ABORT ...\N";

EXIT(l);

} }

IF (!(-E "$DST _DIR/SAMPLE.CONFIGURE")) {

PRINT "-H→ THE FILE SAMPLE.CONFIGURE DOES NOT EXIST, I WILL COPY IT FOR YOU.

.AN"; PRINT "44-t- SAMPLE.CONFIGURE IS USED FOR REFERENCE ONLY! N";

IF( (SRTN = SYSTEM(" CP SOBATBIN/SAMPLE.CONFIGURE $DST_DIR/")) != 0)

{

PRINT" CP SOBATBIN/SAMPLE.CONFIGURE $DST_DIR/ FAIL, ABORT ...\N";

#EXIT(1);

}

}

#PRINT "PLEASE ENTER NAME OF THE PIN LOCATION TABLE \N";

#SFILENAME=&GETFILENAME; tr

# OBAT.PLT FILE IS AN EXTERNAL FILE GENERATED FROM ORIGINAL PIN LOCATION FILE

#

SOBATPLT="$DST_DIR/OBAT.PLT"; PRINT" RUNNING OB ATPLT .. N";

IF ( (SRTN = SYSTEM("$PLT20BATPLT SPLT JFILE > SOBATPLT")) != 0)

{

PRINT" [SUBPROGRAM $PLT2θBATPLT FAILD FOR PREVIOUS REASONS, PLEASE CHECK

OUT, ABORT ... \N"; EXIT(l);

}

SPINCOUNT=&PINCOUNT($OBATPLT) ; PRINT "THERE ARE SPINCOUNT PINS DEFINED IN THE FILE!\N"; $SCHFILE=$DSN_NAME; $IOGENCMD="$IOGEN SPROCESSID SOBATPLT $PACK_FILE $DST_DIR SSCHFILE" ; IF( (SRTN = SYSTEM("$SCHGEN SPROCESSID SOBATPLT SSCHFILE $DST_DIR")) != 0)

{

PRINT" SUBPROGRAM SSCHGEN FAILD FOR PREVIOS REASON, PLEASE CHECK OUT, ABORT ... \N"; EXIT(l);

}

$IOGENCMD="$IOGEN SPROCESSID SOBATPLT $PACK_FILE $DST_DIR SSCHFILE";

PRINT SlOGENCMD;

IF ( (SRTN = SYSTEM(SIOGENCMD)) != 0) {

PRINT " SUBPROGRAM SIOGEN FAILD FOR PREVIOUS REASON, PLEASE CHECK OUT,

ABORT ... \N"; EXIT(l);

} #PRΓNT "PLEASE ENTER NAME OF THE CONFIGURATION FILE \N" ;

#$FILENAME=&GETFILENAME;

SFILENAME = $CONF_FILE;

IF( (SRTN = SYSTEM("$CONFIGURE SPROCESSID SFILENAME SSCHFILE.1 $DST_DIR")) != 0)

{ PRINT" SUBPORGRAM SCONFIGURE FAILD FOR PREVIOUS REASON,PLEASE CHECK

OUT, ABORT ... \N"; EXIT(l);

}

IF( (SRTN = SYSTEM("CP $OBATVIEWLOGIC/SYM/PCB_MACR0.1 SSYM/PCB_MACRO.1 ")) != 0) {

PRINT"CP SOBATVIEWLOGIC/SYM/PCB_MACR0.1 $SYM/PCB_MACR0.1 FAILD, ABORT ..\N";

EXIT(l);

} IF( (SRTN = SYSTEM("CP $0BATVIEWL0GIC/SYM/PCB_MACR0.M0D SSYM/PCB_MACRO.MOD")) != 0) { PRLNT"CP SOBATVIEWLOGIC/SYM/PCB_MACRO.MOD SSYM/PCB_MACRO.MOD FAILD, ABORT .AN";

EXIT(l );

} IF( (SRTN = SYSTEM("CP $OBATVIEWLOGIC/SCH/SAMPLE.2 SSCH/$SCHFILE.2")) != 0)

{

PRINT"CP SOBATVIEWLOGIC/SCH/SSCHFILE.2 SSCH/$SCHFILE.2 FAILD. ABORT ..\N"; EXIT(l);

} IF( (SRTN = SYSTEM("CP SθBATVIEWLOGIC/SCH/SAMPLE.3 SSCH/SSCHFILE.3")) != 0)

{

PRTNT"CP SOBATVIEWLOGIC/SCH/SSCHFILE.3 $SCH/$SCHFILE.3 FAILD, ABORT .AN";

EXIT(l); } IF( (S TN = SYSTEM("CP $OBATVIEWLOGIC/SCH/SAMPLE.4 SSCH/SSCHFILE.4")) != 0)

{

PRINT"CP SOBATVIEWLOGIC/SCH/$SCHFILE.4 SSCH/SSCHFILE.4 FAILD, ABORT ..\N"; EXIT(l);

} IF( (SRTN = SYSTEM("CP SOBATVIEWLOGIC/SYM/SIGLOAD.1 SSYM SIGLOAD.1 ")) != 0)

{

PRINT"CP SOBATVIEWLOGIC/SYM/SIGLOAD.1 SSYM/SIGLOAD. l FAILD, ABORT ..\N";

EXIT(l);

} IF( (SRTN = SYSTEM("CP $OBATVIEWLOGIC/SCH/SIGLOAD.1 SSCH/SIGLOAD.1 ")) != 0)

{

PRINT"CP SOBATVIEWLOGIC/SCH/SIGLOAD. l $SCH/SIGLOAD.l FAILD, ABORT ..\N";

EXIT(l);

}

#

SUB GETFILENAME { LOCAL SFILE; LOCAL $CORRECT=l ; WHILE($CORRECT=l) {

PRINT "FILENAME: ";

CHOP($FILE = <STDIN>);

LAST IF ! SFILE;

IF (! -E SFILE) { PRINT "THE FILE: Y'SFILEV DOES NOT EXIST. PLEASE ENTER AGAIN AN" ;

$CORRECT=l ;

}

ELSE {

SCORRECT=0; }

}

RETURN SFILE;

}

# SUB GETNAME { LOCAL SFILE; LOCAL SCORRECT=l ;

PRINT "FILENAME: "; CHOP($FILE = <STDLN>); LAST IF ! SFILE;

RETURN SFILE;

}

# SUB GETTIMESTAMP {

($SEC,SMIN,$H0UR,$MDAY,SM0N,$YEAR,$WDAY,$YDAY,$ISDST) = LOCALTIME (TIME); $MON=$MON+l ;

IF (LENGTH ($MON) EQ 1) {$MON="0$MON" ;} IF (LENGTH ($MDAY) EQ 1 ) {SMDAY- 'OSMDAY" ;} IF (LENGTH ($HOUR) EQ 1 ) {$HOUR="OSHOUR" ;} RETURN "$MON/$MDAY/SYEAR $H0UR:SMIN:$SEC" ;

} #

SUB LINECOUNT{ LOCAL($FILENAME)=@_;

OPEN (IN, SFILENAME); SLINENUM = 1 ;

WHILE (<IN>) {

SLINENUM44-;

} CLOSE IN; SLINENUM; }

SUB PΓNCOUNT { LOCAL($FILENAME)=@_;

OPEN (IN, SFILENAME); SLINENUM = 0;

FOREACH SLINE (<IN>) {

(SLINE =~ Λs#(.*)$/ι) && (!($l =~ /B/i)) && (SOUTPUT = Sl) && (SLINENUM44-)_; # PRINT "OUTPUT=$OUTPUT\N";

}

CLOSE IN; SLINENUM;

} #

OBATunicadjoin

#!/usr/local/bin/perl5

# # Strip the driver stimilus and loading at the terminals

#

# Usage:

# OBATunicadjoin # #

Sobat jcb_sym="/nfs/proton home/s31ib/viewlogic/obat/sym obat_pcb.1 " ;

Sobat_pcb_sch='7nfs/proton home/s31ib/viewlogic/obat sch/pcb_4mb.1 " ;

Sobat_pcb_sch_2="/nfs/proton/home/s31ib/viewlogic/obat/sch/pcb_sodiml44.1 "; open(GETLIST,"<pcb_spice/list") || die "can not open $ARGV[$i] file\n"; @list=<GETLIST>; close (GETLIST); foreach Sline (@list) { chop Sline;

@nametable=split(" ", Sline); $lookups{Snametable[0]}=$nametable[l];

}

Slookups {"PCB_GND" } ="PCB_GND" ;

$lookups{"PCB_V2"}="PCB_VCC"; Slookups {"PCB_VC2"}="PCB_VCC"; $lookups{"PCB_VC3"}="PCB_VCC"; Slookups {"PCB_VEE" }="PCB_VCC"; $lookups{"PCB_VCC"}="PCB_VCC"; $headertempe='7tmp/headertemp$$"; $btemρ='7tmp/btemp$$"; $atemp='7tmρ/atemp$$"; $tempfile="/tmp/temp$$" ; $howmany=S#ARGV4-l ; print "There are total of Showmany spice files to be combined l\n";

#~Read in the netlist file from Unicad and analyze undef(@siglist); for ($i=0; Si < Showmany; $i++) { print "circuit file= $ARGV[$i]\n"; open(GETCIR,"<pcb_spice/$ARGV[$i].spice") || die "can not open $ARGV[$i] fileW;

1=/ ;

:

print "New Nodes= @siglist \n"; } elsif (Sline =~ ΛA(X|F|E|M|V|R|C|M)/i) { @elements=split(" ",Sline); Sfirst 1 =@elements[0] ; Sfirst2=$fιrstl . "SBSi";

Sline =~ s/$firstl/Sfirst2/ ; print BTMP Sline; } elsif (Sline =~ ΛAT/i) {

@elements=split(" ",Sline); $ first l=@elements[0];

Sfirst2=$fιrstl . "SBSi"; Sline =~ s/$fιrstl/$first2/ ; Sline =~ s/$elements[4]/$elements[4] tline/ ; print BTMP Sline; } elsif (Sline =~ ΛA.option/i) {

} elsif ($line =~ ΛA.ends\b/i) { hτ^*G3κ "

} elsif (Sline =~ ΛA\+/) { print BTMP Sline; } else { print BTMP Sline;

} } } print BTMP ".ENDS\n"; close(BTMP); @slist=sort(@siglist); undef(@newlist); Sprevious- "'; foreach Sany (@slist) { if ((Sany ne Sprevious) && (Sany ne "")) {push(@newlist,$any); }

Sprevious=Sany;

} #$subckt=join(" ",".SUBCKT PCB_MACRO", @newlist,"\n");

$no=@newlist;

Ssubckt=".SUBCKT PCB_MACRO "; print "Total number of the pick up points= Sno\n"; for ($i=0; Si < Sno; $i++) { if ((Si % 7) = 0) {$subckt=join(" ",Ssubckt , "\n+", @newlist[Si]);} else {$subckt=join(" ", Ssubckt , @newlist[$i]);}

} $subckt="$subckt\n"; open(ATMP,">Satemp")|| die "can not open temp file\n"; print ATMP Ssubckt; close(ATMP); system("cat Sbtemp » Satemp"); system("mv Satemp sym/pcb_macro.mod"); system("cp $obat_pcb_sym sym/pcb_macro.l"); system("cp $obat_pcb_sch sch/pcb_hold.1 "); system("cp $obat_pcb_sch_2 sch/pcb_hold.2"); system("mv Satemp sym/pcb_macro.mod");

@newlistb=@newlist;

$i=l ; foreach Snode (@:newlist) { open(PCBTMP,"<sym pcb_macro.l")|| die "can not read symbol file\n";

@pcb=<PCBTMP>; close(PCBTMP); open(TMP,">$tempfile")|| die "can not open temp file\n": foreach Sline (@pcb) { if( Sline =~ /^ΛL/i) {Sline =~ s/ LSi\b/ Snode\b/g } print TMP Sline;

} print "Insert Snode into sysmbol L$i\n"; close(TMP); system("mv Stempfile sym/pcb_macro.l");

Si++;

@newlist=@newlistb;

$i=l; foreach Snode (@newlist) {

$found=$lookups {Snode} ; open(PCBTMP,"<sch/pcb_hold.l")|| die "can not read symbol file\n";

@pcb=<PCBTMP>; close(PCBTMP); open(TMP,">$tempfile")|| die "can not open temp file\n"; foreach Sline (@pcb) { Sline =~ s/ T$i\b/ Sfound ; print TMP Sline;

} print "Insert Snode into schematic TSi\n"; close(TMP); system("mv Stempfile sch/pcb_hold.l");

Si44-_;

}

@newlist=@newlistb; foreach Snode (@newlist) { $found=$lookups {Snode}; if($found =~ /_CN9_/) {

@fhd=split("_",$found); Ssgsocketb {$fnd[2] } =$found; $sgsockett{$fhd[2]}=$found."_T"; if($found =~ ΛAPD/) {

$fhd[0]=~ s/PD// ; if ($fhd[0] < 32) {

$sgr{$fhd[2]}="PD".Sfhd[0]."_U21";

} if ($fnd[0] >31) {

$sgr{$fhd[2]}="PD".Sfhd[0]."_U22"; }

} elsif (Sfound =~ ΛAMA/) { $fhd[0]=~ s/MA// ;

$sgr{$fhd[2]}="MA".Sfhd[0]."_UU";

} else {

$sgr{$fhd[2]}=$found."_UU"; } print "— $fhd[0] $fhd[2] : Sfound Ssgsocketb {$fhd[2]} Ssgsockett{Sfhd[2]} $sgr{Sfhd[0]}\n"; }

} for ($i=l; Si<145;$i44-) { if (!($sgsocketb {$i} =- /_/)) {

# Ssgsocketb {Si} ="Undef_BSi";

Ssgsocketb {Si} ="PCB_GND"; if (!(Ssgsockett{$i} =- /_/)) {

$sgsockett{$i} ="Undef_TSi"; $sgsockett{$i} ="PCB_GND"; if (!($sgr{$i} =- /_/)) {

$sgr{$i} ="PCB_GND";

} print "after: Si : Ssgsocketb {Si} Ssgsockett{$i} Ssgr{Si}\n"; open(PCBTMP2,"<sch/pcb_hold.2")|| die "can not read symbol file\n";

@pcb=<PCBTMP2>; close(PCBTMP2); open(TMP,">$tempfile")|| die "can not open temp file\n"; foreach Sline (@pcb) { if (Sline =~ ΛAL/) {

Sline =~ s/ B$i\b/ Ssgsocketb {Si}/ ;

Sline =~ s/ TSi Ssgsockett{$i}/ ;

Sline =~ s/ M$i\b/ $sgr{$i}/ ;

} print TMP Sline;

} close(TMP); system("mv Stempfile sch/pcb_hold.2");

OBATPCB

#!/usr/local/bin/perl5

# SHeader: /nfs/proton/home/s31ib/obat/bin RCS/OBATpcb,v 1.2 1997 05/08 01 :39:33 kenli Exp $

#

# Strip the driver stimilus and loading at the terminals

#

# Usage: # OBATpcb unicad_circuits

#

# if ($#ARGV != 0 ) { print "***Welcome to S3 OBAT UNICAD->SPICE NETLIST Program *********\n^»; nnnt '* —————————— —————— —— — — — — — ———To l * ( )T^ Δ TΌ I ^^^^^^M"' print "Usage: \n"; print "OBATpcb Unicad_circuits \n\n"; exit; }

$temρfile='7tmp/obat_tmp$$" ; Spcbtemplate- ' sym/obat_pcb 1.1"; $cirfile=$ARGV[$#ARGV-l];

#~Read in the netlist file from Unicad and analyze print "circuit file=$cirfile\n"; oρen(GETCIR,"<$cirfile") || die "can not open ScirfileVn"; @cir=<GETCTR>; close (GETCIR); open(TMP,">$tempfile")|| die "can not open temp fileW; $linec=l; $title=0; $capflag=0; $deviceflag=0; $signalflag=0; $driveflag=0; foreach Sline (@cir) { if ((Sline =~ ΛAV7) && (Slinec = 1)) { print "Title= Sline\n"; $title=l; print TMP Sline;

} elsif ((Sline =~ ΛA ) && (Sline =~ /coupled line models/i)) { $title=0; print TMP Sline; } elsif ((Sline =~ ΛA\*/) && (Sline =~ /transmission line models/i)) { $title=0; print TMP Sline; } elsif ((Sline =~ ΛAV/i) && (Stitle =1 )) { } elsif (Sline =~ ΛA.option/i) { } elsif (Sline =~ ΛA.end i) { } elsif ((Sline =- ΛA.print/i) || (Sline =~ ΛA.tran/i)) {

Sline =~ sΛA./*./; print TMP Sline; } elsif ((Sline =~ ΛAV/) &«fe (Stitle =1)) { Sline =~ s/VAVΛ*V/; print TMP Sline;

} elsif (Sline =~ ΛA\* Signal/i) { @elements=split(" ",$line); Ssignal=$elements[2] ; print "Ssignal Sdevice Sdriveήn"; $signalflag=l ; print TMP Sline;

} elsif (Sline =~ ΛA\* Device/i) {

@elements=split(" ", Sline);

$device="$elements[2]_$elements[3]_$elements[4]"; $deviceflag=l ; print TMP Sline;

} elsif ((Sline =~ ΛAv/) && (Sline =~ /pulse/i)) { @elements=split(" ",$line); Sforce=$elements[l]; Sdriverflag=l ; Scommentnext=l ;

} elsif ((Sline — ΛA\+/) && (Sdriverflag)) { } elsif ((Sline =~ ΛAr/) && (Sdriverflag)) { @elements=split(" ",$line); $rforce=$elements[ 1 ] ; if (Sforce = Srforce) {

Sdri ver=S elements [2] ; print "Ssignal Sdevice $driver\n"; push(@drivers,$driver); $driverflag=0; }else { print TMP $previous_line; print TMP Sline;

} } elsif ((Sline =~ ΛAc/i) && (Sdeviceflag =1) && (Ssignalflag =1)) {

$capflag=l ; } elsif ((Sline =~ ΛAr/i)&&($capflag)&&($deviceflag)&&($signalflag)&&(! (Sdriverflag))) { @celements=split(" ",$previous_line); $cnode=$celements[l];

@relements=split(" ", Sline); $mode=$relements[ 1 ] ; if (Scnode = Srnode) { print "Ssignal Sdevice $cnode\n"; push(@terms,$cnode);

} else { Snodeflag=0; Scapflagl=0; print TMP Sprevious_line; print TMP Sline;

} } else {

$title=0; print TMP Sline; }

$linec=Slinec4T ; Sρrevious_line=$line;

} close(TMP); open(OUTPUT,">sym/obatjpcb.mod"); open(TMP,"<Stempfile")|| die "can not open temp file\n";

@temp=<TMP>: close(TMP);

OBATPLT

#!/usr/local/bin/perl

# SHeader: /nfs/proton/home/s31ib/obat^in/RCS/OBATplt,v 1.3 1997/08/12 00: 14:23 kenli Exp kenli $

#

# OBATplt.p : read pit file and reaπange

# usage: OBATplt plt_filename # # CJH 12/09/96

# 1/30/97 - add filter to remove comment and empty lines # open (IN, @ARGV[0]);

Slinenum = 1 ; while (<IN>) { Safterl=" "; Safter2=" "; Safter3=" ";

Safter4=" "; @before = split; Scount = @before; if ((Scount > 1) && ($before[0] !~ /^Λ#/)) { Safter2 = Sbefore[0];

Safter3 = $before[l];

$pmatch=0; for ($i=2; Si <= Scount; $i++) { if (($i=4) && ($before[$i] =~ /^Λ[A-Z]/)) {

Safter4=$before[$i]; $pmatch=l ;

} elsif ($before[$i] =- /^Λ#[0-9]/) { Safter4=$before[$i];

$pmatch=l ; } } if($pmatch = 0) { Safter4=join("", "#",$linenum) } ; for ($i=2; Si <= Scount; $i++) { if ($before[$i] =~ /^Λ(PAD|BRE|SPA)/) { $afterl=$before[$i]} ;

} write; $linenum44-;

}

format STDOUT = @<««

Slinenum, Safterl, Safter2, Safter3, $after4 OBATpnc2pak

#!/usr/local/bin perl5 # 5 # Convert subcircuits extracted from Pacific Numerix tool # to a OBAT compatible package parameter format. #

Smachine = 'uname -n'; chop(Smachine); 0 if($machine eq 'skiddle') { require "/home/davidt/proj/avanti/util/floor/src/share/util.pl";

} else { require "/nfs/skiddle/home/davidt/proj/avanti/util/floor/src/share/util.pl"; 5 ]

Sprogram = "OBATpnc2pak"; Sprogram2 = Sprogram . ".pi"; 0 if($#ARGV != 0) { die "Usage: Sprogram <file_name>\n";

} 5 Scomm ='**';

(Stim2,$cpu) = start_it($program); 0 ##mkdir("out", 0777);

$inp_file = SARGV[0]; open(INP2, $inp_fϊle) || die "Cannot open input input file '$inp_file': S!\n" 5

$inp_file2 = rm_dir_path($inp_file);

##$out_file = "out"' . Sinp_file2 . "_OUT"; 0 $out_file = Sinp_file2 . "_LST"; open(OUT2,'>'. Sout_file) || die "Cannot open output file '$out_file': S!\n"; printf(OUT2 "%s Generated by program '%s' on %s\n", Scomm, Sprogram, Stim2); printf(OUT2 "%s from input file '%s'\n", Scomm, $inp_file); 5

&read_input; 0 fmish_it($program.Scpu);

# END OF MAIN >:>

#- #- sub read_input { local(Sline);

while (Sline = <INP2>) { chop(Sline);

$tot++; if( Sline =~ .^,Λ\s*\.SUBCKT\s4-.*_(\S4-)/ ) {

$name = Sl ;

$cl=0.2;

Sc2=0.2; $cml=0.2;

Scm2=0.2;

$11=2;

$lm=2;

$rl=2000; $lw=2;

Sr2=0.05;

} elsif( Sline =~ /^A\s*CPKG\s+\S+\s4AS4-\s+(\S+)/) { $C = $l*le+12;

$cl=$C/2;

Sc2=$C/2;

} elsif( Sline =~ /^Λ\s*LPKG\s+\S+\s4-\S+\s4-(\S+)/) { $L = $l*le4-9;

$11=$L;

} elsif( Sline =~ /^Λ\s*RPKG\s+\S+\s+\S+\s+(\S+)/) {

$R = $1; $r2=$R;

} elsif( $line =~ As*\.ENDS/) { $cpak{Sname}=$C; $lpak{Sname}=$L; $rpak{Sname}=$R; printf(OUT2 •'%s\t%8.5f\t%8.5f\t%8.5f\t⁰/o8.5f\t%8.5f\t%8.5f\t%5.0f\t%8.5f\t%8.5f\n", Sname, Scl ,Sc2,Scml ,$cm2,$ll ,$lm,$rl ,Slw,$r2);

$SUbst44-; } elsif( Sline =~ /^Λ\s*W) { printf(OUT2 "%s\n", Sline); } } printf("\n Total lines %d, output lines %d\n\n", Stot, Ssubst); close(INP2); }

#- OBATio

#!/usr/local/bin/perl5

# . . — # Generate OBAT IO ring schematic according to pin location table and

# package parameter file

#

# Usage:

# OBATio pltfile packagefile #

# if ($#ARGV4-l < 5 ) { print "***Welcome to S3 OBAT IO CELL Generation *********tø.^ι. print "* Tool: makeOBATio *************** _n ^». print "Usage: \n"; print "OBATio processID pltfile packagefile destination_dirtory_name schmatic \n\n"; exit(l); }

$processID=$ARGV[0];

$pltfile=$ARGV[l];

Sρackagefile=$ARGV[2] ;

$dst_dir = $ARGV[3]; $schematic_l= $ARGV[4];

$schematic="$dst_dir/sch/$schematic_l";

$tempfile="/tmp/obat$$" ;

$tmp="/tmp/obattmp$$" ; if($processID =~ "035") { $obatiolib="/nfs/proton/home/s31ib/obat/S3N035/obatiolib";

} elsif (SprocessID =~ "031") {

$obatiolib="/nfs/proton/home/s31ib/obat/S3N031/obatiolib";

} elsif (SprocessID =-~ "025") {

Sobatiolib="/nfs/proton home/s31ib/obat/S3N025/obatiolib";

} elsif (SprocessID =~ "022") {

Sobatiolib="/nfs/proton/home/s31ib/obat/S3N025/obatiolib"; }

$obatblankcell="$obatiolib/OBATBLANK.obat"; Sobatpassthrough="$obatiolib/OBATPAST.obat"; system("cp $obatpassthrough $dst_dir/sym obatpast.mod"); print "pit file=$pltfile\n"; Spreviouspin- ' " ; open(GETLIST,"<$pltfile") || die "can not open $ρltfile\n"; @pltlist=<GETLIST>; close (GETLIST); chomp(@pltlist); orint "*********************OBAT CELL pRFPARATIONS***************************\n''-

$used=0; foreach Slist (@pltlist) {

$used44-; ($pinnumber,$iocell,$pinname,$instance,$packagenum)=split(" ",$list);

$packagenum =~ s/#00//;

Spackagenum =~ s/#0//;

Spackagenum =~ s/#//; Spin_sig {Spackagenum} =Spinname; Spin_num { Spackagenum } =$pinnumber; Sobatcell="Sobatiolib/$iocell.obat"; Sobatmod=lc($iocell.".MOD"); print "OBAT cellcalled= SobatcellVn";

# if ((-s $obatcell) && (!(-s "$dst_dir/sym/$obatmod"))) ( if (-s $obatcell) { #

# If the cell exists in library, copy over to user's diretory # system("cp $obatcell $dst_dir/sym/$obatmod"); #

# Now we are going to insert the model call into the associated IO

# in the top level schematic # open(SCH, "<$schematic. l") || die "Can not open Sschematic. lVn"; open(TMP, ">$tmp") || die "Can not open temp fileVn"; foreach Sline (<SCH>) { if ((Sline =~ ΛAA/ ) && ($line =~ /MODEL=/)) { Stoken="MODEL_PrN".Spinnumber;

$line=~ s/$tokenVb/$iocell/ ;

} print TMP $line;

} close(SCH); close(TMP); system("mv Stmp Sschematic.l");

} elsif (!(-s $obatcell)) {

#

# If the cell does NOT exist in library, show the warning!

# and use obatpast.obat in stead. # print "The cell: Sobatcell does not exist! n";

# modify the schematic to refer to obatpast cell# open(SCH, "<$schematic. l") || die "Can not open $schematic\n"; open(TMP, ">$tmp") || die "Can not open temp fileVn" ; foreach Sline (<SCH>) { if ((Sline — ΛAA/ ) && (Sline =~ /MODEL=/)) {

$token="MODEL_PιN".$pinnumber;

$line=~ s/$tokenVb/OBATPAST/ ;

} print TMP Sline; } close(SCH); close(TMP); system("mv Stmp Sschematic. l ");

} } for ($i=$used+l ;$i <201 ; $i++) { open(SCH, "<$schematic. l ") || die "Can not open $schematicVn"; open(TMP, ">$tmp") || die "Can not open temp fileVn" ; foreach Sline (<SCH>) { if ((Sline =~ ΛAA ) && (Sline =~ /MODEL=/)) {

$token="MODEL_PIN".$i; $line=~ s/$tokenVb/OBATPAST/ ; } print TMP $line;

} close(SCH); close(TMP); system("mv Stmp Sschematic.l"); if(($i % 10) = 0) {pnnt "."};

} print "Vn"; print "*********************OBAT PACKAGE PARAMETER PASSING* ******************Vn" ^• open(PAKPARAM."<$packagefιle"); @paklist=<PAKPARAM>; close(PAKPARAM); Sused=0; foreach Splist (@paklist) { if (!(($plist =~ ΛA#/)||(Splist =~ ΛAV*/))) {

($pakpin,$cl,Sc2,Scml,Scm2,Sll,$lm,$rl,$lw,Sr2)=split(" ",Sρlist); $pin_cl {$pakpin}=Scl."P"; $pin_c2{$ρakpin}=$c2."P"; $pin_cml {$pakpin}=$cml."P";

Spin_cm2{$pakpin}=$cm2."P"; Spin l {$pakpin}=Sll."N"; Spin m {$pakpin} =$lm."N" ; $pin_rl {$pakpin}=$rl; $pin w{$pakpin}=$lw."N";

$pin_r2 {$pakpin}=$r2; push(@obatplist, Spakpin); Sused44-;

} } foreach Spinlist (@obatplist){ $ll=$pin_ll {Spinlist}; $lw=$pin_lw {Spinlist} ; $cl=$pin_cl {Spinlist}; Sc2=$pin_c2{$pinlist};

$rl=$pin_rl {Spinlist}; Sr2=$pin_r2 {$pinlist} ; $cml=$pin_cml {Spinlist} ; Scm2=$pin_cm2 {$pinlist} ; $obatpin=Spin_num { Spinlist} ; print "PACKAGE=Sρinlist OBATPIN=$obatpin $pin_sig{Spinlist}Vn"; open(SCH,"<$schematic.l") || die "Can not open $schematicVn"; open(TMP, ">$tmp") || die "Can not open $tmpVn"; foreach Sline (<SCH>) { $token="=PrN".$obatpin."_"; if (($obatpin !="")&&($line =~ /Stoken/)) { # print "before:New Parameter: Sline";

Stokenl 1 ="PIN$obatpin" ."_L1 " ; $tokenlw="PIN$obatpin" . "_LW" ; Stokenc 1 ="PrN$obatpin" . "_C 1 " ;

Stokenc2="PIN$obatpin" . "_C2" ; Stokenr 1 ="PIN$obatpin" ."_R1 " ; $tokenr2="PIN$obatpin" . "_R2" ; Stokencml="PrN$obatpin"."_CMl"; $tokencm2="PIN$obatpin"."_CM2";

Stokenmodel="PrN$obatpin" ."_MODEL" ; Sline =~ s/$tokenll/$ll/; Sline =~ s/$tokenlw/$lw/; Sline =~ s/Stokencl/Scl/; Sline =~ s/$tokenc2/Sc2/; $line =~ s/$tokenrl/Srl/; $line =~ s/$tokenr2/Sr2/; Sline =~ s/$tokencm 1 /Scm 1 /;

Sline =~ s/$tokencm2/$cm2/; $line =~ s/$tokenmodel/LF/;

} print TMP $line; } close(TMP); system("mv Stmp Sschematic.l");

} for (Si=l;Si <201; Si++) { open(SCH. "<$schematic.l") || die "Can not open SschematicVn"; open(TMP, ">Stmp") || die "Can not open temp fileVn" ; foreach $line (<SCH>) {

$token="PIN$i"."_"; if (($line =~ ΛAA/ ) && (Sline =~ /$token/)){ $tokenll="PLN$i"."_Ll";

$tokenlw="PIN$i" . "_LW" ;

Stokencl="PIN$i"."_Cl";

$tokenc2="PrN$i"."_C2";

$tokenrl="PIN$i"."_Rl"; Stokenr2="PIN$i"."_R2";

$tokencml="PIN$i"."_CMl";

$tokencm2="PrN$i"."_CM2";

Stokenmodel="PrN$i"."_MODEL";

$line =~ s/$tokenll/lN/; Sline =~ s/$tokenlw/ 1 N/;

Sline =- - s/$tokencl/0.5P/;

Sline =- - s/$tokenc2/0.5P/;

$line — - s/$tokenrl/1000/;

Sline =- - s/$tokenr2/0.05/;

Sline =- - s/$tokencml/0.5P/;

Sline =- - s/$tokencm2/0.5P/;

Sline =- - s/$tokenmodel/LF/;

) print TMP Sline; l close(SCH); close(TMP); system("mv Stmp Sschematic.l"); if(($i % 10) = = 0) {print "$iVn"}

OBATlib

#!/usr/local/bin/perl5

# # Convert EXD flat netlist to OBAT net list

#

# Usage:

# makeOBATlib processID compatible_type exd_file # #

# This script is to generate OBAT library netlists in the current

# directory 12/11/96 K.Li

# To run this script you need to obtain the combined EXD netlist which

# is used for Cell library charicterization.

$compatible=" spectre"; if($#ARGV != 2 ) { print "***Welcome to S3 OBAT Library Preparation Program *********\_n"; orint "************* Tool- OBATlib Rev 2 1 **************^". print "Usage: Vn"; print "OBATlib processID compatiblejype combined_exd_file VnVn"; print "For example Vn"; print "OBATlib 025 spectre all_cell.exd VnVn"; exit(l); }

$processID=SARGV[$#ARGV-2]; $compatible=$ARGV[$#ARGV- 1 ] ; $fιlename=$ ARGV[$#ARGV] ; print "You had specified $processID as the technology usediVn"; $cnt=0; while (!(SprocessID =~ /025/)) { if (Sent > 0) { print "ProcessID is not valid, please enter umc025 or tsmc025)Vn"; $processID=&getinput; }

Scnt44-;

} print "compatible_type=ScompatibleVn"; print "combined exd file=$filenameVn"; open(INPUT, "<$filename") || die "Can not open SfilenameVn";

@whole=<INPUT>; close(INPUT);

# For 0.25/0.18 IO

$subheader_io = «; + D2XE D2XO D1X DC DO DE DE2

+ RESETN OEN VSEL AGP DRTVESELECT PUN PD LEAKEN BYPASS SET2X

DIBPDN TIBPDN

4- PAD ICK CCK X DCK_2X VREF BIAS VDD VSS VDDD VSSD VSSUB VDIO

4- ICKT CCK XT DCK_2XT VREFT BIAST VDDT VSST VDDDT VSSDT VSSUBT VDIOT

$parameter_io = «; parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05 + _RVDIO=0.05 _RVREF=0.05 _RBIAS=0.05 _RICK=0.05 _RCCK=0.05 _RDCK=0.05

$ringroute_io = «;

RICK ICK ICKT resistor r=_RICK RCCK CCK_1X CCK_1XT resistor r=_RCCK RDCK DCK 2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS

RVDDD VDDD VDDDT resistor r=_RVDDD RVSSD VSSD VSSDT resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVS SUB RVDD VDD VDDT resistor r=_RVDD RVDIO VDIO VDIOT resistor r=_RVDIO

# For 0.25/0.18 CLOCK

$subheader_clk = «;

4- CCLK DCLK STBO CORECK FDBK CORE6 CORE7 4- RESETN OEN VSEL AGP DRIVESELECT PUN PD LEAKEN BYPASS CVAL DIBPDN TIBPDN

4- PAD ICK015 CCK015 DCK015 VREF BIAS VDD VSS VDDD VSSD VSSUB VDIO 4- ICK16U CCK16U DCK16U VREFT BIAST VDDT VSST VDDDT VSSDT VSSUBT VDIOT

Sρarameter_clk =Sparameter_io;

$ringroute_clk = «; RICK ICK015 ICK16U resistor r=_RICK

RCCK CCK015 CCK16U resistor r=_RCCK

RDCK DCK015 DCK16U resistor r=_RDCK

RVREF VREF VREFT resistor r=_RVREF

RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS

RVDDD VDDD VDDDT resistor r=_RVDDD

RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB

RVDD VDD VDDT resistor r=_RVDD RVDIO VDIO VDIOT resistor r=_RVDIO

# For 0.25/0.18 PSTB

$subheader_pstb = «;

4- CCLK DCLK STBO CORECK FDBK SO Sl 4- S2 S3 VSEL AGP DRIVESELECT PUN PD LEAKEN BYPASS CVAL DIBPDN TIBPDN 4- PAD ICK015 CCK015 DCK015 VREF BIAS VDD VSS VDDD VSSD VSSUB VDIO + ICK16U CCK16U DCK16U VREFT BIAST VDDT VSST VDDDT VSSDT VSSUBT VDIOT $parameter_pstb =$parameter_io; $ringroute_pstb =Sringroute_clk;

# For 0.25/0.18 BIAS

$subheader_bias =«; 4- BIAS PDN CORE3 CORE4 CORE5 CORE6 CORE7

4- CORE8 CORE9 CORE10 CORE11 CORE12 CORE13 CORE14 CORE15 CORE16

CORE17 CORE18 CORE19

4- PAD ICK CCK X DCK_2X VREF BIAS VDD VSS VDDD VSSD VSSUB VDIO

4- ICKT CCK XT DCK_2XT VREFT BIAST VDDT VSST VDDDT VSSDT VSSUBT VDIOT

$parameter_bias =$parameter_io; $ringroute_bias =«; RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCK_1XT resistor r=_RCCK RDCK DCK 2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r=_RVDIO RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=_RVDD

RVDDD VDDD VDDDT resistor r=_RVDDD

# For 0.25/0.18 VREF

Ssubheader vref =«; + CORE1 CORE2 CORE3 CORE4 CORE5 CORE6 CORE7

4- CORE8 CORE9 COREIO COREl l CORE12 CORE13 CORE14 CORE15 CORE16

CORE17 CORE18 CORE19

4- PAD ICK CCK X DCK_2X VREF BIAS VDD VSS VDDD VSSD VSSUB VDIO

4- ICKT CCKJXT DCK_2XT VREFT BIAST VDDT VSST VDDDT VSSDT VSSUBT VDIOT

$parameter_vref =Sparameter_io;

Sringroute vref =«;

RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCKJXT resistor r=_RCCK

RDCK DCK_2X DCK_2XT resistor r=_RDCK

RVREFT PAD VREFT resistor r=_RVREF* 0.5

RVREF PAD VREF resistor r=_RVREF* 0.5

RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r=_RVDIO

RVSS VSS VSST resistor r=_RVSS

RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB

RVDD VDD VDDT resistor r=_RVDD RVDDD VDDD VDDDT resistor r=_RVDDD

# if (Scompatible =~ /spectre/i) { foreach Slinec (@whole) { if ($linec =~ /SUBCKT/i) {

@ajine=split(" ",Slinec); open(OUT, ">SaJine[l]V.obat"); push (@celllist,$ajine[l]); print OUT "** OBAT CELL LIBRARY v.2 Vn"; print OUT "** $aJine[l]V.obat Vn"; print OUT "Sajine[0] SaJine[l]Vn"; if ($a_line[l] =~ "PADSIO") { print OUT "Ssubheader o"; print OUT "Sparameter o"; print OUT "Sringroute o";

} elsif ($a ine[l] =~ "PADBIAS") { print OUT "$subheader_bias"; print OUT "$parameter_bias"; print OUT "$ringroute_bias";

} elsif ($a ine[l] =~ "PAD VREF") { print OUT "$subheader_vref; print OUT "$parameter_vref; print OUT "$ringroute_vref; elsif (Sa ine[ 1 ] =~ "PADISTB") { print OUT "$subheader_clk"; print OUT "$parameter_clk"; print OUT "$ringroute_clk";

} elsif ($ajine[l] =~ "PADPSTB") { print OUT "$subheader_pstb"; print OUT "$parameter_pstb"; print OUT "$ringroute_pstb";

} else { print OUT "Ssubheader o"; print OUT "Sparameter o"; print OUT "Sringroute o";

} $subflag=l;

} else I if (Slinec=~ /ENDS/i) { print OUT "Slinec"; close (OUT)

} else {print OUT "Slinec"; $subflag=0

} }

} } else { foreach Slinec (@whole) { if (Slinec =~ /SUBCKT/i) {

@ajine=split(" ",$linec); open(OUT. ">$aJine[l]V.obat"); print OUT "** OBAT CELL LIBRARY Vn"; print OUT "** SaJine[l]V.obat Vn"; print OUT "$ajine[0] $aJine[l]Vn"; if($ajine[l] =~ "PADSIO16D8E") { print OUT "Ssubheaderjo";

} else { print OUT "Ssubheader2";

} print OUT "+ _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05Vn"; print OUT "+ _RICK=0.05 _RCCK=0.05 _RDCK=0.05 _RVREF=0.05 _RBIAS=0.05 _RVDIO=0.05Vn"; print OUT "RICK ICK ICKT RICK Vn"; print OUT "RCCK CCKJX CCKJXT RCCK Vn"; print OUT "RDCK DCK 2X DCK 2XT RDCK Vn"; print OUT "RVREF VREF VREFT _RVREF Vn"; print OUT "RBIAS BIAS BIAST _RBIAS Vn"; print OUT "RVSS VSS VSST _RVSS Vn"; print OUT "RVDDD VDDD VDDDT JtVDDDVn"; print OUT "RVSSD VSSD VSSDT _RVSSDVn"; print OUT "RVSSUB VSSUB VSSUBT _RVSSUBVn" print OUT "RVDD VDD VDDT _RVDDVn"; print OUT "RVDIO VDIO VDIOT _RVDIOVnVn";

} if (Slinec=~ /ENDS/i) { pπnt OUT "Slinec"; close (OUT)

} else {print OUT "Slinec";

} } } } close(OUT);

@salls=sort(@celllisf) ; Sprevious- "'; undef(@celllist); foreach Sany (@salls) { if ((Sany ne Sprevious) && (Sany ne "")) { print "New Cell: Sany is prepared.Vn"; push(@celllist,$any);

} $previous=$any; }

# Create files for Power I/Os

# if ($processID =-~ "025") { open(OUT, ">OBATPAST.obat");

} print OUT «EOFl;

** OBAT CELL LIBRARY

** OBATPAST.obat .SUBCKT OBATPAST Ssubheaderjo

51 ICK ICKT switch position=l

52 CCKJX CCKJXT switch position=l

53 DCK_2X DCK_2XT switch position=l S4 VREF VREFT switch position=l

55 BIAS BIAST switch position=l

56 VDD VDDT switch position=l

57 VSS VSST switch position=l

58 VDDD VDDDT switch position=l S9 VSSD VSSDT switch position=l

510 VSSUB VSSUBT switch position^

511 VDIO VDIOT switch position=l .ENDS

EOF1

#

# if ($processID =~ "025") { open(OUT, ">OBATBLANK.obat");

} print OUT «EOF2A; // OBAT CELL LIBRARY

// OBATBLANK.obat

.SUBCKT OBATBLANK Ssubheaderjo parameters _RVSS=10MEG _RVDD=10MEG _RVSSD=10MEG _R\T)DD=10MEG

_RVSSUB=10MEG VV

_RVDIO=10MEG _RVREF=0.5 _RBIAS=0.5 _RICK=10MEG _RDCK=0.5

10 RVDDD PAD VDDD resistor r=_RVDDD/2

RVDDDT PAD VDDDT resistor r=_RVDDD/2

RICK ICK ICKT resistor r=_RICK

RCCK CCKJX CCKJXT resistor r=_RCCK

RDCK DCK_2X DCK XT resistor r=_RDCK 15 RVREF VREF VREFT resistor r=_RVREF

RBIAS BIAS BIAST resistor r=_RBIAS

RVSS VSS VSST resistor r=_RVSS

RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB 20 RVDD VDD VDDT resistor r=_RVDD

RVDIO VDIO VDIOT resistor r= JIVDIO

Ssubheader3

25 .ENDS

30 if (SprocessID =~ "025") { open(OUT, ">PADCBICK.obat");

} print OUT «EOF2B;

// OBAT CELL LIBRARY

35 // PADCBICK.obat

.SUBCKT PADCBICK Ssubheaderjo parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05 40 _RICK=100MEG _LW=4NH _L1=4NH VV

_RVREF=0.05 _RBIAS=0.05 _RVDIO=0.05 _RCCK=0.05 _RDCK=0.05

RICK PAD ICK resistor r=_RICK 2

RICKT PAD ICKT resistor r=_RICK/2 45 RCCK CCK J X CCK_1 XT resistor r=_RCCK

RDCK DCK_2X DCK_2XT resistor r=_RDCK

RVREF VREF VREFT resistor r=_RVREF

RBIAS BIAS BIAST resistor r=_RBIAS

RVSS VSS VSST resistor r=_RVSS so RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB

RVDD VDD VDDT resistor r=_RVDD

RVDIO VDIO VDIOT resistor r= JIVDIO

RVDDD VDDD VDDDT resistor r= RVDDD

JJ

Ssubheader3 .ENDS

# if ($processID = "025") { open(OUT, ">PADCBICKG.obat");

} print OUT «EOF2L;

// OBAT CELL LIBRARY a PADCBICKG.obat

.SUBCKT PADCBICKG Ssubheader io parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05 _RICK=0.05 _LW=4NH _L 1 =4NH VV

_RVREF=0.05 _RBIAS=0.05 _RVDIO=0.05 _RCCK=0.05 _RDCK=0.05

RICK GND ICK resistor r=_RICK/2

RICKT GND ICKT resistor r=_RICK 2 RCCK CCKJX CCKJXT resistor r=_RCCK

RDCK DCK_2X DCK_2XT resistor r=_RDCK

RVREF VREF VREFT resistor r=_RVREF

RBIAS BIAS BIAST resistor r=_RBIAS

RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB

RVDD VDD VDDT resistor r=_RVDD

RVDIO VDIO VDIOT resistor r=_RVDIO

RVDDD VDDD VDDDT resistor r= RVDDD

Ssubheader3

.ENDS

EOF2L

if($processID =- "025") { open(OUT, ">PADCBCCK.obat"); } print OUT «EOF2C;

// OBAT CELL LIBRARY

// PADCBCCK.obat

.SUBCKT PADCBCCK Ssubheaderjo parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05

_RCCK=100MEG _LW=4NH _L1=4NH VV

_RVREF=0.05 _RBIAS=0.05 _RVDIO=0.05 _RICK=0.05 _RDCK=0.05

RCCK PAD CCK resistor r=_RCCK 2 RCCKT PAD CCKT resistor r=_RCCK/2 RICK ICK ICKT resistor r=_RICK RDCK DCK 2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r= _RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=_RVDD RVDIO VDIO VDIOT resistor r=_RVDIO RVDDD VDDD VDDDT resistor r=_RVDDD

J

Ssubheader3

.ENDS

# if ($processID =- "025") { open(OUT, ">PADCBCCKG.obat"); 5 } print OUT «EOF2M;

// OBAT CELL LIBRARY

// PADCBCCKG.obat

.SUBCKT PADCBCCKG 0 $subheader_io parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05 _RCCK=0.05 _LW=4NH _L1=4NH VV _RVREF=0.05 _RBIAS=0.05 _RVDIO=0.05 _RICK=0.05 _RDCK=0.05 5

RCCK GND CCK resistor r=_RCCK/2

RCCKT GND CCKT resistor r=_RCCK/2

RICK ICK ICKT resistor r=_RICK

RDCK DCK_2X DCK_2XT resistor r=_RDCK 0 RVREF VREF VREFT resistor r=_RVREF

RBIAS BIAS BIAST resistor r=_RBIAS

RVSS VSS VSST resistor r=_RVSS

RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB 5 RVDD VDD VDDT resistor r=_RVDD

RVDIO VDIO VDIOT resistor r=_RVDIO

RVDDD VDDD VDDDT resistor r= RVDDD

$ subheader 3 0

.ENDS EOF2M close(OUT);

# 5 # if($processID =~ "025") { open(OUT, ">PADCBDCK.obat");

} print OUT «EOF2D; 0 II OBAT CELL LIBRARY

// PADCBDCK.obat

.SUBCKT PADCBDCK Ssubheaderjo 5 parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05 JRDCK=100MEG J_W=4NH _L1=4NH VV RVREF=0.05 RBIAS=0.05 RVDIO=0.05 RCCK=0.05 RICK=0.05 RDCK PAD DCK resistor r=_RDCK/2 RDCKT PAD DCKT resistor r=_RDCK/2 RCCK CCKJX CCKJXT resistor r=_RCCK RICK ICK ICKT resistor r=_RICK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=_RVDD RVDIO VDIO VDIOT resistor r= JIVDIO RVDDD VDDD VDDDT resistor r= RVDDD

Ssubheader3

.ENDS

EOF2D close(OUT);

# # if ($processID =~ "025") { open(OUT, ">PADCBDCKG.obat");

} print OUT «EOF2N; a OBAT CELL LIBRARY

// PADCBDCKG.obat

.SUBCKT PADCBDCKG Ssubheaderjo parameters _RVSS=0.05 _RVDD=0.05 _RVSSD=0.05 _RVDDD=0.05 _RVSSUB=0.05 _RDCK=0.05 _LW=4NH _L1=4NH VV _RVREF=0.05 _RBIAS=0.05 _RVDIO=0.05 _RCCK=0.05 JUCK=0.05

RDCK GND DCK resistor r=_RDCK/2 RDCKT GND DCKT resistor r=_RDCK/2

RCCK CCKJX CCKJXT resistor r=_RCCK

RICK ICK ICKT resistor r=_RICK

RVREF VREF VREFT resistor r=_RVREF

RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS

RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVSSUB

RVDD VDD VDDT resistor r=_RVDD

RVDIO VDIO VDIOT resistor r=JRVDIO RVDDD VDDD VDDDT resistor r= JRVDDD

Ssubheader3

.ENDS EOF2N close(OUT);

#

# if ($processID =~ "035") { open(OUT, ">OBATBLANK.obat");

} print OUT «EOF2;

// OBAT CELL LIBRARY // OBATBLANK.obat

.SUBCKT OBATBLANK Ssubheaderjo parameters _RVSS=10MEG _RVDD=10MEG _RVSSD=10MEG _RVDDD=10MEG _RVSSUB=10MEG

RVDDD PAD VDDD resistor r=_RVDDD/2 RVDDDT PAD VDDDT resistor r=_RVDDD/2 RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r=_RVSSD

RVSSUB VSSUB VSSUBT resistor r=_RVS SUB RVDD VDD VDDT resistor r=_RVDD

$subheader3 .ENDS

# if($processID =~ "025") { open(OUT, ">PADVDDD.obat");

} print OUT «EOF3;

// OBAT CELL LIBRARY a PADVDDD.obat

.SUBCKT PADVDDD Ssubheaderjo Sparameter Jo RVDDD PAD VDDD resistor r=_RVDDD/2 RVDDDT PAD VDDDT resistor r=_RVDDD/2 RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK_2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r= JtVREF RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r= RVSS RVSSD VSSD VSSDT resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=JRVDD RVDIO VDIO VDIOT resistor r= JIVDIO

$subheader3

.ENDS

# if ($processID =~ "025") { open(OUT, ">PADGNDD.obat");

} print OUT «EOF5;

// OBAT CELL LIBRARY

// PADGNDD.obat .SUBCKT PADGNDD Ssubheaderjo Sparameterjo RVSSD PAD VSSD resistor r=_RVSSD/2 RVSSDT PAD VSSDT resistor r=_RVSSD/2 RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK_2X DCK XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r= JIVDIO RVSS VSS VSST resistor r=_RVSS RVDDD VDDD VDDDT resistor r=_RVDDD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r= RVDD

$subheader3

.ENDS

# if($processID =~ "025") { open(OUT, ">PADGNDS.obat");

} print OUT «EOF7; II OBAT CELL LIBRARY

// PADGNDS.obat

.SUBCKT PADGNDS Ssubheaderjo Sparameter Jo

RVSSUB PAD VSSUB resistor r=_RVSSUB/2 RVSSUBT PAD VSSUBT resistor r=_RVSSUB/2 RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK_2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r= JIVDIO RVSS VSS VSST resistor r=_RVSS RVDD VDD VDDT resistor r=_RVDD

RVSSD VSSDT VSSD resistor r=_RVSSD RVDDD VDDD VDDDT resistor r= RVDDD

Ssubheader3

.ENDS

# if($processID =~ "025") { open(OUT, ">PADVDDIOL.obat");

} print OUT «EOF8; a OBAT CELL LIBRARY

// PADVDDIOL.obat

.SUBCKT PADVDDIO4 S subheader io Sparameter_io

RVDD PAD VDD resistor r=_RVDD/2 RVDDT PAD VDDT resistor r= JtVDD/2 RICK ICK ICKT resistor r=_RICK

RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK 2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r=_RVDIO RVSS VSST VSS resistor r=_RVSS RVDDD VDDD VDDDT resistor r=_RVDDD RVSSD VSSDT VSSD resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r= RVSSUB

Ssubheader3

.ENDS

EOF8 close(OUT);

#

# if($processID =~ "025") { open(OUT, ">PADGNDIOL.obat"); } print OUT «EOF9;

// OBAT CELL LIBRARY

// PADGNDIOL.obat

.SUBCKT PADGNDIOL Ssubheaderjo Sparameterjo

RVSS PAD VSS resistor r=_RVSS/2 RVSST PAD VSST resistor r=_RVSS/2 RICK ICK ICKT resistor r=_RICK

RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK 2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r= JIVDIO RVDDD VDDD VDDDT resistor r=_RVDDD RVSSD VSSDT VSSD resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVS SUB RVDD VDD VDDT resistor r= RVDD

Ssubheader3

.ENDS

EOF9 close(OUT);

#

# if ($processID =~ "035") { open(OUT. ">PADGNDIOL.obat"); } print OUT «EOF9A;

// OBAT CELL LIBRARY

// PADGNDIOL.obat .SUBCKT PADGNDIOL

Ssubheader_io

Ssubheaderparam035 RVSS PAD VSS resistor r=_RVSS/2 RVSST PAD VSST resistor r=_RVSS/2 RVDDD VDDD VDDDT resistor r= J .VDDD RVSSD VSSDT VSSD resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=_RVDD

Ssubheader3

.ENDS EOF9A

if ($processID =~ "025") { open(OUT, ">PADVDDW.obat"); print OUT «EOF10;

// OBAT CELL LIBRARY

// PADVDDW.obat-025 .SUBCKT PADVDDW Ssubheaderjo Sparameterjo

RVSS VSST VSS resistor r=_RVSS RVDDD VDDD VDDDT resistor r=_RVDDD RVSSD VSSDT VSSD resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDDT VDD VDDT resistor r=_RVDD RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK_2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVDIO VDIO VDIOT resistor r= JIVDIO

Ssubheader3 .ENDS

# if($processID =~ "035") { open(OUT, ">PADTVDDW.obat");

} print OUT «EOF10A;

// OBAT CELL LIBRARY

// PADTVDDW.obat-035

.SUBCKT PADTVDDW Ssubheaderjo $subheaderparam035

RVSS VSST VSS resistor r=_RVSS RVDDD VDDD VDDDT resistor ι= RVDDD RVSSD VSSDT VSSD resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDDT VDD VDDT resistor r=_RVDD Ssubheader3 .ENDS EOF10A close(OUT); # # if($processID =~ "025") { open(OUT. ">PADVDIO.obat"); print OUT «EOFl l; II OBAT CELL LIBRARY

// PADVDIO.obat- 025

.SUBCKT PADVDIO

Ssubheaderjo

Sparameterjo

RVDIO PAD VDIO resistor r=_RVDIO/2 RVDIOT PAD VDIOT resistor r= JlVDIO/2 RICK ICK ICKT resistor r=_RICK RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK_2X DCK_2XT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r=_RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=_RVDD RVDDD VDDD VDDDT resistor r=_RVDDD

Ssubheader3 .ENDS

if ($processID =~ "025") { open(OUT, ">PADVDDDIO.obat");

} print OUT «EOF13;

// OBAT CELL LIBRARY a PADVDDDIO.obat- 025

.SUBCKT PADVDDDIO

Ssubheaderjo

Sparameterjo RVDIO PAD VDIO resistor r=_RVDIO/2 RVDIOT PAD VDIOT resistor r=_RVDIO/2 RICK ICK ICKT resistor r= JUCK RCCK CCKJX CCKJXT resistor r=_RCCK RDCK DCK_2X DCKJXT resistor r=_RDCK RVREF VREF VREFT resistor r=_RVREF RBIAS BIAS BIAST resistor r=_RBIAS RVSS VSS VSST resistor r=_RVSS RVSSD VSSD VSSDT resistor r= RVSSD RVSSUB VSSUB VSSUBT resistor r=_RVSSUB RVDD VDD VDDT resistor r=_RVDD RVDDDT PAD VDDDT resistor r=_RVDDD/2 RVDDD PAD VDDD resistor r=_RVDDD/2

Ssubheader3 .ENDS EOF 13 close(OUT);

#-

# sub getinput { local Sprocess; while(l) { chop($process = <STDIN>); return Sprocess; } } #

OBATsch

#!/usr/local bin perl5

#

# Inserting signal names from pin Location table into schematic #

# Usage:

# OBATsch processID pltfile top_level_schematic

#

# if($#ARGV+l < 4 ) { print "***Welcome to S3 OBAT Signal Name Insertion Program ********=⁽ "^• print " * Tool : OBATsch* ************* *\n" _; print "Usage: Vn"; print "OBATsch processID pltfile sch_name destination ir VnVn"; exit(l); }

SprocessID=$ARGV[0]; $pltfile=SARGV[l];

$schematicname=S ARGV[2] ;

$dst_dir = $ARGV[3];

$linec=&linecount(Spltfile); print "Total OBAT io cells =$linecVn"; if($linec > 200) {

$schematictemplate="/nfs/proton/home/s31ib/viewlogic/obat/sch/ioring600.1";

} else {

$schematictemplate="/nfs/proton home/s31ib/viewlogic/obat/sch/ioring200.1 " ;

} $symboltemplate="/nfs/proton/home/s31ib/viewlogic/obat/sym io.1 " ; $symboltemplate2="/nfs/proton/home/s3 lib/viewlogic/obat/sym/lf.1 " ; #

$corebus{'035'}=6;

Scorebus {'umc031'}=7; Scorebus {'tsmc031'} =7;

$corebus{'025'}=19;

$corebus{^*tsmc025'}=19;

$corebus{'umc025'}=19;

Scorebus {'umc022'}=l 9; $padring{'035'}=7;

Spadring { 'umc031 ' } =5 ;

Spadring {'tsmc031'}=5;

Spadring{'umc025'}=l l;

Spadring {'umc022'}=l l; Spadring{'tsmc025'}=l l;

#

(Stitle = Sschematicname) =~ tr/a-z/A-Z/;

Stitle = Stitle . "Board Level Schematic for OBAT analysis"; $schematic="$dstJir/sch/Sschematicname.l";

Sschematic3="$dst ir/sch/$schematicname.3 " ; system("cp Sschematictemplate Sschematic");

$symbol="$dst_dir/sym/io.1 "; system("cp Ssymboltemplate Ssymbol"); Ssymbol2="$dst ir/sym/lf2.1 "; system("cp $symboltemplate2 Ssymbol2");

$tempfile="/tmp/obat$$" ;

Sobatblankcell="OBATBLANK.obat"; Snow=&gettimestamp ; $username=$<;

$lineθl="=- — = =S3 OBAT

SCHEMATIC= Sline02="THIS SCHEMATIC IS CREATED FROM S3 OBAT LIBRARY ";

Sline03="TIME: Snow";

Sline04="PROJECT: Sschematic ";

Sline05="USER: Susername ";

Sline06=" "; Sline07="Pleaese do NOT modify this page before consulting with OBAT team";

$line08="You can create the pages 2, 3, 4 as you wish ";

Sline09=" ";

$linel0=" S3 COT DEPARTMENT, version 1.0 1997 "; print "pit file=$pltfιleVn"; print "input schematic file=SschematicVn"; open(GETLIST,"<$pltfile") || die "can not open SpltfileVn";

@pltlist=<GETLIST>; close (GETLIST); chomp(@pltlist); @namelist=@pltlist;

@wholefile=""; open(OUT,">$tempfile") || die "can not open temp fileVn"; p_rint „***************#*****_{INSERT piN} NAME INTO SCHEMATIC 1 foreach Slist (@namelist) { open(OUT,">$tempfile") || die "can not open temp fileVn"; open(INPUT, "<$schematic") || die "Can not open SschematicVn"; ($pinnumber,$iocell,$pinname,$instance,$packagenum)=split(" ",$list); Spinsymbol="PIN".$pinnumber; Spinpad=$pinsymbol."_PAD"; if ('.(defined (Scount {Spinname}))) {

$newpinpad=$pinname. "_P AD" ; Scount {$pinname}=l ; } else { Scount {Spinname} 4-4-;

Sρatchpad=$count {Spinname} ; Snewpinpad=Spinname."_PAD".$patchpad;

}

Spinmodel="MODEL=MODEL_PIN".$pinnumber; foreach Sline (<INPUT>) { if (Sline =~ ΛAL/ ) {

$line=~s/ SpinsymbolVb/ Spinname/; $line=~s/ SpinpadVb/ Snewpinpad/;

} if (Sline =~ ΛAA ) {$line=~s/ SpinmodelVb/ MODEL=Siocell/;} print OUT Sline;

} close (INPUT); close(OUT); system("mv Stempfile Sschematic"); print "Spinname located in OBAT pin= Spinnumber = Package pin= Spackagenum =Model: SiocellVn";

} @namelist=@pltlist; #

# — MODIFY THE COREBUS & PADRING TO BE PROCESS (I/O LIBRARY)

COMPATIBLE —

#

open(INPUT, "<Sschematic") || die "Can not open Sschematicvn"; open(OUT,">$tempfile") || die "can not open temp fileVn"; @wholefile=<INPUT>; foreach Sline (@wholefile) {

Sline =~ s/l :25/l :$corebus{$processID}/g;

Sline =~ s/l : 12/l :$padring{$processID}/g; print OUT Sline;

} close (OUT); close (INPUT); system("mv Stempfile Sschematic"); print "Complete for CorebusVn"; nrint "*****************************MODIFY PADRING***********************************Vn"' open(INPUT, "<$symbol") || die "can not open symbol fileVn"; open(OUT,">$tempfile") |j die "can not open temp fileVn"; @wholefile=<rNPUT>; foreach Sline (@wholefile) {

Sline =~ s/l :25/l :$corebus{$processID}/g;

Sline =~ s/l : 12/l :$padring{$processID}/g; print OUT Sline; } close (OUT); close (INPUT); system("mv Stempfile Ssymbol"); print "Complete for PadringVn"; #

# orint "*********************INSERT NO CONNECT open(INPUT, "<Sschematic") || die "Can not open SschematicVn"; open(OUT,">$tempfile")|| die "can not open temp fileVn"; @wholefile=<INPUT>; foreach Sline (@wholefile) { if ((Sline =~ ΛAL/) && (Sline =~ / PIN/)) { @atrlist=split(" ", Sline); $pirmunτ=$atrlist[-l];

Spinnum =~ s/PIN//; if ((Spinnum >= Slinec)) { $atrlist[-l]="NC"; print OUT @atrlist; print OUT "Vn"; } else { print OUT Sline;

} } else { print OUT Sline;

}

} close (OUT); close (INPUT); system("mv Stempfile Sschematic"); print "Complete for No connect pinsVn"; _print ..***,^| _EI ^| _I********_I ^|,***_] ^| ₁ ^|,_I ^|.*_INsERT PASS THROUGH ON UNUSED CELLS* ******************** *\n"' open(INPUT, "<$schematic") || die "Can not open SschematicVn"; open(OUT,">$tempfile")|| die "can not open temp fileVn"; @wholefile=<INPUT>; foreach Sline (@wholefile) { if ((Sline =~ ΛAA/) && (Sline =~ MODEL=/)) { @atrlist=split(" ",$line); $model=$atrlist[-l]; Smodel — s/MODEL=PAD _//; if ((Smodel >= Slinec)) {

$atrlist[- 1 ]="MODEL=OB ATP AST" ;

;^— > print OUT @atrlist; print OUT "Vn";

} else { print OUT Sline;

} } else { print OUT Sline;

}

} close (OUT); close (INPUT); system("mv Stempfile Sschematic"); print "Complete for Pass-through model insertionVn"; print ^»*********************ΓNSERT TEXT INTO SCHEMATIC open(INPUT, "<$schematic") || die "Can not open SschematicVn"; oρen(OUT,">$tempfile")|| die "can not open temp fileVn"; @wholefile=<ιNPUT>; foreach Sline (@wholeϊϊle) { if (Sline =~ ΛAT/) {

Sline =~ s/OBAT_TITLE/$title/; Sline =~ s/OBATJJNE01/$line01/;

Sline =~ s/OBAT_LrNE02/$line02/; Sline =~ s/OBAT JLrNE03/$line03/; Sline =~ s/OBAT_LINE04/$line04/; Sline =~ s/OBAT_LINE05/$line05/; Sline =~ s/OBATJLINE06/$line06/;

Sline =~ s/OBAT_LINE07/Sline07/; Sline =~ s/OBAT_LlNE08/$line08/; Sline — s/OBAT J INE09/$line09/; Sline =~ s/OBAT_LINE10/$linelO/; } print OUT Sline;

} close (OUT); close (INPUT); system("mv Stempfile Sschematic"); print "Complete for Text insertion! Vn";

#

# Subroutines-

# sub linecount{ local($filename)=@_; open (IN, Sfilename); Slinenum = 1 ; while (<IN>) {

Slinenum4-4-;

sub getinput { local ($ string) = @_ local Sfile; while(l) { print "$ string "; chop($file = <STDIN>); return Sfile;

} I sub gettimestamp {

($sec,$min,$hour,Smday,$mon,Syear,Swday,$yday,$isdst) = localtime (time); $mon=$mon4-l; if (length (Smon) eq 1) {$mon="0$mon" ;} if (length (Smday) eq 1 ) {$mday="0$mday" ;} if (length (Shour) eq 1 ) {$hour="0$hour" ;} return "$mon/$mday/$year $hour:$min:$sec"; }

OBATconfigure

#!/usr/local/bin/perl5

#

# Inserting signal names from pin Location table into schematic #

# Usage:

# OBATconfigure ProcessID configure _fϊle topJevel_schematic

#

# if ($#ARGV 4-l < 4 ) { print "***Welcome to S3 OBAT Signal Name Insertion Program ********\n"; print " * Tool : OBATconfigure* * ************ *\n" ; print "Usage: Vn"; print "OBATconfigure processID configure top_level_schematic destination Jirrectory

VnVn"; exit(l);

} SprocessID=SARGV[0]; $configure=$ARGV[l]; Sschematic="SARGV[3]/sch/$ARGV[2]"; $temρfile="/tmp/obat$$" ; print "Process JD =$processIDVn"; print "Configure file=$configureVn"; print "Schematic file=$schematicVn"; if ((SprocessID =~ /025/)||($processιD — /031/)|| (SprocessID =~ /022/)) #processing the configure file to make up the pinname related core Jms signal set up

{ open(CONF, Sconfigure) || die "Can't open the configuration file Sconfigure : $! Vn"; while(<CONF>)

{ if(!/^Λ#/)

{ chop($J; _,

(Spinname, @sig_pairs) = split(Λs+/, $ J; if( Spinname =~ Λw4-/ )

{ undef($core_sigs); for(Si=0; Si <= $#sig_pairs; $i++)

{ ($sig_name, Sval) = split(/=/, Ssig_pairs[$i]); if($val eq "l")

{

$core_sigs = $core_sigs . ",VCCQ";

} elsif($val eq "0")

{

$core_sigs = $core_sigs . ",VSSQ";

} else {

$core_sigs = $core_sigs . ",$val";

} if (Si =0) {$core_sigs =~ s/,//g ;} $new_pinname=$pinname. "_P AD" ; $new_core_sigs{$new_pinname} = Score_sigs

close(CONF);

10 ## processing the schmatic file open(SCH, "<S schematic") || die "Can't open the schematic file Sschematic:S! Vn"; open(TMP, ">$tempfile") || die "Can't open the Stempfile to write : $! Vn"; while(($line = <SCH>) && defmed(%new_core_sigs))

15 { if( (Sline =~ /^ΛLVs4-/) &&($line=~/_PAD/)&& ! (Sline =~ /COREXXX/))

{ print "SlineVn"; 20 chop(Sline);

@elements = split(Λs4-/,$line); if (@elements[l] = "610") {$x_cord="510"} if (@elements[l] = "830") {$x_cord="740"}

$y_cord=@elements[2]; 25 # Sx_cord = @elements[l] - 105;

# $y_cord = @elements[2] 4- 5;

Spinname = $elements[9]; if(defmed($new_core_sigs {Spinname} )) 30 {

Stoken = "L" . " " . $x_cord . " " . $y_cord; Scurjoc = tell(SCH);

## search the coordinate corresponding COREXXX line from the begining of the file 35 seek(SCH,0,0);

Sln_cnt = 0; while(<SCH>)

{ Sln_cnt-H-;

40 if(/^Λ$tokenVb/)

{ if (Spinname =~ "SDCLK") {

$new_content=$token . " 4 0 3 0 1 0 " . $new_core_sigs {Spinname} ;

} 45 else {

$new_content=Stoken . " 4 0 3 0 1 0 " . Snew_core_sigs {Spinname} ;

}

SmodifyJines{$ln_cnt} = $new_content ;

}

JO

## go back to a new pinname processing seek(SCH, Scurjoc, 0);

}

JJ

## starting to generate the tmp schmatic output seek(SCH, 0, 0); Sln_cnt = 0; while(<SCH>)

I

Sln_cnt-H-; if(defined($modifyJines{$ln_cnt}))

{ print TMP "$modifyJines{Sln_cnt} Vn"; } else

{ print TMP $_;

close(SCH); close(TMP); if( (Srtn = systemC'mv Stempfile Sschematic")) != 0)

{ print "mv Stempfile Sschematic fail, program abort ... \n"; exit(l);

} print " Vn"; print "-Please open schematic Sschematic for editing Vn"; print " Vn"; print "- Any question please direct to OBAT team ! Thanks. Vn"; print " Vn";

}

# sub getinput { local Sprocess; while(l) { chop($process = <STDIN>); return Sprocess; } }

obat4.mod

/* obat.mod j AHDL modules for SpectreHDL simulation fro OBAT project

Revision Note:

03/20/97 - debug measuret and measuret2 module -CJH

03/19/97 - Disable clklow and elk high checking for sdram -CJH 0 Jan 22 97 - obat.mod is born -CJH

*/

module chkminmax (pin) (delay, vmin, vmax) 5

/* chkminmax module will report maximum throughout the sim if maximum voltage is greater than vmax. It will report minimum if minimum is less than vmin. Only start checking after time specified by delay. */ 0 node pin; parameter real delay, vmin, vmax;

{ real vol, now, mintime, maxtime, minval. maxval; initial { 5 } analog { vol = val(pin); now = $time(); if ((vol > vmax)&&(now > delay)) { 0 maxval=vol; maxtime=now;

} if ((vol < vmin)&&(now > delay)) { minval=vol; 5 mintime=now;

}

} final { if (maxval > vmax) { 0 $strobe("###Vn");

$strobe("### %I : High voltage of %4g is measured at %eVn", maxval, maxtime);

$strobe("###Vn");

} 5 if (minval < vmin) {

$strobe("###Vn"); $strobe("### %I : Low voltage of %4g is measured at %eVn", minval, mintime); $strobe("###Vn"); 0 }

}

} module sub Jolf (dq, dqi) J /* sub Jolf module is the package model including parasitic inductance and capacitance from bonding pad, lead frame, and bond wire, dq is external pin to PCB and dqi is the internal pin to silicon. */ node [V, I] dq, dqi; ' node [V, I] h,j,k,l; initial {

} analog {

/* inductors */

V(dq, h) <- dot(1.3e-9*I(dq, h)); V(j, k) <- dot(0.2e-9*I(j, k));

V(k, 1) <- dot(4e-9*I(k, 1));

/* capacitors */

1(h) <- dot(0.29e-12*V(h));

I(k) <- dot(0.29e-12*V(k)); I(dqi) <- dot(0.4e-12*V(dqi));

/* resistor */

V(h, j) <- (4.0*I(h,j));

V(l, dqi) <- (1.08*1(1, dqi));

} final {

} }********************************************************************** module checksh (d, elk) (delay, trig_val, setup, hold)

/* checksh module will report setup and hold time violation. It will only look at the first postive edge elk after delay and it cannot cannot handle negative setup/hold time. This module will report setup and hold time it measured if no violation is found.*/ node d, elk; parameter real delay, trig_val, setup, hold;

{ real clkedge=-l, drisetime=-l, dfalltime=-l ; real setuptime, holdtime; integer ierror=0 ; initial {

} analog { if (($threshold((val(d) - trig_val), l))&&(Stime() > delay)) { drisetime = $time();

} if (($threshold((val(d) - trig_val), -l))&&(Stime() > delay)) { dfalltime = StimeO;

} if (($threshold((val(clk) - trig_val), l))&&(Stime() > delay)) { clkedge = $time();

} } final { if (drisetime < 0){

Sstrobe("###Vn");

Sstrobe("### %I : Error. Data rise time not found.Vn"); Sstrobe("###Vn"); ierror=l;

} if (dfalltime < 0){ $strobe("#a#Vn");

Sstrobe("### %I : Eπor. Data fall time not found.Vn");

Sstrobe("###Vn"); ieπor=l ;

} if (clkedge < 0) {

Sstrobe("###Vn");

Sstrobe("### %I : Error. Clock rise time not found.Vn"); Sstrobe("###Vn"); ieπor=l;

} if (ieπor = 0) { if (drisetime > dfalltime) { /* data fall and rise */ setuptime = clkedge - dfalltime; holdtime = drisetime - clkedge;

} if

{ /* data rise and fall */ setuptime = clkedge - drisetime; holdtime = dfalltime - clkedge;

} if ((setuptime < setup) && (holdtime < hold)) { $strobe("###Vn"); Sstrobe("### %I : Fail setup and hold time at %9.3eVn", clkedge);

$strobe("### setup time = %9.3e (req: %9.3e)Vn", setuptime, setup); $strobe("### hold time = %9.3e (req: %9.3e)Vn", holdtime, hold); $strobe("###Vn");

} else if ((setuptime < setup) && (holdtime > hold)) { $strobe("###Vn");

$strobe("### %I : Fail setup time at %9.3eVn", clkedge); Sstrobe("### setup time = %9.3e (req: %9.3e)Vn", setuptime, setup); $strobe("###Vn"); } else if ((setuptime > setup) && (holdtime < hold)) { $strobe("###Vn");

Sstrobe("### %I : Fail hold time at %9.3eVn", clkedge); Sstrobe("### setup time = %9.3e (req: %9.3e)Vn", setuptime, setup); Sstrobe("###Vn"); gisg { $strobe("###Vn");

$strobe("### %I : Pass setup/hold time check.Vn"); $strobe("### setup = %g ; hold = %gVn", setuptime, holdtime); $strobe("###Vn"); }

}

} /**********************************************************************/ module sdramcore (elk, dO) (ov, trig_val, tacc, toh, clkhigh, clklow)

/* clkhigh, clklow checking disable for now. 3/19/97 CJH */

/* sdramcore module emulate core function for sdram or sgram. It will toggle dO pin after access time tacc and maintain level for toh after second clock, ov is original voltage value for dO (0 or 1), clkhigh/clklow gives the minimum time for elk high and elk low. This module will flag if these times are not met. For pratical reason, ignore hi-Z operation */ node [V, I] elk, dO; parameter real trig_val, tacc, toh; /* clkhigh, clklow; */ parameter integer ov;

{ node [V, I] out;

/* 10 ohm is output resistance - this number could be tweaked */ real rout=10; real tacci; real startime=100, stoptime=100; /* clkhighstart— 1, clklowstart=-l ; * ' integer ichange=0, jchange=0, count=0, x=0;

10 initial { tacci = tacc-1.37e-9; /* adjust for package effect */ x = ov;

} 15 analog {

/* For the data output portion */ if ((Sthreshold((val(clk) - trig_val), 1)) && (count=0)) { startime = Stime() 4- tacci;

old((val(clk) - trig_val),-l)) && (count=l)) { count44-;

} 5 if (($threshold((val(clk) - trig_val), 1)) && (count=2)) { stoptime = Stime() 4- toh; count44-;

} if (($time() > startime) && (ichange=0)) { 30 x = !x; ichange44-;

} if (($time() > stoptime) && (jchange=0)) { x = !x; 3J jchange44-;

}

V(out) <- $transition(2.0*trig_val*x, 0, le-9, le-9);

/* For output equivalent driver */

40

V(d0, out) <- rout*I(dO, out);

/* Checking elk high and low time */

45 /* if ($threshold((val(clk) - trig_val), 1)) { clkhighstart = $time(); if ((clkhighstart - clklowstart) < clklow) { $strobe("###Vn");

Sstrobe("### Error. Not enough elk low time from %e to %eVn", 50 clklowstart, clkhighstart);

$strobe("###Vn");

} } if ($threshold((val(clk) - trig_val), -1)) { JJ clklowstart = $time(); if ((clklowstart - clkhighstart) < clkhigh) { Sstrobe("###Vn");

Sstrobe("### Eπor. Not enough elk high time from %e to %eVn", clkhighstart, clklowstart);

Sstrobe("###Vn");

} } */

} final {

} I_{*********************************************************************} module sdramcore2 (cen, re, elk, dO) (ov, trig_val, tacc, toh, clkhigh, clklow)

/* add re pin for read enable */

/* clkhigh, clklow checking disable for now. 3/19/97 CJH */ I* sdramcore module emulate core function for sdram or sgram. It will toggle dO pin after access time tacc and maintain level for toh after second clock, ov is original voltage value for dO (0 or 1), clkhigh/clklow gives the minimum time for elk high and elk low. This module will flag if these times are not met. For pratical reason, ignore hi-Z operation */ node [V, I] cen. re, elk, dO; parameter real trig val, tacc, toh; /* clkhigh, clklow; */ parameter integer ov;

{ node [V, I] out;

/* 10 ohm is output resistance - this number could be tweaked */ real rout; real startime=100, stoptime=100; /* clkhighstart— 1, clklowstart— 1 ; */ real fliptime=100; real tacci; integer ichange=0, jchange=0, count=0, x=0, fchange=0, newcount=0, newcountl=0; initial { tacci = tacc - 1.37e-9; /* adjust for package effect */ x = ov;

} analog { /* For the data output portion */ if (( V(re) > trig_val) && ( V(cen) <= trig_val)) { rout = 10; } else {rout = 100000000; } /* if ( V(re) <= trig_val) { rout = 100000000; } */ if (($threshold((val(clk) - trig_val), 1)) && (count=0)) { startime = Stime(); startime = startime 4- tacci;

if (($threshold((val(clk) - trig_val),-l)) && (count=l)) { count44-; } if (($threshold((val(clk) - trig_val), 1)) && (count=2)) { stoptime = Stime(); stoptime = stoptime 4- toh; count44-; } if (($threshold((val(clk) - trig_val),-l)) && (count=3)) {

C0Unt44-; if (($threshold((val(clk) - trig_val), 1)) && (count=4)) { startime = Stime(); startime = startime 4- tacci; count44-; newcount = 1 ;

} if ((Sthreshold((val(clk) - trig_val),-l)) && (count=5)) { old((val(clk) - trig_val), 1 )) && (count=6)) { = Stime(); = stoptime 4- toh;

newcount 1 = 1; } if (($time() > startime) && (ichange=0)) { x = !x; ichange44-;

} if ((Stime() > stoptime) && (jchange=0)) { x = !x; jchange44-; fliptime = Stime(); fliptime = fliptime 4- 2.0e-9; if ((Stime() > fliptime) && (fchange=0)) { x = !x; fchange44-;

} ) if ((Stime() > startime) && (newcount=l)) { x = !x; newcount44-;

} if (($time() > stoptime) && (newcount 1=1)) x = !x; newcount 1-. . , fliptime = $time(); fliptime = fliptime 4- 2.0e-9;

} V(out) <- Stransition(2.0*trig_val*x, 0, le-9, l e-9);

/* For output equivalent driver */

V(d0, out) <- rout*I(dO, out);

/* Checking elk high and low time disabled*/

} final { /* $strobe("the value of count=%dVn", count); */ } } ************************************************************************/ module sgram (elk, adO, adl, ad2, dO, dl, d2, d3, d4, d5, d6, d7, d8, d9, dlO, dl 1, dl2, dl3, dl4, dl5) (trig_val, cin, cout. tacc, toh, clkhigh, clklow) /* sdram module is the top level sdram/sgam module that could be called in AHDL simulation. It consists of three address pin for measuring signal traveling from S3 chip to memory, pd pin will toggle, this is for measuring signal from memory to S3 chip. This module put together package model for I/O pin, input capacitance and output capacitance loading. */

node [V,I] elk, adO. adl, ad2, dO, dl, d2, d3, d4, d5, d6, d7, d8; node [V,I] d9, dlO, dl l, dl2, dl3, dl4, dl5; 10 parameter real trig val, cin, cout, tacc, toh, clkhigh, clklow;

{ node [V,I] adOi, adli, ad2i, dOi, dli, d2i, d3i, d4i, d5i, d6i, d7i, d8i; node [V,I] d9i, dlOi, dl li, dl2i, dl3i, dl4i, dl5i, clkin; real cini, couti;

15

/* connect to other module thru declare section */ /* Address input package model */ subjolf adiolfO(adO, adOi); /* adOi is bonding pad */ sub Jolf adiolfl (adl, adli); 20 subjolf adiolf2(ad2, ad2i); /* elk package model */ subjolf clkiolf(clk, clkin); /* sdram core function */

bj lf d lΩ(dl dli) subjolf doutlf2(d2, d2i); subjolf doutlD(d3, d3i); subjolf doutlf4(d4, d4i); subjolf doutlf5(d5, d5i); subjolf doutlf6(d6, d6i); sub Jolf doutlf7(d7, d7i); subjolf doutlf8(d8, d8i); subjolf doutlf9(d9, d9i); subjolf doutlΩO(dlO, dlOi); subjolf doutlfl l(dl 1, dl li); subjolf doutlfl2(dl2, dl2i); subjolf doutlΩ3(dl3, dl3i); subjolf doutlΩ4(dl4, dl4i); subjolf doutlΩ5(dl 5, dl5i); initial { /* cin, cout number are from spec, deduct lpF in package */ cini = cin - 1.0e-12; couti = cout - 1.0e-12; } analog {

/* Input cap loading for address pin */ I(adθi) <- dot(cin*V(adOi)); I(adli) <- dot(cin*V(adli)); I(ad2i) <- dot(cin*V(ad2i));

/* elk inp cap */

I(clkin) <- dot(cini*V(clkin)); I* output cap */

I(dθi) <- dot(couti*V(dOi));

I(dli) <- dot(couti*V(dli));

I(d2i) <- dot(couti*V(d2i));

I(d3i) <- dot(couti*V(d3i)); I(d4i) <- dot(couti*V(d4i));

I(d5i) <- dot(couti*V(d5i));

I(d6i) <- dot(couti*V(d6i));

I(d7i) <- dot(couti*V(d7i));

I(d8i) <- dot(couti*V(d8i)); I(d9i) <- dot(couti*V(d9i));

I(dlθi) <- dot(couti*V(dlOi));

I(dl li) <- dot(couti*V(dl li));

I(dl2i) <- dot(couti*V(dl2i));

I(dl3i) <- dot(couti*V(dl3i)); I(dl4i) <- dot(couti*V(dl4i));

I(dl5i) <- dot(couti*V(dl5i));

} final { }

} ************************************************************************/ module sg32256 (cen, re, elk, adO, adl, ad2, ad3, ad4, ad5, ad6, ad7, ad8, ad9, adlO, dO, dl, d2, d3, d4, d5, d6, d7, d8, d9, dlO, dl i, dl2, dl3, dl4, dl5, dl6. dl7, dl8, dl9, d20, d21. d22, d23, d24, d25, d26, d27, d28, d29, d30, d31) (trig_val, cin, cout. tacc, toh, clkhigh, clklow) / * sdram module is the top level sdram/sgam module that could be called in AHDL simulation. It consists of three address pin for measuring signal traveling from S3 chip to memory, pd pin will toggle, this is for measuring j signal from memory to S3 chip. This module put together package model for I/O pin, input capacitance and output capacitance loading. */

node [V,I] cen, re, elk, adO, adl, ad2, ad3, ad4, ad5, ad6, ad7, ad8, ad9. adlO; 10 node [V,I] dO, dl, d2, d3, d4, d5, d6, d7, d8, d9, dlO, dl i, dl2, dl3, dl4, dl5, dl6, dl7; node [V,I] dl8, dl9, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31 : parameter real trig_val, cin, cout, tacc, toh, clkhigh, clklow;

{ node [V,I] adOi. adli, ad2i, ad3i, ad4i. ad5i, adόi, ad7i, ad8i, ad9i,adl0i; 15 node [V,I] dOi, dli, d2i, d3i, d4i, d5i, d6i, d7i, d8i; node [V,I] d9i, dlOi, dl li, dl2i, dl3i, dl4i, dl5i, clkin; node [V,I] dl6i, dl7i, dl8i, dl9i, d20i, d21i, d22i, d23i, d24i, d25i, d26i; node [V,I] d27i, d28i, d29i, d30i, d31i; real cini,couti;

20

/* connect to other module thru declare section */ /* Address input package model */ subjolf adiolfO(adO, adOi); /* adOi is bonding pad */ subjolf adiolfl (adl, adli); 25 subjolf adiolf2(ad2, ad2i); subjolf adiolf3(ad3, ad3i); subjolf adiolf4(ad4, ad4i); subjolf adiolf5 (ad5 , ad5 i) ; subjolf adiolf6(ad6, adόi); 30 subjolf adiolf7(ad7, ad7i); subjolf adiolf8(ad8, ad8i); subjolf adiolf9(ad9, ad9i); subjolf adiolflO(adlO, adlOi); /* elk package model */ 35 subjolf clkiolf(clk, clkin); /* sdram core function */ sdramcore2 corepdO(cen, re, clkin, dOi) (ov=0, trig_val=trig_val, tacc=tacc, toh=toh,

subjolf doutlfl4(dl4, dl4i) subjolf doutlfl5(dl 5, dl5i); subjolf doutlfl6(dl 6, dl6i); subjolf doutlfl7(dl 7, dl7i); subjolf doutlfl8(dl 8, dl8i); subJolf doutlfl9(dl9, dl9i); subjolf doutlf20(d20, d20i); subjolf doutlf21(d21, d21i); subjolf doutlf22(d22, d22i); subjolf doutlf23(d23, d23i); sub Jolf doutlf24(d24, d24i); subjolf doutlf25(d25, d25i); subjolf doutlf26(d26, d26i); subjolf doutlf27(d27, d27i); subjolf doutlf28(d28, d28i); sub Jolf doutlf29(d29, d29i); subjolf doutlf30(d30, d30i); sub Jolf doutlf31(d31, d31i); initial { /* cin, cout number are from spec, deduct IpF in package * ' cini = cin - 1.0e-12; couti = cout - 1.0e-12;

} analog { /* Input cap loading for address pin */

I(adθi) <- dot(cini*V(adOi));

I(adli) <- dot(cini*V(adli));

I(ad2i) <- dot(cini*V(ad2i));

I(ad3i) <- dot(cini*V(ad3i)); I(ad4i) <- dot(cini*V(ad4i));

I(ad5i) <- dot(cini*V(ad5i));

I(ad6i) <- dot(cini*V(ad6i));

I(ad7i) <- dot(cini*V(ad7i));

I(ad8i) <- dot(cini*V(ad8i)); I(ad9i) <- dot(cini*V(ad9i));

I(adlθi) <- dot(cini*V(adlOi));

/* elk inp cap */

I(clkin) <- dot(cini*V(clkin));

/* output cap */

I(dθi) <- dot(couti*V(dOi));

I(dli) <- dot(couti*V(dli));

I(d2i) <- dot(couti*V(d2i)); I(d3i) <- dot(couti*V(d3i));

I(d4i) <- dot(couti*V(d4i));

I(d5i) <- dot(couti*V(d5i));

I(d6i) <- dot(couti*V(d6i));

I(d7i) <- dot(couti*V(d7i)); I(d8i) <- dot(couti*V(d8i));

I(d9i) <- dot(couti*V(d9i));

I(dlθi) <- dot(couti*V(dlOi));

I(dl li) <- dot(couti*V(dl li));

I(dl2i) <- dot(couti*V(dl2i)); I(dl3i) <- dot(couti*V(dl3i));

I(dl4i) <- dot(couti*V(dl4i));

I(dl5i) <- dot(couti*V(dl5i));

I(dl6i) <- dot(couti*V(dl6i)); I(dl7i) <- dot(couti*V(dl7i)

I(dl8i) <- dot(couti*V(dl8i)

I(dl9i) <- dot(couti*V(dl9i)

I(d20i) <- dot(couti*V(d20i) s I(d21i) <- dot(couti*V(d21i)

I(d22i) <- dot(couti*V(d22i)

I(d23i) <- dot(couti*V(d23i)

I(d24i) <- dot(couti*V(d24i)

I(d25i) <- dot(couti*V(d25i) 10 I(d26i) <- dot(couti*V(d26i)

I(d27i) <- dot(couti*V(d27i)

I(d28i) <- dot(couti*V(d28i)

I(d29i) <- dot(couti*V(d29i)

I(d30i) <- dot(couti*V(d30i) 15 I(d31i) <- dot(couti*V(d31i)

} final {

} 0 I*_**_**_**_**_***_***_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_**_***_***_**_**_**_**_**_**_**_**_*****

/* measuret uses delay after which only measurements can be made. AS soon as delay is satisfied, measurements for trigger and target are made from the very first trig_val and 5 targ_val crossings. */ module measuret (trigjn, targjn) (delay, nstart, nstop, trigjval, targjval)

/* measuret module will report time delay from trigger to target time. 0 If nstart or nstop > 0, it is looking for low->high edge; otherwise it is looking for high->low edge, trigjval and targ_val specified the threshold voltage. It only starts looking after time specified by delay. */ node trigjn, targjn; 35 parameter real delay, trig_val, targjval; parameter integer nstart, nstop;

{

/* trigger & target variables*/ integer i = 1, j = 1, k = 1, 1 = 1, m = 1, n = 1, d = 1, e = 1; 40 integer y = 0, z = 0, a = 0, b = 0, c = 0; integer pos rigtran = 0, neg rigtran = 0, trigtran = 0; integer pos argtran = 0, neg argtran = 0, targtran = 0; integer itrigdir, itargdir; real trigTime = 0, negtrigTime = 0, postrigTime = 0; 45 real targTime = 0. negtargTime = 0, postargTime = 0; string trigdir, targdir; /* stream fptr;*/ real trigger ran[ 10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; real target _tran[ 10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; JO real false rigtran_LH[ 10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0} real false rigtran_HL[ 10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0} real false _targtran_LH[ 10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0} real false _targtran_HL[ 10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0} integer nstarti, nstopi; JJ initial {

/* fptr = $fopen("analysis/%I", "a");*/ if(nstart > 0) { itrigdir=l ; trigdir = "rise"; } else if (nstart < 0) { itrigdir=-l ; nstarti = -1 * nstart; trigdir = "fall"; } else { itrigdir=0; trigdir = "cross"; } if (nstop > 0) { itargdir=l ; targdir="rise"; } else if (nstop < 0) { itargdir=-l; nstopi = -1 * nstop; targdir="fall"; } else { itargdir=0; targdir="cross";

} } analog { /* start of trigger measurement*/

/*initial trigger & subsequent trigger transition in itrigdir dir.(noise/glitch) measurements. Also, previous -itrigdir transition time stored in a variable, to be transferred to array*/ if (($threshold((val(trig Jn) - trigjval), itrigdir)) && ($time() > delay)) { if (i = nstarti) {

44-a; false rigtran_LH[a] = negtrigTime; false rigtran_HL[a] = postrigTime; trigTime = $time(); trigtran44-; i-; j-s k-; } i++; j++; k44-;

}

/*noise/glitch transition in -itrigdir direction time measurement & previous itrigdir direction transition time stored in a variable to be later stored in an array.*/ if (Sthreshold((val(trigJn) - trigjval), -1) && (trigtran > 0) &&(itrigdir > 0) &&($time() > delay)) { if(j = nstarti) {

++y; trigger ran[y] = trigTime; negtrigTime = Stime(); neg_trigtran44-;

}

} /* noise/glitch transition in -itrigdir direction time measurement & previous itrigdir direction transition time stored in a variable to be later stored in an array.*/ if (Sthreshold((val(trigJn) - trigjval), 1) && (trigtran > 0) && (itrigdir < 0) && ($time() > delay)) { if (k == nstarti) {

4-4-y; trigger ran[y] = trigTime; postrigTime = $time(); pos rigtran44-; }

}

/* start of target measurement*/ /^initial trigger & subsequent trigger transition in itrigdir dir.(noise/glitch) measurements. Also, previous -itrigdir transition time stored in a variable, to be transferred to array*/ if ((Sthreshold((val(targJn) - targjval), itargdir)) && ($time() > delay)) { if (l = nstopi) { 44-b; falseJargtran_LH[b] = negtargTime; false targtran_HL[b] = postargTime; targTime = $time(); targtran44-; 1-; m-; n~;

}

144-; m++;

} /*noise/glitch transition in -itrigdir direction time measurement & previous itrigdir direction transition time stored in a variable to be later stored in an array.*/ if ((Sthreshold((val(targJn) - targjval), -1) && (targtran > 0) &&(itargdir > 0)) && (Stime()

> delay)) { if (m = nstopi) { 44-z; target Jran[z] = targTime; negtargTime = $time(); neg argtran44-;

} } /* noise/glitch transition in -itrigdir direction time measurement & previous itrigdir direction transition time stored in a variable to be later stored in an array.*/ if ((Sthreshold((val(targJn) - targ_val), 1) && (targtran > 0) && (itargdir < 0)) && ($time()

> delay)) { if (n = nstopi) {

44-z; target Jran[z] = targTime; postargTime = $time(); pos_targtran44-; }

} } final { /* printing to a file trigger/target values, number of transitions thru trigger/target points for lh and hi trigger/target and time instant when these transitions occured*/ Sstrobe("### %I: Tpd = %9.3e : Trig@ %9.3e %s -> Targ@ %9.3e %sVn", target Jran[ 1 ] - trigger Jran[ 1 ] , trigger Jran[ 1 ] , trigdir, target Jran[ 1 ] , targdir) ; if(((target ran[l] - trigger ran[l]) < 0) && ((target ran[l] - trigger ran[l]) >= -1.000e-09))

{

Sstrobe("check trigger & target, it may be OKVn"); i for (d = l ; d < 10; d4-+) z = e;

* Ins glitch window is provided to avoid "target before trigger" conflicts for dataout to strobe measurements. But need to verify target-trigger numbers if fishy numbers are seen.

*/ if((target ran[z] - trigger ran[l]) < 0){

44-z;

44-e;

Sstrobe("target before trigger! ! ! or target not found! ! ! .Vn"); Sstrobe("if target-trigger is < 0ns but > -4.5ns,Vn"); Sstrobe(" check trigger and target, data to data delay is OKVn"); Sstrobe("### %I: Tpd = %9.3e : Trig@ %9.3e %s -> Targ@ %9.3e %sVn", target ran[z] - trigger ran[l], trigger ran[l], trigdir, target tran[z], targdir); }

}

$strobe("### trigtran = %4d neg rigtran = %4d pos rigtran = %4dVn", trigtran, negjrigtran, pos rigtran);

Sstrobe("### targtran = %4d neg argtran = %4d pos Jargtran = %4dVn", targtran, negjargtran, pos argtran);

Sstrobe("###triggerJran = %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3eVn", triggerjran[l], trigger ran[2], trigger ran[3], trigger ran[4], trigger ran[5], trigger_tran[6], trigger_tran[7], trigger_fran[8], trigger _tran[9]); Sstrobe("###falseJrigtran_LH = %9.3e, %9.3e, %9.3e, %9.3eVn", false rigtran_LH[2], falseJrigtran_LH[3], falseJrigtran_LH[4],falseJrigtran_LH[5]);

Sstrobe("###falseJrigtran_HL = %9.3e, %9.3e, %9.3e, %9.3eVn", false rigtranjHL[2], falseJrigtran_HL[3], falseJrigtran_HL[4],false rigtran_HL[5]); Sstrobe("###targetJran = %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3e, %9.3eVn", target ran[l], target ran[2], target ran[3], target ran[4], target ran[5], target ran[6], target ran[7], target ran[8], target ran[9]);

Sstrobe("###falseJargtran_LH = %9.3e, %9.3e, %9.3e, %9.3eVn", false argtran_LH[2], false argtran_LH[3], false argtran_LH[4], falseJargtran_LH[5]); Sstrobe("###falseJargtran_HL = %9.3e, %9.3e, %9.3e, %9.3eVn", false Jargtran JIL[2], false argtran JJL[3], false argtran_HL[4], falseJargtranjHL[5]); Sstrobe("###Vn"); /* Sfclose(fptr);*/ } }

/* lβ.mod */ module resistor; module inductor; module capacitor; module lf(u2, ul, pad, dl, d2, pin) (cl, c2, 11, rl, cml, cm2, lw,r2) node [V,I] u2, ul, pad, dl, d2, pin; parameter real cl, c2, 11, rl, cml, cm2, lw, r2;

{ node [V, I] padi,padii; real cmml, cmm2;

/* inductor */ inductor Ll(pad, padi) (l=lw); inductor L2(padii, pin) (1=11);

/* capacitor */ cmm2 = 2.0*cm2; cmml = 2.0*cml; capacitor Cl(ul, padi) (c=cmm2); capacitor C2(u2, pin) (c=cmml); capacitor C3(dl, padi) (c=cmm2); capacitor C4(d2, pin) (c=cmml);

/* resistor */ resistor Rl(padii, pin) (r=rl); resistor R2(padii, padi) (r=r2); analog {

I(padii) <- dot(c2*V(padii)); I(pin) <- dot(cl*V(pin)); }

}

module ddrcore (elk, clkn, dqs, dqO, dq2) (tcycle, tcoqs, tdqqs, trpst) I* ddr sgram assuming CL=2 BL=4 */ node [V, I] elk, clkn, dqs, dqO, dq2; parameter real tcycle, tcoqs, tdqqs, trpst;

{ node [V, I] dqsi, dqOi, dq2i; real preambstart=100, dqsstart=100.0, routdqs=le6; real postambstart=100, dt02, dq02start=100, dq02stop=100; real dq02toggle= 100; real routdq0=le6, routdq2=le6; integer count=0, iinit=0, xdqsi=0, ibl=4; /* burst length=4 */ integer xdq02i=0, idqs=0, idq02=0; initial { dt02 = tdqqs; /* dqO and dq2 lag the DQS by tdqqs */ } analog {

/* initial setting of internal node */ if (iinit = 0) {

V(dqsi) <- 0; V(dqθi) <- 0; V(dq2i) <- 2.5; iinit = 1 ; }

/* rout control tristate of output */ V(dqs, dqsi) <- routdqs * I(dqs, dqsi); V(dq0, dqOi) <- routdqO * I(dq0, dqOi); V(dq2, dq2i) <- routdq2 * I(dq2, dq2i); if ((Sthreshold((val(clk) - val(clkn)), 1)) && (count=0)) preambstart = Stime()4-tcoqs; dqsstart = preambstart 4- tcycle; dq02start = dqsstart 4- tdqqs; dq02toggle = dq02start; count44-;

10

/* DQS preamble and postamble */ if (($time() >= preambstart) && (Stime() < postambstart)) routdqs=30; } else { y routdqs=le6;

}

/* DQO DQ2 start and stop */ if ((StimeO >= dq02start) && (StimeO < dq02stop)) { 20 routdq0=30; routdq2=30; } else { routdq0=30; /* Remove the tri-state drive */ routdq2=30;

25 }

/* DQO DQ2 go back to original state */ if ($time() >= dq02stop ) { V(dqθi) <- 0; 30 V(dq2i) <- 2.5;

}

/* dqsi signal control */ $break_point(dqsstart) ; 35 if (($time()-dqsstart) >= 0.0 ) { dqsstart = Stime()4-tcycle/2.0; if (idqs=(ibl-l)) { postambstart = $time() 4- trpst;

} 40 if (idqs < ibl) { xdqsi = ϊxdqsi; idqs44-;

} } 45 V(dqsi) <- $transition(2.5*xdqsi, 0, le-10, le-10);

/* dqOi & dq2i signal control */ Sbreak_point(dq02toggle); if ((Stime()-dq02toggle) >= 0 ) { JO if (idq02 <= ibl) { if (idq02=0) { xdq02i=l; dq02toggle = Stime()4-tcycle/2.0-2.0*dt02;

} JJ if (idq02=l) { xdq02i=0; dq02toggle = $time()4-tcycle/2.0; if (idq02=2) { xdq02i=0; dq02toggle = $time()+tcycle/2.0+2.0*dt02;

I if (idq02=3) { xdq02i=l; dq02toggle = Stime()4-tcycle/2.0-2.0*dt02; if (idq02=4) { xdq02i=0;

I* Sstrobe("dq02toggle= %eVn", dq02toggle); */ idq02-H-;

V(dqθi) <- Stransition(2.5*xdq02i, 0, le-10, le-10); V(dq2i) <- Stransition(2.5*(!xdq02i), 0, le-10, le-10);

}

}

module sub Jdrpkg (dq, dqi) */

p_m

— C

I

GND

*/ node [V, I] dq, dqi;

{ node [V, I] h; initial { } analog { /* inductors */

V(dqi, h) <- dot(5.8e-9*I(dqi, h)); /* L=5.8nH */ /* capacitors */ I(dq) <- dot(1.3e-12*V(dq)); /* C=1.3pF */

/* resistor */

V(h, dq) <- (0.1550*I(h,dq)); /* R=0.155 ohm */ V(h, dqi) <- (10*I(h,dqi)); /* R=0.155 ohm */ } final {

} }

module ddrsgram (elk, clkn, dqs, dqO, dq2) (tcycle, tcoqs, tdqqs, trpst) node [V, I] elk, clkn, dqs, dqO, dq2; parameter real tcycle, tcoqs, tdqqs, trpst;

{ node [V, I] clki, clkni, dqsi, dqOi, dq2i; sub Jdrpkg padO(clk, clki); sub Jdrpkg padi (clkn, clkni); sub Jdrpkg pad2(dqs, dqsi); sub Jdrpkg pad3(dq0, dqOi); sub Jdrpkg pad5(dq2, dq2i); ddrcore sgramO (clki, clkni, dqsi, dqOi, dq2i) (tcycle=tcycle, tcoqs=tcoqs, tdqqs=tdqqs, tφst=trpst);

}

OBATsplits

#!/usr/local bin/perl5

# # OBATsplits

# * Conditon the netlist generated from wspice to be

# l)Spectre simulator compatible

# 2)Add/Modify parameters to configure fast/slowest senarios

# 3)Split out fast/slowest SPICE files for simulations #

# Usage:

# OBATsplits hspice_netlist file processID

#

# if ($#ARGV != l ) { print "***Welcome to S3 OBAT Spectre Run Spliter *********\_n ^». print "* Tool: makeOBATtrim************Vn"; print "Usage: Vn"; print "OBATsplits hspice_netlist file processID VnVn"; print "For example: Vn"; print "OBATsplits kv3.cir umc025 VnVn"; print "Available processID are: Vn"; print "umc025 tsmc025 tsmc031 tsmc035 umc035. VnVn"; exit;

}

Sdielectric Joss=l ;

$tempfile="/tmp/obat mpSS" ;

$cirfile=$A GV[$#ARGV-l]; $processID=$ARGV[$#ARGV-2];

$outformat="PSF ASCII";

$reltol=0.01; print "circuit file=$cirfileVn"; open(GETCIR,"<Scirfile") || die "can not open ScirfileVn"; @cir=<GETCIR>;

@cirtemp=@cir; close (GETCIR);

$temp="/tmp/temp$$"; open(TMP,">$temp")|| die "can not open temp fileVn"; $delete=0; foreach Sline (@cir) {

@splits=split(" ",$line); if($splits[3] =~ /mslinel/i) {

Sline =~ s/$ splits [ 1 ]/$ splits [ 1 ] PCB_GND/ ; Sline =~ s/$splits[2]/$splits[2] PCB_GND/ ;

Sline =~ s/$splits[3]/MSLINE/ ;

} if (($splits[0] =~ /^ΛC/i)&& ($splits[-l] =~Λ$V[pcV]/i)) {

$line="$splits[0] $splits[l] $splits[2] capacitor c=$splits[3]Vn"; print "Sline";

} if (Sline =~ /PCB_GND PCB_GND PCB_GND PCB_GND MSLINE/) {

$delete=l;

(Sdelete =l)&&($line =~ ΛA+/)) {

$delete=0; } else {

$delete=0; print TMP Sline;

} }

} 5 close(TMP); system("mv Stemp Scirfile"); #

# Modify Tline paramater to include dielectric loss # 10 if (Sdielectricjoss) { open(GETCIR,"<Scirfile") || die "can not open ScirfileVn"; @cir=<GETCIR>; @cirtemp=@cir; close (GETCIR); is Stemp="/tmp/tempSS"; open(TMP,">Stemp")|| die "can not open temp fileVn"; foreach Sline (@cir){ if (Sline =~ I tline /i) {

Sline =~ s/ tline / TLINE_S3 /i ;

20 } print TMP Sline;

} close(TMP); system("mv Stemp Scirfile");

25 } open(GETCIR,"<$cirfile") || die "can not open ScirfileVn"; @cir=<GETCIR>; @cirtemp=@cir; 30 oρen(TMP,">$temρfile")|| die "can not open StempfileVn"; $linec=l; # #

$deviceJib{"umc025"}="V"/nfs/proton/home/s31ib/obat/S3N025/spectre/umc/umc_s3n025.mo 3J dV";

$deviceJib{"tsmc025"}="V"/nfs/proton/home/s31ib/obat/S3N025/spectre/tsmc/tsmc_s3n025.m odV";

Sdevice Jib {"tsmc031 "}="V"/nfs/proton home/s31ib/obat/S3N03 l/spectre/tsmc/tsmc_s3n031.m odV"; 40 Sdevice Jib {"umc031 " }="V nfs/proton home/s31ib/obat S3N03 l/spectre/umc/umc_s3n031.mo dV";

Sdevice Jib {"umc022" } ="V"/nfs/proton/home/s31ib/obat/S3N022/spectre/umc/umc_s3n022.mo dV";

Sdevice Jib{"umc018"}="V"/nfs/proton/home/s31ib/obat/S3N018/spectre/umc/umc_s3n018.mo 45 dV"; if (SprocessID =~ /035/) { $vddd=3.3; $vdd=3.3; $vddw=5.0; JO $scale=l;

$vddwnode="VDDW"; } elsif($processID =~ /025/) { $vddd=3.30; $vddw=3.30; JJ Svdd=2.50;

$scale=0.75; Svddwnode=""; } elsif($ρrocessID =~ /031/) { Svddd=3.3; Svdd=3.3; Svddw=5.0; Sscale=0.9; j Svddwnode="VDDW";

} elsif (SprocessID =~ /022/) { Svddd=3.3; Svdd=1.8; Svddw=3.3; 10 Sscale=0.7;

Svddwnode=""; } elsif (SprocessID =~ /018/) { Svddd=3.3; Svddw=3.3; 15 Svdd=1.8;

Sscale=1.0; Svddwnode="";

}

$vdddff=Svddd*l.l; 0 Svdddtt=Svddd*1.0;

Svdddss=Svddd*0.9;

$vddff=Svdd*l.l;

$vddtt=Svdd;

$vddss=$vdd*0.9; 5 $pdtll=25.4e-3;

Spdtl2=25.4e-3;

$pdtl3=50.8e-3;

$ctll=25.4e-3;

Sctl2=25.4e-3; 0 Sctl3=25.4e-3;

Sctl4=25.4e-3;

Sctl5=25.4e-3;

$tvar=0.3;

Spdtll s=$pdtll *(l-$tvar); 35 $pdfl2s=$pdfl2*(l -Stvar);

Spdtl3 s=$pdtl3 * ( 1 -Stvar) ;

Sctlls=Sctll*(l-Stvar);

$ctl2s=$cfl2*(l -Stvar);

$ctl3s=Sctl3*(l-$tvar); 40 Sctl4s=Sctl4*(l -Stvar);

Sctl5s=$ctl5*(l -Stvar);

$common_header=« ;

#define _METHOD gear2

#define _STEP COINS 45 #define _STOP 50NS

#define _STATS yes

#define _CIRCUITAGE 10

#defme _SCALE Sscale

#define _RAWFMT Soutforaiat JO #define _RELTOL Sreltol

#define PI 3.14159265358979323846264338327950288419716939937511

#defme ABSTOL_TIME le-12

#defme _ALPHAC 0.78

#define _ALPHAD 3.94 JJ #define _STOPTDR 10

#defme OINTSTDR 512 foreach Sline (@cir) { if ((Sline =~ ΛA*/) && (Slinec == !)) { $title=l; print TMP Sline; print TMP«EOF; J //

// Fast Process Corner

//

// use: spectre -E cirtemp

// to activate C preprocessor 10 #defme JVDDD Svdddff

#define VDIO _VDDD

#defme _VDD Svddff

#define VCCQ _VDD

#defme VDDW Svddw 15 #define _VSSQ 0

#defme _VSSUB 0

#define _VREF 0

#defme _TEMP 0

#defme PROCESS J ORNER FAST 20 #define CORERW _VSSQ

#defme _MADSL _VSSQ

#define PDDSL _VSSQ

#define _PDTL1 Spdtlls

#defme _PDTL2 $pdtl2s 25 #define _PDTL3 Spdtl3s

#defme _CTLl Sctlls

#define _CTL2 $ctl2s

#defme _CTL3 Sctl3s

#define _CTL4 Sctl4s 30 #define _CTL5 Sctl5s

$common_header

* Sketch Mode: The following line should be deleted .GLOBAL Svddwnode VSSUB

35 * Sketch Mode Only: Please uncomment the following line for 025 IO *. GLOBAL VDD VSS VDDD VSSD VDIO Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line for 035/031 IO

* .GLOBAL VDD VSS VDDD VSSD Svddwnode VSSUB

40

#include Sdevicejib {SprocessID} #include "measurejnclude" ahdljnclude "/nfs/proton/home/s31ib/obat/ahdl/obat4.mod" .Model TLINE_S3 tline 45 EOF

} elsif (!(Sline =~ ΛA.GLOBAL/i) && !($line =~ ΛA.OPTION/i)) { Sline =~ sΛATRANSO TRAN /OBAT_FF TRAN write="Scirfile.ff.ic" /; print TMP Sline;

} JO $linec=$linec-t-l;

} close(TMP); system("mv Stempfile Scirfile.ff ');

#

JJ # — Read Mode for FF process corner

#

@cir=@cirtemp; open(TMP,">$tempfile")|| die "can not open StempfileVn"; Slinec=l ; foreach Sline (@cir) { if ((Sline =~ ΛA*/) && (Slinec = 1)) { $title=l; j print TMP Sline; print TMP«EOF12;

//

// Slow Process Corner

// 10 II use: spectre -E cirtemp

// to activate C preprocessor

#define _VDDD Svdddff

#defme VDIO VDDD

#defme _VDD Svddff is #define VCCQ _VDD

#define _VDDW Svddw

#defme _VSSQ 0

#defme _VSSUB 0

#defme VREF 0 20 #define _TEMP 0

#define PROCESS_CORNER FAST

#defme _CORERW _VCCQ

#define _MADSL _VSSQ

#defme _PDDSL _VSSQ 25 #defme _PDTL 1 Spdtl 1 s

#define _PDTL2 Spdtl2s

#defme _PDTL3 Spdtl3s

#define _CTLl $ctlls

#defme _CTL2 Sctl2s 30 #define _CTL3 $ctl3s

#defme _CTL4 $ctl4s

#defme _CTL5 Sctl5s

$common_header

35 * Sketch Mode: The following line should be deleted .GLOBAL Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line is for 025 IO *. GLOBAL VDD VSS VDDD VSSD VDIO Svddwnode VSSUB

40 * Sketch Mode Only: Please uncomment the following line is for 035/031 IO

* .GLOBAL VDD VSS VDDD VSSD Svddwnode VSSUB

#include Sdevicejib {SprocessID} #include "measurejnclude.rec" 45 ahdljnclude "/nfs/proton/home/s31ib/obat/ahdl/obat4.mod" .Model TLINE_S3 tline EOF12

} elsif (!($line =~ ΛA.GLOBAL/i) && !($line — ΛA.OPTION/i)) { Sline =~ s/VATRANSO TRAN /OBAT_REC_FF TRAN write="Scirfιle.rec.ff.ic" /; JO Sline =~ s/ PROBE 1 =/ PROBE=/; print TMP Sline;

} $linec=$linec4-l;

} JJ close(TMP); system("mv Stempfile Scirfile.rec.ff ');

#

# — Write Mode for SS process corner #

$pdtlls=$pdtll*(l -Stvar); Spdtl2s=$pdtl2*(l4-Stvar); Spdtl3 s=Spdtl3 * ( 1 +Stvar) ; $ctlls=$ctll*(l+Stvar); Sctl2s=Sctl2*(l4-Stvar); Sctl3s=$ctl3*(l4-Stvar); Sctl4s=Sctl4*(l+Stvar); Sctl5s=$ctl5*(l4-Stvar); @cir=@cirtemp; open(TMP,">$tempfιle")|| die "can not open StempfileVn";

$linec=l; foreach Sline (@cir) { if ((Sline =~ ΛA* ) && (Slinec = 1)) { $title=l; print TMP Sline; print TMP«EOF2; // // Slow Process Corner II

II use: spectre -E cirtemp

// to activate C preprocessor

#define _VDDD Svdddss

#define _VDIO Svdddss #defme _VDD Svddss

#defme _VCCQ _VDD

#define _VDDW Svddw

#define _VSSQ 0

#defme _VSSUB 0 #define _VREF 0

#define _TEMP 125

#define PROCESS_CORNER SLOW

#define _CORERW VSSQ

#define _MADSL _VSSQ #define _PDDSL _VSSQ

#defme _PDTL1 Spdtlls

#defme _PDTL2 Spdtl2s

#define _PDTL3 Spdtl3s

#define _CTLl $ctlls #defme _CTL2 Sctl2s

#defme _CTL3 Sctl3s

#define _CTL4 Sctl4s

#define _CTL5 Sctl5s

Scommon header

* Sketch Mode: The following line should be deleted .GLOBAL Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line is for 025 IO *. GLOBAL VDD VSS VDDD VSSD VDIO Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line is for 035/031 IO

* .GLOBAL VDD VSS VDDD VSSD Svddwnode VSSUB

#include Sdevice Jib {SprocessID }

#include "measurejnclude" ahdljnclude nfs/proton/home/s31ib/obat/ahdl/obat4.mod"

.Model TLINE_S3 tline

EOF2 } elsif (!($line =~ ΛA.GLOBAL/i) && ! (Sline =~- ΛA.OPTION/i)) { Sline =~ sΛATRANSO TRAN /OBAT_SS TRAN write="Scirfile.ss.ιc" /; Sline =~ s/ PROBE 1=/ PROBE=/; print TMP Sline;

I Slinec=Slinec4-l;

I close(TMP); system("mv Stempfile Scirfile. ss");

10 #

#

# — Read Mode for SS process corner

#

@cir=@cirtemp; 15 open(TMP,">$tempfile")|| die "can not open StempfileVn";

$linec=l; foreach Sline (@cir) { if ((Sline =~ ΛA*/) && (Slinec = 1)) { $title=l ; 20 print TMP Sline; print TMP«EOF22;

//

// Slow Process Corner

// 25 II use: spectre -E cirtemp

// to activate C preprocessor

#defme _VDDD Svdddss

#define _VDIO _VDDD

#define _VDD Svddss 30 #define _VCCQ _VDD

#define JVDDW Svddw

#define _VSSQ 0

#define _VSSUB 0

#defme _VREF 0 JJ #define _TEMP 125

#define PROCESS_CORNER SLOW

#defme _CORERW VCCQ

#define _MADSL JVSSQ

#define _PDDSL _VSSQ 40 #defme _PDTL 1 Spdtl 1 s

#define _PDTL2 Spdtl2s

#define _PDTL3 Spdtl3s

#defme _CTLl Sctlls

#define _CTL2 Sctl2s 45 #define _CTL3 SctBs

#define _CTL4 Sctl4s

#defme _CTL5 Sctl5s

Scommon_header

JO * Sketch Mode: The following line should be deleted .GLOBAL Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line is for 025 IO *. GLOBAL VDD VSS VDDD VSSD VDIO Svddwnode VSSUB

JJ * Sketch Mode Only: Please uncomment the following line is for 035/031 IO

* .GLOBAL VDD VSS VDDD VSSD Svddwnode VSSUB

#include Sdevice Jib {SprocessID} #include "measurejnclude.rec" ahdljnclude "/nfs/proton home/s31ib/obat/ahdl/obat4.mod" .Model TLINE_S3 tline EOF22 5 } elsif (! (Sline =~ ΛA.GLOBAL/i) && ! (Sline =~ ΛA.OPTION/i)) {

Sline =~ sΛATRANSO TRAN /OBAT_REC_SS TRAN write="Scιrfile.rec.ss.ic" /;

Sline =~ s/ PROBE 1=/ PROBE=/; print TMP Sline;

I 10 Slinec=$linec4T ;

} close(TMP); system("mv Stempfile Scirfile.rec.ss");

#

15 @cir=@cirtemp; open(TMP,">$tempfile")|| die "can not open StempfileVn";

Slinec=l ; foreach Sline (@cir) { if ((Sline =~ ΛA*/) && (Slinec = 1)) { 20 $tifle=l ; print TMP Sline; print TMP«EOF3; // // Typical Process Corner

25 II

II use: spectre -E cirtemp

// to activate C preprocessor

#defme JVDDD Svdddtt

#defme JVDIO _VDDD 30 #define _VDD Svddtt

#define _VCCQ _VDD

#define _VDDW Svddw

#define _VSSQ 0

#defme _VSSUB 0 35 #define _VREF 0

#defme _TEMP 25

#defme PROCESS_CORNER TYPICAL

#define _CORERW _VSSQ

#defme _MADSL _VSSQ 40 #defme _PDDSL _VSSQ

#define JDTL1 Spdtll

#define _PDTL2 Spdtl2

#define JDTL3 Spdtl3

#defme _CTL1 Sctll 45 #defme _CTL2 Sctl2

#define _CTL3 Sctl3

#defme _CTL4 Sctl4

#define _CTL5 Sctl5

Scommon header

JO

** Sketch Mode: The following line should be deleted .GLOBAL Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line is for 025 IO *. GLOBAL VDD VSS VDDD VSSD VDIO Svddwnode VSSUB

JJ

* Sketch Mode Only: Please uncomment the following line is for 035/031 IO

* .GLOBAL VDD VSS VDDD VSSD Svddwnode VSSUB #include Sdevice Jib {SprocessID } #include "measurejnclude" ahdljnclude "/nfs/proton/home/s31ib/obat/ahdl/obat4.mod" .Model TLINE_S3 time EOF3

} elsif (! (Sline =~ ΛA.GLOBAL/i) && ! (Sline =~ ΛA.OPTION/i)) {

Sline =~ sΛATRANSO TRAN /OBAT_TT TRAN wπte="Scirfile.tt.ιc" /;

Sline =~ s/ PROBEl=/ PROBE=/; print TMP Sline; }

Slinec=$linec4-1;

} close(TMP); systemC'mv Stempfile Scirfile.tt"); #

# — Ground Bounce Analysis

@cir=@cirtemp; open(TMP,">$tempfile")|| die "can not open StempfileVn"; $linec=l; foreach Sline (@cir) { if ((Sline =~ ΛA*/) && (Slinec = 1)) { Stitle=l; print TMP Sline; print TMP«EOF4; II

II Fast Process Corner

//

// use: spectre -E cirtemp

// to activate C preprocessor #defme _VDDD Svdddff

#defme JVDIO Svdddff

#define _VDD Svddff

#defme _VCCQ Svddff

#define _VDDW Svddw #defrne _VSSQ 0

#defme _VSSUB 0

#defme _VREF 0

#define _TEMP 25

#define JSfUMSS 5 #defme PROCESS_CORNER FAST

#defme _CORERW VSSQ

#defme _MADSL _VSSQ

#defme DDSL _VSSQ

Scommon header

* Sketch Mode: The following line should be deleted .GLOBAL Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line for 025 IO *. GLOBAL VDD VSS VDDD VSSD VDIO Svddwnode VSSUB

* Sketch Mode Only: Please uncomment the following line for 035/031 IO

* .GLOBAL VDD VSS VDDD VSSD Svddwnode VSSUB

#include Sdevicejib {SprocessID}

#include "measurejnclude" ahdljnclude "/nfs/proton home/s31ib/obat/ahdl/obat4.mod"

.Model TLINE_S3 tline

EOF4 } elsif (! (Sline =~ ΛA.GLOBAL/i) && ! (Sline =~ ΛA.OPTION/i)) { Sline =~ sΛATRANSO TRAN /OBAT_GB TRAN /; Sline =~ s/ PROBE 1=/ PROBE=/; pπnt TMP Sline;

Slinec=$linec4-1 ;

} close(TMP); system("mv Stempfile Scirfile. gb"); #

OBATsim2html

#!/usr/local/bin perl

#

# OBATsirn2html : convert the output file into a tablized html file # usage: OBATsim2html simlog Jilename html Jilename

# #

# Usage:

# OBATsim2html html _fιle #

# if($#ARGV < 0 ) { print "***Welcome to S3 OBAT simlog to html conversion Program *********\_n"; print "* Tool: OBATsim2html***************Vn"; print "Usage: Vn"; print "OBATsim2html html ile VnVn"; exit(l);

} Soutfile=@ARGV[0]; print "SoutfileVn": open(OUTFILE,">Soutfile") || die "can not open SoutfileVn"; foreach Sline (<STDIN>) { if ($line =~ /### x/) { @elements=split(" ",Sline);

$signal=$elements[ 1 ] ; $signal=~ s/:// ; $signal=~ s/_u2/_u/ ; $signal=~ s/_u3/_u/ ; $signal=~ s/_u4/_u/ ;

$signal=~ s/_u5/_u/ ; $signalmax=Ssignal."_max"; $signalmin=$signal."_min"; print "$signal=SvalueVn"; $value= $elements[4] * le9; if(Svalue > 0) { if (Slookups {Ssignal} = "") { Slookups {Ssignalmax } =$ value; Slookups {Ssignalmin } =$value; $lookups{$signal}=$value;

} else { if (Slookups {Ssignalmax} < Svalue) { Slookups {$signalmax}=S value; } if (Slookups {Ssignalmin} > Svalue) {

Slookups {Ssignalmin} =S value;

}

} }

} print OUTFILE «EOF; <ι Generated from OBATsim2html script — >

<HTML> <HEAD> <TITLE>S3 OBAT TIMING OUTPUT S</TITLE> </HEAD>

<BODY BGCOLOR="#FFFFFF">

<H2><IMG SRC="/nfs/proton home/s31ib/obat/html/icons/logo2.gif' HEIGHT=87

WIDTH=98 ALIGN=CENTER><FONT COLOR="#C00000">GX3 OBAT

TIMING OUTPUT SUMMARY</H2>

<H4>Read Path From PDx_Ux(Data)to the GUI CORE</H4>

<P>

<HR SIZE=4x/P>

</UL>

<TABLE WIDTH=500 BORDER=l CELLSPACING=0 CELLPADDING=2 WIDTH="600"

>

<TR bgcolor="#6699cc"> <TH nowrap allign=center colspan=7><FONT COLOR="#FFFFFF">SUMMARY FOR THIS

RUN</FONT></TH>

</TR>

<TR bgcolor="#6699cc">

<TH nowrapxFONT COLOR="#FFFFFF">PART NO.</FONT></TH> <TH nowrapxFONT COLOR="#FFFFFF">SIGNAL NAME</FONTx/TH>

<TH nowrapxFONT COLOR="#FFFFFF">SIGNAL NAME</FONTx/TH>

<TH nowrap colspan=2><FONT COLOR="#FFFFFF">TPD (L -> H)</FONT></TH>

<TH nowrap colspan=2><FONT COLOR="#FFFFFF">TPD (H -> L)</FONT></TH>

</TR> <TR bgcolor="#6699cc">

<TH nowrapxFONT COLOR="#FFFFFF">Destination</FONT></TH>

<TH nowrapxFONT COLOR="#FFFFFF">FROM</FONTx/TH>

<TH nowrapxFONT COLOR="#FFFFFF">TO</FONT></TH>

<TH nowrapxFONT COLOR="#FFFFFF">MIN</FONTx/TH> <TH nowrapxFONT COLOR="#FFFFFF">MAX</FONT></TH>

<TH nowrapxFONT COLOR="#FFFFFF">MIN</FONT></TH>

<TH nowrapxFONT COLOR="#FFFFFF">MAX</FONTx/TH>

</TR>

EOF Ssignalfrom="DlXX";

@others=("coreckil","corecki2"); foreach Ssignalname (@others) { $part="S3GUI CORE";

Smaxhl- 'xsdck". Ssignalname. "hl_max"; Smaxlh="xsdck".$signalname."lh_max";

Sminhl="xsdck". Ssignalname. "hl_min"; $minlh="xsdck". Ssignalname. "lh_min"; Svaluemaxhl=$lookups {Smaxhl} -7.5 ; Svalueminhl=Slookups {Sminhl} -7.5 ; Svaluemaxlh=Slookups{$maxlh}-7.5;

Svalueminlh=$lookups{$minlh}-7.5; print OUTFILE «EOF6;

<tr allign=center>

<td nowrap alligh=center>Spart</td> <td nowrap alligh=center>Ssignalfrom</td>

<td nowrap alligh=center>$signalname</td>

<td nowrap alligh=center>Svalueminlh</td>

<td nowrap alligh=center>Svaluemaxlh</td>

<td nowrap alligh=center>Svalueminhl</td> <td nowrap alligh=center>$valuemaxhl</td>

</tr>

EOF6 for($i=0; Si <64; $i++) { $signalname="PDI".$i; $signalfrom="PD".$i."_Ux";; 5 Spart="S3GUI CORE";

Smaxhl="xpdupd".$i."_uhl_max"; Smaxlh="xpdupd".$i."_ulh_max"; Sminhl="xpdupd".$i."_uhl_min"; Sminlh="xpdupd".$i."_ulh_min"; 10 $valuemaxhl=Slookups{$maxhl} ;

$valueminhl=$lookups {Sminhl } ; $valuemaxlh=Slookups {Smaxlh} ; Svalueminlh=S lookups {Sminlh} ; print OUTFILE «EOF7; 15 <tr allign=center>

<td nowrap alligh=center>$part</td> <td nowrap alligh=center>$signalfrom</td> <td nowrap alligh=center>Ssignalname</td> <td nowrap alligh=center>$valueminlh</td> 20 <td nowrap alligh=center>$valuemaxlh</td> <td nowrap alligh=center>$valueminhl</td> <td nowrap alligh=center>$valuemaxhl</td> </tr> EOF7

25

}

$now=&gettimestamp ; 30 print OUTFILE «EOF20;

</TABLE>

</UL>

<HR SIZE=4x/P>

<P>The file is converted from the source on <Bx/FONT><BxFONT JJ COLOR="#0000FF">$now

</FONTx/B></P>

</BODY>

</HTML> 40 EOF20 close (OUTFILE); sub gettimestamp {

($sec,$min,$hour,Smday,$mon,$year,$wday,Syday,$isdst) = localtime (time);

Smon=Smon4-l; 45 if (length (Smon) eq 1) {$mon="0$mon" ;} if (length (Smday) eq 1 ) {Smday="0$mday" ;} if (length (Show) eq 1 ) {$hour="0$hour" ;} return "Smon/$mday/$year $hour:$min:$sec";

} O OBATsummary

#!/usr/local/biri/perl5

#

# OBATsummary : Preparing the summary data for SDF stage s #

# Usage: OBATsummary ch name processid result.all OBAT. summary # print "Running OBATsummaryVn"; 10 Scktfile = SARGV[0]; $processιd = $ARGV[l ]; Sinput = SARGV[2]; open(INP, Sinput) || die "OBATsummary: Eπor: Can not open SinputVn"; Stphlmin = 1 ; 15 Stphlmax = 0; Stplhmin = 1 ; Stplhmax = 0; foreach Sline (<INP>) {

@element = split(" ", Sline); 20 if (Selement[l] =~ /core2m.clk.-hl/) {

#pπnt "hi Sline"; Stphltmp = Selement[4]; if (Stphltmp > Stphlmax) { Stphlmax = Stphltmp;} if (Stphltmp < Stphlmin) { Stphlmin = Stphltmp;}

25 } if ($element[l] =~ /core2m.clk.-lh/) { #print "lh Sline"; Stplhtmp = $element[4]; if (Stplhtmp > Stplhmax) { Stplhmax = Stplhtmp;} 30 if (Stplhtmp < Stplhmin) { Stplhmin = Stplhtmp;}

} }

Stplhmin = Stplhmin * le9; Stplhmax = Stplhmax * le9; 35 Stphlmin = Stphlmin * 1 e9; Stphlmax = Stphlmax * le9; close (INP); print "# Circuit File = ScktfileVn"; 40 print "# Process = SprocessidVn"; print "#Vn"; print "# TPLH TPHLVn"; print "# Min Max Min MaxVn";

Scolumn 1 ="clk_mem" ; 45 $~ = "SUMOUT"; write;

#print "Compiling number for ctr_mem...Vn"; open(INP, Sinput) || die "OBATsummary: Eπor: Can not open SinputVn"; JO Stphlmin = 1 ; Stphlmax = 0; Stplhmin = 1 ; Stplhmax = 0; foreach Sline (<INP>) { JJ @element = split(" ", Sline); if ($element[l] =~ /core2m.ma[sl]-hl/) { #print "hi Sline"; Stphltmp = $element[4]; if (Stphltmp > Stphlmax) { Stphlmax = Stphltmp;} if (Stphltmp < Stphlmin) { Stphlmin = Stphltmp;} ιf (Selement[l] =~ /core2m.ma[sl]-lh/) { #print "lh Sline"; Stplhtmp = Selement[4]; if (Stplhtmp > Stplhmax) { Stplhmax = Stplhtmp;} if (Stplhtmp < Stplhmin) { Stplhmin = Stplhtmp;} 0

Stplhmin = Stplhmin * le9; Stplhmax = Stplhmax * le9; Stphlmin = Stphlmin * le9; Stphlmax = Stphlmax * le9; 5 close (INP);

Scolumn 1 ="ctr_mem" ; write; 0 SinputVn";

5

0

J

0

5

#print "Compiling number for mem_fbclk...Vn"; open(INP, Sinput) || die "OBATsummary: Eπor: Can not open SinputVn";O Stphlmin = 1 ; Stphlmax = 0; Stplhmin = 1 ; Stplhmax = 0; foreach Sline (<INP>) { J ©element = split(" ", Sline); if (Selementfl] =~ /m.clk2core-hl:/) { #print "hi Sline"; Stphltmp = Selement[4]; if (Stphltmp > Stphlmax) { Stphlmax = Stphltmp;} if (Stphltmp < Stphlmin) { Stphlmin = Stphltmp;} if (Selement[l] =~ /m.clk2core-lh:/) { ffprint "lh Sline"; Stplhtmp = $element[4]; if (Stplhtmp > Stplhmax) { Stplhmax = Stplhtmp;} if (Stplhtmp < Stplhmin) { Stplhmin = Stplhtmp;}

Stplhmin = Stplhmin * le9; Stplhmax = Stplhmax * le9; Stphlmin = Stphlmin * le9; Stphlmax = Stphlmax * le9; close (INP);

Scolumnl ="mem_fbclk"; write; exit(O); format SUMOUT =

Scolumnl, Stplhmin, Stplhmax, Stphlmin, Stphlmax

OBATsdf_wln

# ! /usr/local/bin/perl

if ((S#ARGV 4- l) < 5 )

{ print "Usage: $0 relation Jile data_summary pinlocation Jile source_sdf wln_file destination Jir Vn"; exit(l);

10

######## interface

Schk ile = $ARGV[0]; 15 $dataJιle = $ARGV[l];

Spit Jile = SARGV[2];

$orgJιle = $ARGV[3];

SdstJir = SARGV[4];

@org _file_flds = split(Λ//, Sorg_file); 20 $orgJιle_name = SorgJιle_flds[$#orgJιle_flds];

25

######### check the destination space free space #check to see if a file has been existing $new_file = Sdst Jir . "/" . Sorg ιle_name; if( -e Snew ϊle) 30 {

#delete this file unlink($new ile) ; }

35 $df_out = 'cd Sdst Jir; /nfs/zerot/usr/ucb/df ;

@out_lns = split(Λn/, Sdf out);

@out_flds = split(Λs4-/, SoutJns[l]);

$avail_space = $out_flds[3];

$ls_out = Ts -1 Sorg Jile'; 40 @ls_out_flds = split(Λs4-/, Sls_out);

$file_size = $ls_outjlds[3]/1000;

#$free_rate = ($avail_space - Sfile_size)/$avail__space;

#print "freejrate = Sfree_rate Vn"; if( ($avail_sρace =~ Λd+ ) && (Sfile_size =~ Λd+/) && ($file_size > $avail_space ))

45 { print "Sorry, no enough space left on Sdst Jir to save the destination file Vn"; print "orginal_fϊle size = $file_size kbytes -> avaiable on Sdst ir = $avail_space Vn"; exit (l);

50 } else

{ print "Here required minum space size should be :$file_size kB Vn";

}

JJ

if(Sorg Jιle_name =~ Λw+\.sdf7) {

Sfile_mode = 0;

} else

5 {

Sfile node = 1 ; } undef(%lh_mins) ;

10 undef(%hl_mins); undef(%lh_maxs); undef(%hl_maxs) ; undef(%port_path) ; 15 undef(%sig_path); undef(%pat_sig_path) ; undef(@fullname_sigs); undef(%inst_path) ;

20

## open the data file to set up the path related data associate-aπay open(DATA, "Sdata ile") || die "Can't open the Sdata Jile: $! Vn"; while(<DATA>)

25 {

# skip the comment line if(/^ΛVs*#/)

{ next;

30 } else

{ chop($J;

(Spath, $lh_min, Slhjmax, $hl_min, $hl_max) = split(Λs+/, $ J; JJ $lh_mins {Spath} = $lh_min;

$hl_mins {Spath} = $hl_min;

$lh_maxs {Spath} = Slhjmax;

$hl_maxs {Spath} = Shl nax; }

40 } close(DATA);

## check the summary data being read in if(!defined(%lh_mins) && !defmed(%hl_mins) && !defined(%lh_maxs) &&

! defined(%hl_maxs))

45 { print "Please make sure you Sdata file has the same format as : <~zhou/Proj/OBAT/m5.data>

Vn"; exit (1);

} 50 else

{ print "Hi, finishing processing the Sdata Jile to set up the data information, next -> Vn";

}

JJ

## read in the relationship file open(CHK, "Schk Jile") || die "Can't open the Schk Jile: $! Vn"; while( <CHK>)

# skip the comment line if(/^ΛVs*#/) next; elsif /(\ +)\s+\((.+)\)\s+(\S+) )

{ 10 $path_name = $ 1 ;

Ssig_grρ = $2; $port_connect = $3;

## set up the ports path associate aπay 15 $port_path{Spath_name} = Sport_connect;

JO } else

{

@fullname_sigs = (@fullname_sigs, Ssig); $sig_path{$sig} = $path_name; JJ }

} if( defined($pat_sig) )

{ chop($pat_sig); 40 Spat_sig_path{$pat_sig} = $ρath_name;

}

}

} 45 close(CHK);

#### translate the fullname_sigs array into an associate aπay for(Si=0; Si <= S#fullname_sigs; $.++^■)

{

$fullname_sigs{$fullname_sigs[$i]} = Si;

50 }

###### read the *.plt file to set up the instance check list

JJ if( defmed(@fullname_sigs || %pat_sig_path ) )

{ open(PLT , "Spit Jile") || die "Can't open the Spit Jile: $! Vn"; print "Now got all the signal relationship define information from the Schkjϊle . Vn"; print "Starting processing the Spit Jile now ... Vn";

} else

{ print "Please maek sure your relationship file defined in the same format as:

<~zhou Proj/OBAT/m5.chk> Vn"; exit(l);

}

10 while( Sline = <PLT> ) {

# skip the comment line 15 if($line =~ /^ΛVs*#/)

{ next;

} else

20 { chop(Sline);

(Sid, Scell ype, $sig_name, $inst_name, Spack d) = split(Λs+/, Sline);

# $inst_name =~ sΛ///;

25

##### check the signal with the fullname if( defmed(%fullname_sigs) && defined($fullname_sigs{$sig_name}) )

{

$inst_path{$inst_name} = $sig_path{$sig_name}; JO delete ($fullname_sigs{$sig_name});

}

#//////////////// check the pattern_signals

JJ while( ( $pat_sig , Spath) = each (%pat_sig_path) )

{ if( $sig_name =~ /$pat_sig/ )

{

$inst_path{$inst_name} = $pat_sig_path{$pat_sig};

40 }

} }

45 } close(PLT);

## check if the instances list have been set up JO if( !defmed(%inst_path))

{ print "Sorry, some thing wrong, no instance has been set up in our check list to be modified.Vn"; print "Please check all your input files, program have to abort .... Vn"; JJ exit(l);

} else print "Starting to processing the Sorg Jile....Vn"; print "It's a huge file, please be patient Vn";

#### processing the win file #####

10 open(INPUT, Sorg Jile ) || die "Can't open the Sorg ile: $! Vn"; open(OUTPUT, ">$new ιle") || die "Can't open Snew Jile write: $! Vn"; select((select(OUTPUT), $| = 1)[0]); undef($start_chk);

15 while( <INPUT> )

{

#print ".";

20

######## processing the *.wln file if( $file_mode = 1) {

25 if ( /^ΛPATH -Vs4-(VS+)/)

{ print OUTPUT $_;

JO

$inst = $l;

# appending the '/' to the PATH name

Sinst = "/" . Sinst;

JJ ## turn off the check flag for previous instance

$start_chk = 0; undef($path); if(defmed($inst_path{ Sinst}) ) {

40

### set up the flag to check a new data $start_chk = 1 ; Spath = $inst_path {Sinst} ;

45 }

} elsif( ($start_chk = 1) && (S_ =~ /^ΛDELAYPATH/) )

{

Sline = $_; JO Sline =~ sΛn|;//g;

(Sleft, Slight) = split(/ = /, Sline); @left_flds = split(Λs4-/, Sleft); Snum = @left_flds;

JJ if( (Snum = 5) && (Sleft Jlds[2] =~ /TO/i) )

{

Sports = $left_flds[l] . $left_flds[3]; if( Sports eq Sport_path {Spath} )

{

@right Jlds = split(/ : /, Sright); @right_flds_bak = @right_flds; if( $left_flds[4] =~ /LH/i )

{

Sright_flds[0] = Slh nins {Spath} ;

Sright Jlds[2] = $lh_maxs {Spath} ;

Sright_flds[l] = ($right_flds[0] - Sright Jlds[2])/2;

10

} elsif ( Sleft_flds[4] =~ /HL/i)

{ 15 Sright_flds[0] = $hl_mins {Spath} ;

Sright_flds[2] = $hl_maxs {Spath} ; Sright_flds[l] = ($right_flds[0] ^ Sright_flds[2])/2; }

20 print OUTPUT "DELAYPATH $left_flds[ 1 ] TO Sleft_flds[3]

Sright_flds[0] : Sright Jlds[l] : $right_flds[2] ; Vn"; print "Instance : Sinst got modified -> Vn"; print "from($right_flds ak[0]:$right_flds_bak[l]:$right_flds_bak[2]) to 25 (Sright Jlds[0]:$rightjlds[l]:$rightjlds[2]) Vn";

} else

{ JO print OUTPUT $_;

} } else

{ JJ print OUTPUT S_ ;

}

} 40 else

{ print OUTPUT $_;

}

} 45 ######### processing the * .sdf file else

{ if( ($_ =~ Λ((\w+)\s+(\S+)\)/ ) && ( $1 eq 'INSTANCE') )

{ O print OUTPUT $_;

Sinst = $2;

# take away all the 'V Sinst =~ sΛV/g; JJ ## turn off the check flag for previous instance

Sstart_chk = 0; undef($path); if(defined($instj5ath{$inst}) ) #print $_; ### set up the flag to check a new data $start_chk = 1 ; Spath = Sinst_path {Sinst} ;

10 } elsif ( ($start_chk = 1) && ($_ =~ Λ(IOPATH\s+(\w+)\s+(\w+)\s+\(([\d|\.|:]+)\)\s+\(([\d|\.|:]+)\)/) )

{

Sfrom = $1; is Sto = S2;

Slh_flds = $3;

Shljlds = $4;

Sleft = $';

Sports = Sfrom . Sto; 20 if( Sports eq $port_path {Spath} )

{

@lh_flds = split(/:/, $lh_flds); @lh_flds_bak = @lh_flds; $lh_flds[0] = $lh_mins {Spath} ; 25 $lh_flds[2] = Slh_maxs {Spath} ;

$lh_flds[l] = ($lh_flds[0] 4- SlhJlds[2])/2; @hl_flds = split(/:/, $hl_flds); @hl_flds_bak = @hl_flds; $hl_fids[0] = $hl_mins {Spath}; 30 $hl_flds[2] = $hl_maxs {Spath} ;

$hl_flds[l] = ($hl_flds[0] 4- Shljlds [2])/2; print OUTPUT "Vt(IOPATH Sfrom Sto ($lhjlds[0]:$lhjlds[l]:$lhjlds[2]) ($hl_flds[0]:$hl_flds[l]:$hl_flds[2])$left"; print" Instance Sinst got modified -> Vn"; JJ print"rising_group :from ($lh_flds_bak[0]:Slh_flds_bak[l]:$lh_flds_bak[2]) to

($lh_flds[0]:$lh_flds[l]:$lh_flds[2]) Vn"; print"falling_group: from ($hl_flds_bak[0]:$hl_flds_bak[l]:$hl_flds_bak[2]) to ($hlJιds[0]:$hlJlds[l]:$hlJlds[2]) Vn";

40

} else

{ print OUTPUT S_;

45 }

} else

{ JO pπnt OUTPUT $_;

} }

} JJ close(INPUT); close(OUTPUT); OBATtran2dats

# j # Usage:

# makeOBATtran2dats psffile

#

# 9/8 Ken Li

# 0 if ($#ARGV != 0 ) { print "***Welcome to S3 OBAT TRAN->DAT Generation *********\_n ^». print " The program will take the specified tran file to generate Vn"; print " each individual dat file (compressed) for all the signals Vn"; 5 print " in the tran fileVn"; print " * Tool : makeOB ATtran2dats* * ** * ******* *\n" ; print "Usage: Vn"; print "makeOBATtran2dats psffile VnVn"; exit; 0 }

$psffile=S ARGV[S#ARGV- 1 ] ; open(GETPSF,"<$psffile") || die "can not open SpsffileVn";

@pfile=<GETPSF>; close (GETPSF); 5 chomp(@pfile);

@psfιle=@pfile;

$signalstart=0;

# Sort all the signals in the File foreach Sline (@psfile) { JO if (Sline — ΛATRACE/) {

$signalstart=l ;

} elsif ((!(Sline =~ ΛAVALUE/)) && (Ssignalstart =1)) {

@signal=split(" ", Sline); J $sig=$signal[0];

Ssig =~ s/"//g;

# if (Ssig =~ /(A|B|O|E|MA|PD|CLKIDlX)/i) { push(@valids,$sig);} push(@valids,Ssig);

} 40 elsif (Sline =~ ΛAVALUE/) {

$signalstart=0; } }

@salls=sort(@valids); 45 $previous=""; foreach Sany (@salls) { if ((Sany ne Sprevious) && (Sany ne "")) { push(@sorteds,$any); } $previous=$any;

} JO @valids=@sorteds; $numberargs=@valids; print "There are total of Snumberargs signals are going to be generated now!Vn"; print " Please Be patient! Vn";

# Create plot data file for each signal

JJ foreach Ssignal (@valids) {

Ssignal =~ tr/a-z/A-Z/ ; Soutfile=$signal."."."dat"; SoutfileZ=Soutfile.".Z"; if (( -e Soutfile) || (-e SoutfileZ)) { pπnt "File:Soutfιle exists! !Vn"} else { open(OUTFILE, ">Soutfile") || die "Can not open Ssignal.datVn": @psflist=@pfile; foreach Slist (@psflist) {

($sig,$value)=split(" ",$list); if ((Ssig — Λ"timeV"/i ) && (! (Svalue =~ Λ"/i))) { $value=$value* 1 e9; print OUTFILE "Svalue "; } if ((Ssig =~ Λ"SsignalV"/i)&& (!($ value =~ Λ"/i))){ print OUTFILE "SvalueVn"; } } close (OUTFILE); system("compress Soutfile&"); }

OBATprints

# ! /usr/local/bin perl5

# $

# ._.. s #

# Usage:

# OBATprints printername psffile #

# 2/27 Ken Li

10 # if ($#ARGV != 1 ) { print "***Welcome to S3 OBAT PLOT Generation *********\_n-,. pπnt "* Tool: OBATprints*************Vn"; is print "Usage: Vn"; print "OBATprints printername psffile VnVn"; exit;

}

#-define printer name

20 Sρrinterl="b2f3n7";

Sprinter2="hpmp" ;

$colθφrinterl="hpdpl";

$colorprinter2- 'hpdp2 " ;

$siglist=" OB ATsignals" ;

25 $psffιle=$ARGV[l];

$printer=$ARGV[0];

$pbm=0;

$tofile=0; if (Sprinter =~ /(Sprinterl |Sprinter2)/i) {

30 $color=0; print "Printer=SprinterVn";

} elsif (Sprinter=~ /pbm i) {

$pbm=l;

$tofile=l ;

JJ print "Output format=SprinterVn";

} elsif (Sprinter =~ /(Scoloφrinter 1 |Scoloφrinter2)/i) {

Scolor=l;

Sprinter=Scoloφrinter2 ; print "Printer=$printerVn";

40 } elsif (1) { die "The accepted print format is Sprinterl Sprinter2 Scoloφrinterl Scolθφrinter2 pbmVn";

} open(GETPSF,"<Spsffile") || die "can not open SpsffileVn"; 45 @pfile=<GETPSF>; close (GETPSF); chomp(@pfile); open(GETSIG,"<Ssiglist") || die "can not open SsiglistVn"; @slist=<GETSIG>; JO close(GETSIG); chomp(@slist);

# Sort all the signals in the File foreach Sline (@slist) { if (!($line — ΛA#/)) { JJ push(@comlist,$line);

(Ssig, SxO, Sxl, SyO, Syl)=split(" ",$line);

@sigs=split(Λ+/,$sig); push(@alls.@sigs); }

@salls=sort(@alls); Sprevious- "'; foreach Sany (@salls) { if ((Sany ne Sprevious) && (Sany ne "")) { push(@valids,$any); }

Sprevious=Sany;

}

# Create plot data file for each signal

10 foreach Ssignal (@valids) {

Soutfιle=$signal."."."dat"; SoutfileZ=Ssιgnal."."."dat.Z"; if ( -e Soutfile) { print "File:$outfile exists! !Vn"; 15 } elsif (-e SoutfileZ) { system(" uncompress SoutfileZ"); print "File:$outfileZ exists! !Vn";

} else { 20 open(OUTFILE, ">Soutfile") || die "Can not open Ssignal.datVn";

@psfiist=@pfile; foreach Slist (@psflist) {

($sig,Svalue)=split(" ", Slist) ; if ((Ssig =~ Λ"timeV"/i ) && (! (Svalue =~ Λ'Vi))) { 25 Svalue=$value*le9; print OUTFILE "Svalue ";

} if ((Ssig =~ Λ"$signalV'7i)&& (! (Svalue =~ Λ"/i))){ print OUTFILE "SvalueVn"; JO }

} close (OUTFILE);

} } JJ foreach Sjplot (@comlist) { if(!(Sjρρlot =~ ΛA#/)) { push (@combined,$jplot); }

} 40 Snote=""; if (!($tofile)&&(Scolor)) {

$termstr="set term postscript color"; } elsif ((Stofile)&&($pbm)) {

$termstr="set teπn pbm color small";

45 } elsif (1) {

$termstr="set term postscript";

} Snc=S#combined4-l ;

JO foreach Sgroup (@combined) {

(Sgφ,$xO,Sxl,$yO,$yl,$note)=split(" ",$group); if (SxO =~ /(a|auto)/i) { $xscale="set autoscale x"} else

{Sxscale="set xrange [$xO:$xl]"} if (SyO =~ /(a|auto)/i) { $yscale="set autoscale y"} else JJ {Syscale="set yrange [SyO:$yl]"} if (!($note = "")) {Snote =~ s/J /g;}

@glist=split(Λ4-/,$gφ);

Sname- 'plot.Snc"; open(GNUFILE, ">Sname") || die "Can not open file Sname Vn"; Scuπenttime=&gettimestamp ; print GNUFILE «EOF; Stermstr

set nolog set nopolar set title "(gjglist" w set xlabel "Time (ns)....S3 OBAT plots: Scuπenttime" Sxscale Syscale set key set ylabel "Voltage (Volts) Snote"

15 set xtics O,l EOF

Slookups{$nc}=$note.".pbm"; Slist=shift(@glist); Si=l ; 20 print GNUFILE "plot V'Slist.datV" with linespoints Si 0 ";

Si=Si4-l ; foreach Slist (@glist) { if ((Scolor)H(Spbm)) { print GNUFILE ",VVVn V'Slist.datV" with linespoints Si 0"; 25 }else { print GNUFILE ",VVVn V'Slist.datV" with linespoints Si Si";

} $i=Si4-l ;

} JO close (GNUFILE); $nc=$nc-l ;

} if (Stofile) { for ($i=l ; Si <= S#combined4-l ; $_++) { JJ $filename=Slookups{$i} ; if (-e "plot.Si") {

Scmd="gnuplot plot.Si > Sfilename" ;

} system("$cmd"); 40 unlinkC'plot.Si");

} } else { for ($i=l ; Si <= S#combined4-l; $i++) { system("gnuplot plot.Si |lpr -PSprinter ");

45 }

}

sub getinput { JO local (Sstring) = @_; local Sfile; while(l) { print "Sstrin "; JJ chop(Sfile =~<STDιN>); return Sfile; } } # sub gettimestamp {

($sec,Smin,$hour,Smday,$mon,$year,Swday,$yday,Sisdst) = localtime (time);

Smon=Smon4-l; if (length (Smon) eq 1) {$mon="0Smon" ;} if (length (Smday) eq 1 ) {$mday="OSmday" ;} if (length ($hour) eq 1 ) {$hour="0$hour" ;} return "Smon/Smday/Syear $hour:$min:$sec";

}

Claims

CLAIMSWhat is Claimed is:

1. A method for analyzing a plurality of circuit models, the method comprising the steps of: generating a first analog circuit model from a first circuit data; generating a second analog circuit model from a second circuit data; generating a behavioral model from a third circuit data; combining the first analog circuit model with the second analog circuit model to generate a third analog circuit model; combining the third analog circuit model with a behavioral model to generate a hybrid circuit model; applying a first input signal to the hybrid circuit model to generate a first output signal.

2. The method of claim 1 further comprising the step of: dividing the first output signal into a second output signal and a third output signal.

3. The method of claim 2 further comprising the step of: transforming the second output signal into timing effect data relating to the hybrid circuit model.

4. The method of claim 2 further comprising the step of: transforming the third output signal into noise effect data relating to the hybrid circuit model.

5. The method of claim 1 wherein generating the first analog circuit model further comprises the additional steps of: generating a plurality of fourth analog circuit models from the first circuit data; and combining the plurality of fourth analog circuit models into the first analog circuit model.

6. The method of claim 1 wherein the second circuit data comprises a package parameter table and a pin location table.

7. The method of claim 1 wherein generating the second analog circuit model comprises the additional step of: replacing an analog circuit component of the second analog circuit model with a first identifier. j

8. The method of claim 1 wherein the generating of the behavioral circuit model comprises the additional step of: converting the third analog circuit model having a first format from the first format to a second format.

9. The method of claim 1 wherein the third circuit data comprises electrical and0 functional circuit information.

10. The method of claim 1 wherein the behavioral circuit model is an analog high- level description language model.

11. A computer based system for analyzing timing and noise effects in a hybrid circuit model based upon predefined electrical parameters, the system comprising: 5 a storage device containing component information and predefined electrical parameters; and a hybrid circuit model simulation system, adapted to receive the component information and the predefined electrical parameters, coupled to the storage device, for generating the timing effects and the noise effects of the hybrid circuit. 0

12. A hybrid circuit model simulator comprising: a first modeler module for generating a first analog circuit model from a first circuit data; a second modeler module for generating a second analog circuit model from a second circuit data; 5 a third modeler module for generating a behavioral model from a third circuit data; an integrator preprocessor module, coupled to the first modeler module and the second modeler module, for combining the first analog circuit model with the second analog circuit model to generate a third analog circuit model; an integrator module, coupled to the integrator preprocessor module, for combining the third analog circuit model with a behavioral model to generate a hybrid circuit model; and a simulator module, coupled to the integrator module, for applying a first input signal to the hybrid circuit model to generate a first output signal. j

13. The simulator of claim 12 wherein the first output signal is timing effect data relating to the hybrid circuit model.

14. The simulator of claim 12 wherein the first output signal is noise effect data relating to the hybrid circuit model.

15. The simulator of claim 12 wherein the first modeler includes: 0 an extractor module for generating a plurality of fourth analog circuit models from the first circuit data; and a joiner module, coupled to the extractor module, for combimng the plurality of fourth analog circuit models into the first analog circuit model.

16. The simulator of claim 12 wherein the second circuit data comprises a package5 parameter table and a pin location table.

17. The simulator of claim 12 wherein the third modeler module includes: a translator, coupled to the integrator module, for converting the third analog circuit model having a first format from the first format to a second format.

18. The simulator of claim 12 wherein the third circuit data comprises electrical0 and functional circuit information.

19. The simulator of claim 12 wherein the behavioral circuit model is an analog high-level description language model.

20. The simulator of claim 12 wherein the second modeler module includes: a schematic manager module for graphically editing the second analog circuit5 model.