WO1999067895A1

WO1999067895A1 - Method and apparatus for storing and accessing different chip sequences

Info

Publication number: WO1999067895A1
Application number: PCT/SE1999/001078
Authority: WO
Inventors: Håkan ERIKSSON; Martin Jonson
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 1998-06-23
Filing date: 1999-06-16
Publication date: 1999-12-29
Also published as: HK1039225A1; KR20010071566A; NO20006509L; CN1307756A; AR018927A1; RU2001101930A; CA2335742A1; AU4941099A; JP2002519887A; EP1090465A1; EE200000777A; NO20006509D0; ID27301A; IL139840A0; BR9911434A

Abstract

A chip sequence generator (160) stores sequences in a memory (190) having a memory address system. A chip sequence reader uses a memory read address generator (150) to access different phases of the sequences. The reader delivers the different phases to correlators or circuits in a spread spectrum receiver. The memory read address generator generates addresses dependant on a finger select value and a counter value. Each finger select value corresponds to a particular phase of a sequence. The counter value corresponds to a position in time. In sleep mode, the counter value is changed to correspond to the number of clock cycles in a sleep period. The receiver conserves power during sleep and accesses the correct phase of the sequence at wake up. The memory can also store paging sequences. The chip sequence generator generates new sequences as needed and writes them to addresses used to store sequences no longer needed.

Description

METHOD AND APPARATUS FOR STORING AND ACCESSING DIFFERENT CHIP SEQUENCES

BACKGROUND The invention relates to receiving spread spectrum radio signals, such as digitally modulated signals in a Code Division Multiple Access (CDMA) mobile radio telephone system, and more particularly, to using a random access memory to store and access different chip sequences and different phases of the different chip sequences.

In a CDMA communication system, informational signals are impressed upon high-bit-rate spreading codes. A spreading code is a binary sequence of +1 and -1 values that are usually referred to as chips. Spreading codes are usually generated by a pseudo- noise (PN) process that appears random, but that can be replicated by an authorized receiver. The informational signal and the high-bit-rate spreading codes are combined by multiplying the two bit streams together. This combination of the higher-bit-rate signal with the lower-bit-rate data stream is called "coding" or "spreading" the informational data stream. Each informational data stream, or channel, is allocated a unique sequence, or "spreading code."

Coded informational signals are used to modulate a radio-frequency (RF) carrier by, for example, quadrature phase shift keying (QPSK), and are jointly received as a composite signal at a receiver. The coded signals and noise related signals overlap in both frequency and time. A receiver can correlate the composite signal with one or more spreading codes to isolate and decode a corresponding information signal. It will be appreciated by those skilled in the art that the composite signal is actually correlated with a complex conjugated version of the one or more spreading codes. One CDMA technique, called "traditional CDMA with direct spreading," uses a spreading code (a signature sequence) to represent one bit of information. Receiving the transmitted code or its complement (the opposite of each bit of the code sequence) indicates whether the information bit is a "-1" or a "+1." The entire N-chip sequence, < or its complement, is referred to as a transmitted symbol. The receiver generates a compl ex conjugated replica of the signature sequence with its own sequence generator and correlates the received signal with the replica to produce a normalized value ranging from -1 to +1. When a large positive correlation results, a "-1" is detected; when a large negative correlation results, a "+1" is detected. FIG. 1 illustrates an example of a CDMA transmitter and a CDMA receiver. A transmitter 10 receives input user data from multiple users. In a traditional CDMA system, each symbol of input user data 20 is multiplied by a signature sequence 22. There is a unique signature sequence for each input user. The signature sequence can be, for example, 256 chips long or selected from one of 64 possible codes. Input user data is then spread by a long code 24. According to some CDMA standards, the long code 24 is 2¹⁵ chips long. While the signature sequences eliminate multiple access interference among users in the same cell, the long code is used to eliminate multiple access interference among the transmitters. For example, each base station in a group of base stations can use a different long code. The spread signal for input user data 22 is then summed with the other spread signals to form composite signal 26. Composite signal 26 is used to modulate a radio frequency carrier 28 which is transmitted by transmitting antenna 30.

At the receiver 40, a receiving antenna 42 receives signal 32. Receiver 40 demodulates signal 32 using carrier signal 44 to provide composite signal 46. Composite signal 46 is multiplied by a synchronized long code 48. Receiver 40 has at least one chip sequence generator (not shown). Long code 48 is a locally generated complex conjugated replica of long code 24.

The despread signal 50 is then multiplied by a synchronized signature sequence 50. Signature sequence 52 is a locally generated complex conjugated replica of signature sequence 22 (or one of the other N signature sequences used by transmitter 10). The multiplication by signature sequence 52 eliminates the interference due to transmission to the other users. The receiver 10 integrates over the length of each symbol to determine whether the symbol is a "+1 " or a "-1." It will be evident to those skilled in the art that receiver 40 can not reconstruct input user data 20 unless it can (1) determine long code 24 and synchronize a locally generated complex conjugated replica of long code 24 with the received signal 32, and (2) determine signature sequence 22 and synchronize a locally generated complex conjugated replica of signature sequence 22 with the despread signal 50.

U.S. Patent 5,457,713 discloses a soft-ware assisted method for maintaining spread spectrum chip sequence synchronization. According to U.S. Patent 5,457,713, appropriate chip code generators can be fashioned from an exclusive OR gate tapped shift register with feedback, a random access memory/read only memory (RAM/ROM) look- up table wherein the appropriate chip code pattern is stored, or a serial shift register wherein the appropriate chip code pattern is stored. U.S. Patent 5,457,713 achieves chip sequence synchronization by using a ROM look-up table that has several inputs designed to alter the time/phase offset of the repetitive chip code output. An advance input time advances the chip code position; and, a delay input time delays the chip code position. While a RAM/ROM look-up table is useful for storing a list of relatively short signature sequences, it is not feasible to store a list of long codes that are each 2¹⁵ bits in length. A look-up table does not allow for new chip sequences or for accessing different phases of the new chip sequences. A list of all possible long codes (or even portions of all possible long codes) would be too large to fit on a single chip. It is for this reason that most receivers use a bank of sequential logic circuits, such as feedback registers, to generate the necessary long codes.

In many radio communication systems, the received signal includes two components, an I (in-phase) component and a Q (quadrature) component. The transmitter codes the I components and Q components separately. In a typical receiver using digital signal processing, the received I and Q component signals are sampled every T_c seconds, where T_c is the duration of a chip, and stored as streams of I and Q samples. When the signal has two components, usually one chip sequence generator generates a first chip sequence for the I components, and a second chip sequence generator generates a second chip sequence for the Q components. In mobile communication systems, signals transmitted between base and mobile stations typically suffer from echo distortion or time dispersion (multipath delay). Multipath delay is caused by, for example, signal reflections from large buildings or nearby mountain ranges. The obstructions cause the signal to proceed to the receiver along not one, but many paths. The receiver receives a composite signal of multiple versions of the transmitted signal that have propagated along different paths (referred to as "rays"). The rays have different and randomly varying delays and amplitudes.

Each distinguishable "ray" has a certain relative time of arrival, kT_c seconds, and spans n of the I and Q chip samples, where n is the number of chips in the spreading code. Each signal image is a n chip sequence. As a result of multipath time dispersion, the correlator outputs several smaller spikes rather than one large spike. Each ray that is received after the spreading code period (that is, if the time delay caused by a reflection exceeds one spreading code period) appears as an uncorrelated interfering signal that reduces the total capacity of the communication system. FIG. 2 illustrates an example of a multipath profile of a received composite signal.

The ray that propagates along the shortest path arrives at a time T₀ with an amplitude A_Q, and rays propagating along longer paths arrive at time T,, T₂, T₃ with amplitudes A A₂, A₃, respectively. To optimally detect the transmitted signal, the spikes received must be combined in an appropriate way. This is usually done by a RAKE receiver, which is so named because it "rakes" all the multipath contributions together. A RAKE receiver uses a form of diversity combining to collect the signal energy from the various received signal paths (or rays). Diversity produces redundant communication channels so that when some channels fade, communication is still possible over non-fading channels. A CDMA RAKE receiver combats fading by detecting the echo signals individually using a correlation method and adding them coherently.

FIG. 3a illustrates a RAKE receiver wherein delayed versions of a received signal are processed in parallel. A radio frequency (RF) receiver 310 demodulates an input signal and quantizes the demodulated signal to provide digital samples 312. Digital samples 312 correspond to a composite signal. In some systems, the composite signal has in-phase and quadrature components that are divided into streams of I and Q samples.

The RAKE receiver comprises digital data receivers 320, 322, 330, and 332. When digital data receivers are used as part of a RAKE receiver, they are sometimes referred to as fingers. The digital samples 312 corresponding to time T₃ are delivered to digital data receiver 332. In digital data receiver 332, the digital samples 312 are correlated with one or more chip sequences. If, for example, digital samples 312 are complex digital samples, the stream of I samples are correlated with a first chip sequence and the stream of Q samples are correlated with a second chip sequence. The RAKE reciever has delay taps 315 that correspond to the delays between each of the rays. As a result, a delayed version of the digital samples 312 corresponding to time T₂ are delivered to digital data receiver 330; a delayed version of the digital samples 312 corresponding to time T, are delivered to digital data receiver 322; and a delayed version of the digital samples 312 corresponding to time T₀ are delivered to digital data receiver 320. Alternatively, the digital samples can be collected in a buffer and different sets of the digital samples can be delivered to the digital data receivers simultaneously. The total time delay of the delay line (or the size of the buffer) limits the amount of arrival time delay that can be raked together.

In each of the digital data receivers 320, 322, and 330, the input samples are correlated with the same one or more chip sequences as in digital data receiver 332. The finger outputs that have significant energy are appropriately weighted and combined to maximize the received signal-to-noise- and-interference ratio. The finger outputs are each multiplied by a multiplier 352, and then added together by an accumulator 354. The output of the accumulator 354 is decoded by a threshold device 356. FIG. 3b illustrates a RAKE receiver wherein a received signal is processed in parallel with delayed versions of one or more chip sequences. Digital samples 312 are processed serially instead of collecting delayed versions of the digital samples 312 from a delay tap line or a buffer. In digital data receiver 332, the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T₃. In digital data receiver 330, the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T₂. In digital data receiver 322, the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T,. And, in digital data receiver 320, the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T₀. The finger outputs that have significant energy are appropriately weighted and combined to maximize the received signal-to-noise-and-interference ratio. The chip sequences are usually provided by a set (bank) of chip sequence generators. Because each ray is correlated with a different phase of the one or more chip sequences, at least one chip sequence generator is required for each ray.

For a multipath profile such as that shown in FIG. 2, the RAKE receiver would require four chip sequence generators, one for each phase of the chip sequence. If there is a stream of I samples and a stream of Q samples for each ray, the RAKE receiver would require eight chip sequence generators.

As a mobile station moves away from a source, the quality of the received signal usually decreases. When the quality of the received signal decreases to the point that another source can provide a better signal or the system determines that it can decrease the amount of interference experienced by other mobile stations in the system, the system should perform a handoff. The base station or base stations can perform what is referred to as a soft handoff. A soft handoff occurs when the original source and the new source transmit substantially the same information to the mobile station at the same time until the original source terminates its transmission. If the mobile station is using a RAKE receiver, the signal from the new source appears as additional multipaths, and the RAKE receiver can process the two signals as a single signal. In a soft handoff situation, the receiver allots some of the digital data receivers (first group) to the first source and its multipath rays and some of the digital data receivers (second group) to the second source and its multipath rays. The first group of receivers uses a first chip sequence and the second group of receivers uses a second chip sequence. If the received signal is processed in parallel with delayed versions of the chip sequences, the first group uses different phases of the first chip sequence, and the second group uses different phases of the second chip sequence. One of the problems with using multiple chip sequence generators to provide different chip sequences (and different phases of the different chip sequences) is that many portable devices are designed to enter sleep mode when not in use. For example, a mobile station roaming in a cellular system can reduce power consumption by spending the majority of its time asleep. The mobile station can obtain (from the cellular system) information regarding the chip sequence that is used for pages (the paging sequence) and information regarding when in time to listen for the paging sequence (the assigned paging frame). The mobile station can awaken before the assigned paging frame in order to listen for the paging sequence, and if a page is not received, the mobile station can return to sleep mode. While in sleep mode, the mobile station can power down most of its circuits. However, it is usually still necessary to advance the chip sequence generators so that the chip sequence generators provide the same phase at the end of the sleep period as at the beginning of the sleep period. As the number of chip sequence generators increases, the benefits of sleep mode decrease.

Co-assigned and co-pending application entitled "PSEUDORANDOM NUMBER SEQUENCE GENERATION IN RADIOCOMMUNICATION SYSTEMS" for

Bottomley et al. (Attorney Docket No. 027575-084) addresses this problem and discloses that each of the local code generators can be advanced a certain number of clock cycles to accommodate for the inactive clock cycles during sleep mode. However, the advancing of multiple sequence generators is still complicated and costly. The full benefits of sleep mode are better realized by eliminating the need for multiple chip sequence generators.

It has been recognized generally that one code generator and suitable components, such as a serial shift register, can be used to replace multiple code generators. If the chip sequence is relatively short, it is possible to use one code generator and a serial shift register to advance or delay the code. However, these and other attempts to replace multiple code generators are not well suited for receiving increasingly longer chip sequences or processing signals serially (as opposed to initially collecting them in a memory and providing them in parallel to the correlators). In addition, these attempts to replace multiple code generators with a single code generator do not provide for searching for new multipath rays. Searching for new multipath rays often involves retarding (or backing up) the chip sequence. Retarding the chip sequence is the same as advancing the chip sequence an amount less than a full period. However, advancing the chip sequence at an increased frequency is complicated and costly. Moreover, these attempts to replace a multiple code generators with a single code generator are not well suited for soft handoff situations and/or maintaining a proper state during sleep mode. There is a need for a reliable and efficient system for replacing multiple code generators with a single code generator and for providing different phases of a spreading code to different correlators or circuits used in a spread spectrum receiver.

SUMMARY

These and other drawbacks, problems, and limitations of conventional receivers are overcome by using a chip sequence generator, a memory, and a chip sequence reader. The chip sequence generator and the chip sequence reader can be implemented in hardware or software as part of or separate from a controller. The chip sequence reader can access different phases of different sequences and provide the same to various correlators or circuits used in a receiver.

According to one aspect of the invention, the chip sequence generator writes different chip sequences to a memory having a memory address system, and the chip sequence reader uses a memory read address generator to access the different phases of the different sequences. The memory read address generator can use a finger select value and/or a counter value to generate the memory read address(es).

According to another aspect of the invention, the memory read address generator uses a finger select value that corresponds to a particular chip sequence and a particular phase of the chip sequence. In, for example, a soft handoff situation, a first finger is designated a first finger select value corresponding to a first phase of a first sequence, a second finger is designated a second finger select value corresponding to a second phase of the first sequence, and a third finger is designated a third finger select value corresponding to a first phase of a second sequence. Stored sequences can also be used to search for stronger signals or rays

According to another aspect of the invention, the counter value corresponds to a number of clock cycles. In sleep mode situations, the counter value is advanced a number of clock cycles equal to a number of clock cycles in a sleep period. As a result, the receiver can conserve power during sleep mode and still access the correct phase of the correct sequence at the end of the sleep period.

According to another aspect of the invention, the chip sequence generator can generate new chip sequences as needed and write the new chip sequences to addresses that are used to store chip sequences that are no longer needed. As a result, it is not necessary to store extraneous chip sequences that use up valuable chip space. According to another aspect of the invention, the memory is used to store a paging sequence that is used by a cellular system to page a mobile station. The mobile station can access the paging sequence during a period of time preceding an assigned paging frame.

An advantage of the invention is that a single chip sequence generator can replace multiple chip sequence generators. Another advantage is that once a chip sequence is stored in the memory, the code generator can be powered down until needed. As a result, power consumption is reduced. Moreover, different phases of different sequences are readily available whether the code generator is active or not.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing, and other objects, features, and advantages of the invention will be more readily understood upon reading the following detailed description in conjunction with the drawings in which:

FIG. 1 illustrates an example of a CDMA transmitter and a CDMA receiver; FIG. 2 illustrates an example of a multipath profile of a received composite signal;

FIGS. 3a and 3b illustrate different RAKE receivers;

FIG. 4 illustrates an example of a chip sequence generator; FIG. 5 illustrates a spread spectrum receiver and an apparatus for accessing different chip sequences and different phases of the different chip sequences;

FIG. 6 illustrates in more detail an apparatus for accessing different chip sequences and different phases of the different chip sequences;

FIG. 7 illustrates an apparatus for generating a memory read address; and, FIG. 8 is a flow chart diagram for storing a locally generated chip sequence in a memory.

DETAILED DESCRIPTION

In the following description, specific details are set forth, such as particular circuits, circuit components, techniques, etc., in order to provide a thorough understanding of the invention. For example, the description refers to exemplary modulation and transmitting techniques. However, it will be apparent to those skilled in the art that the present invention can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, and circuits are omitted so as not to obscure the description of the present invention with unnecessary detail.

As discussed above, FIG. 1 illustrates an example of a CDMA transmitter and a CDMA receiver. FIG. 2 illustrates an example of a multipath profile of a received composite signal. FIGS. 3a and 3b illustrate different RAKE receivers. FIG. 4 illustrates an example of a chip sequence generator. A pseudo-noise (PN) or pseudorandom sequence is one type of chip sequence that is frequently used in CDMA systems. A PN sequence is a binary sequence with an autocorrelation that resembles, over a period, the autocorrelation of a random binary sequence. Its autocorrelation also roughly resembles the autocorrelation of band-limited white noise. Although it is deterministic, a pseudonoise sequence has many characteristics that are similar to those of random binary sequences, such as having a nearly equal number of Os and Is, very low correlation between shifted versions of the sequence, very low crosscorrelation between any two sequences, etc. A PN sequence is usually generated using sequential logic circuits such as a feedback shift register. Feedback shift register 70 has memory devices 71, 72, 73, . . . , m and a feedback logic circuit 78. Binary sequences are shifted through the shift registers in response to clock pulses, and the output of the various stages are logically combined and fed back as the input to the first stage 71. When the feedback logic circuit 78 consists of exclusive-OR gates the shift register is usually referred to as a linear PN sequence generator.

The initial contents of the memory stages 71, 72, 73, . . . , m and the feedback logic circuit 78 determine the successive contents of the memory. If a linear shift register ever reaches a zero state, it remains in a zero state so that the output would subsequently be all 0's. Since there are exactly 2^m-l nonzero states for a m-stage feedback shift register, the period of a PN sequence produced by a linear m-stage shift register cannot exceed 2^m-l symbols. A sequence of period 2^m-l generated by a linear feedback register is called a maximal length (ML) sequence. A Gold code is another type of chip sequence that is frequently used in CDMA systems. A Gold code can be created by linearly combining two PN sequences.

FIG. 5 illustrates a spread spectrum receiver and an apparatus for accessing different chip sequences and different phases of the different chip sequences. Chip sequence generator 160 generates a chip sequence 164 that is stored in a memory 190. A controller 150 is connected to the memory 190 by a bus or one or more suitable connections. Chip sequence generator 160 can use memory stages and a feedback logic circuit as shown in FIG. 4 to generate the chip sequence 164. The controller 150 can control the chip sequence generator 160, and ultimately the chip sequence 164, by controlling the initial contents of the memory stages. The chip sequence generator 160 can generate many different chip sequences. Memory 190 is any device that is suitable for storing chip sequences. One example is a random access memory device. Memory 190 can use a memory address system (an address counter) so that there is an address for each chip stored in the memory 190. The memory 190 can also be arranged so that each address corresponds to a particular set of chips. Each set of chips corresponds to a particular phase of a particular sequence. As a result, the controller 150 can access different phases of the different chip sequences by accessing different addresses in memory 190. When writing to the memory 190, the controller 150 can also designate an address (or a set of addresses). The controller 150 can generate new chip sequences using chip sequence generator 160 and write the new chip sequences to address 166.

Memory 190 can use multiple outputs (or a single output) for delivering multiple phases of the chip sequence to multiple circuits in a spread spectrum receiver. These circuits can include circuits for correlating, adding, and/or multiplying two sequences together. In an exemplary embodiment, memory 190 has a bus for delivering different phases of the different chip sequence to fingers of a RAKE receiver and a searcher receiver.

In a CDMA mobile radio telephone system, antenna 300 receives a spread spectrum signal. A radio frequency (RF) receiver 310 amplifies and filters the received signal. The receiver 310 demodulates the received signal and quantizes the demodulated signal to provide digital samples 312. Digital samples 312 correspond to a composite signal. In some systems, the composite signal has in-phase and quadrature components that are divided into streams of complex digital samples I and Q .

The digital samples 312 are delivered to digital data receivers 320, 322, 330, and 332 and to searcher receiver 340. A delayed tap line can be used to deliver delayed versions of the digital samples to the digital data received and the searcher receiver. The digital samples are processed by digital receivers 320, 322, 330, and 332 using chip sequences stored in memory 190. Memory 190 has a bus or one or more suitable connections for providing chip sequences to the receiver. For example, controller 150 uses a first memory read address 181a to provide a first set of chips 201a to digital data receiver 332; a second memory read address 181b to provide a second set of chips 201b to digital data receiver 330; a third memory read address 181c to provide a third set of chips 201c to digital data receiver 322; a fourth memory read address 18 Id to provide a fourth set of chips 20 Id to digital data receiver 320; and, a fifth memory read address 181e to provide a fifth set of chips 20 le to searcher receiver 340. The first set of chips 201a is a first phase of a first chip sequence, the second set of chips 201b is a second phase of the first chip sequence, the third set of chips 201c is a third phase of the first chip sequence, the fourth set of chips 20 Id is a fourth phase of the first chip sequence, and the fifth set of chips 20 le is a fifth phase of the first chip sequence. Or alternatively, one or more of the set of chips can be phases of a second or third chip sequence.

In addition, controller 150 can provide control signals to digital data receivers 320, 322, 330, and 332. The outputs of receivers 320, 322, 330, and 332 are provided to diversity combiner and decoder 350. Controller 150 can assist combiner 350 in adjusting the timing of the outputs and in finding the weighted sum of the realigned outputs. Methods for diversity combining and decoding are well known in the art and will vary from system to system.

Searcher receiver 340 can scan different phases of a currently used sequence to look for other multipath signals (rays). Controller 150 can instruct searcher receiver 340 to search certain phases. When the controller 150 determines that searcher receiver 340 has found a stronger ray, the controller 150 can update digital data receivers 320, 322, 330, or 332 by instructing them to use a different phase of the current sequence. The searcher receiver 340 can also search different phases of an inactive chip sequence. If the searcher receiver determines that the inactive chip sequence provides a stronger signal than the current chip sequence, one or more of the digital data receivers can be updated to use different phases of the inactive sequence. New chip sequences can be generated by the chip sequence generator 160 or an additional chip sequence generator (not shown). If additional chip sequences are required, these additional chip sequences are also stored in memory 190 or an additional memory (not shown). As discussed more fully below, the disclosed structure is extremely useful in soft handoff and/or sleep mode situations.

FIG. 6 illustrates in more detail an apparatus for accessing different chip sequences and different phases of the different chip sequences. Memory 190 is any device that is suitable for storing chip sequences. If memory 190 has a memory address system that is divided into rows and columns, each row can be used to store a different sequence, a portion of a sequence, or a single chip.

It will be appreciated by those skilled in the art that if a long code is on the order of 2¹⁵ chips that in some applications it is not feasible to store all 2¹⁵ chips. It may be advantageous to store only a portion, for example, 50,000 chips of the long code. The length of each portion may depend on the total number of different sequences stored in the memory. As the number of sequences is increased, the length of each portion can be decreased accordingly.

A controller 150 has an input 360 for conditions or instructions from other circuits. Controller 150 delivers instructions to a chip sequence generator 160. Chip sequence generator 160 is capable of generating different chip sequences. The chip sequence generator 160 can write the different chip sequences to the memory 190. A serial-to-parallel converter 162 can be used to allot (or configure) the sequence 164 to rows in the memory 190. For example, the serial-to-parallel converter 162 can control how many chips are written to each row. The controller 150 generates a memory write address 166. The memory write address 166 is used to store the chip sequence 164.

The controller 150 also generates a memory read address 181. The memory read address 181 is used to access a particular phase of a particular chip sequence. The particular phase of a particular chip sequence is delivered from the memory 190 using a suitable connection 201. The desired memory read address 181 will depend on conditions or instructions from other circuits via input 360. If, for example, the invention is used in a spread spectrum receiver, the memory read address 181 will depend on the chip sequence, the phase of the chip sequence, and when in time the chip sequence is needed. In a RAKE receiver, a combiner combines the output from different fingers that are receiving the same physical channel. The fingers can be configured to receive signals that use different chip sequences; signals that use the same chip sequence, but with a different phase shift; and/or signals that use the same chip sequence and the same phase shift, but that are multi-path delays. The controller 150 can keep track of the fingers and which chip sequence and which phase each finger is using.

FIG. 7 illustrates an apparatus for generating a memory read address. Memory read address generator 151 can be implemented in hardware or software as part of or separate from controller 150. Memory read address generator 151 has an input for a finger select value 170 and a counter value 174. The finger select value 170 corresponds to a chip sequence value 171 and a phase offset value 172. The memory read address 181 depends on the combination 173 of the chip sequence value 171 and the phase offset 172.

The read address generator 151 can use a clock cycle to keep track of time and can advance the counter value 174 with each clock cycle. If a group of fingers are configured to receive multipaths of the same signal, the group of fingers should use the same counter value. The memory read address 181 depends on the combination 175 of the combination 173 and the counter value 174. The counter value 174 is useful to ensure that a circuit continues to receive the correct phase of the correct sequence. Referring back to FIGS. 5 and 6, the read address 181 is used to access a particular phase of a particular chip sequence. The particular phase of the particular chip sequence is then delivered via an output 201 to a particular finger or searcher. The memory 190 can use individual connections (as shown in FIG. 4) or a common bus or output for delivering codes to the fingers or searcher. The memory 190 is particularly useful for searching for stronger rays or signals. The controller 150 can provide a series of finger select values, thereby accessing different sequences and/or phases, and provide the different sequences and/or phases to the searcher receiver.

When a receiver receives from a cellular system a list of sequences to listen for or to search. The controller 150 can instruct the sequence generator 160 to generate the new sequences and to write them to the memory 190. Moreover, the controller 150 can instruct the sequence generator 160 to write to addresses that are used to store chip sequences that are no longer needed.

Memory 190 is also particularly useful for soft handoff situations. When the controller 150 determines that a new sequence provides a better signal, the controller 150 can configure one or more of the fingers to receive the old chip signal and multipath rays using an old chip sequence, and configure the remaining fingers to receive the new signal and multipath rays using a new chip sequence. The controller 150 can configure a fmger select value for each fmger so that the first group of fingers uses a different phase of the old chip sequence, and each fmger in the second group of fingers uses a different phase of the new chip sequence.

Finally, memory 190 is particularly useful for sleep mode situations. As discussed above, the full benefits of sleep mode are not realized if there are many chip sequence generators, and the sequence generators are active during sleep mode. This problem is overcome by using a single generator, storing different sequences in a memory, and advancing (or changing) a counter value before or during a sleep period. In a sleep mode situation, the controller 150 can advance the counter value 174 a number of clock cycles equal to the number of clock cycles that the receiver will be asleep so that when the receiver wakes up, each fmger is using the correct phase of the correct sequence. FIG. 8 is a flow chart diagram for storing a locally generated chip sequence in a random access memory. In step 410, a control processor can reset a local code generator. For example, the control processor can reset the initial contents of memory stages of a feedback shift register. In step 420, the code generator generates stage i of a chip sequence that is determined by the initial contents of the code generator the feedback logic circuit.

In step 430, stage i of the chip sequence is stored in a memory. Once stage i of the chip sequence is stored, different phases of the chip sequence are readily available.

In step 440, the control processor can check to see if additional stages of the chip sequence are needed. If additional stages are needed, the code generator can generate the next stage of the chip sequence. Once the chip sequence is fully loaded, the code generator can be powered down. As discussed above, a linear feedback register generates a sequence that has a maximum period of 2^m-l, where m is the number of stages.

In step 450, the control processor can check to see if an additional chip sequence is needed. If so, the control processor can reset the code generator and generate additional chip sequences. As discussed above, the size of the memory can be decreased by not storing extra chip sequences and by loading chip sequences as needed. While the memory can be used to store more than one sequence, it is not necessary to store sequences that are no longer necessary for receiving signals. While the description above makes frequent reference to providing chip sequences to the fingers of a RAKE receiver or a searcher receiver, memory 190 is also useful for storing chip sequences used for specific or other purposes. For example, memory 190 can be used to store one or more chip sequences used exclusively for listening for pages. In a sleep mode situation, the cellular system can assign a paging frame and one or more paging sequences to each mobile station. Each mobile station can store the paging sequences in memory 190 so that the paging sequences are readily available. When the mobile station wakes up before an assigned paging frame, the mobile station can obtain the paging sequence from the memory 190.

The preceding description of the preferred embodiments are provided to enable any person skilled in the art to make and use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles described herein may be applied without departing from the scope and spirit of the present invention. For example, the disclosed methods and structures can be used not only in base stations or consumer products such as mobile, cordless, and satellite phones, but also in other types of audio and/or video equipment. Thus, the present invention is not limited to the disclosed embodiments, but is to be accorded the widest scope consistent with the claims below.

Claims

WHAT IS CLAIMED IS:

1. An apparatus for accessing different chip sequences and different phases of the different chip sequences, the apparatus comprising: a memory suitable for storing chip sequences; a chip sequence generator configured to write different chip sequences to the memory; and, a chip sequence reader configured to read different phases of the different chip sequences from the memory.

2. An apparatus as described in claim 1, the chip sequence reader including a memory read address generator.

3. An apparatus as described in claim 2, the memory read address generator configured to generate a memory read address that is dependent on a fmger select value.

4. An apparatus as described in claim 3, the fmger select value corresponding to a chip sequence and a phase offset.

5. An apparatus as described in claim 2, the memory read address generator configured to generate a memory address that is dependent on a counter value.

6. An apparatus as described in claim 5, the memory read address generator configured to generate a memory read address that is dependent on a finger select value.

7. An apparatus as described in claim 6, the fmger select value corresponding to a chip sequence and a phase offset.

8. An apparatus as described in claim 1, the chip sequence reader configured to deliver a first phase of a first chip sequence to a first fmger of a RAKE receiver.

9. An apparatus as described in claim 8, the chip sequence reader using a fmger select value to access a memory address in the memory that corresponds to the first phase of the first chip sequence.

10. An apparatus as described in claim 8, the chip sequence reader configured to deliver a second phase of the first chip sequence to a second fmger of the RAKE receiver.

11. An apparatus as described in claim 10, the chip sequence reader using a first fmger select value to access a memory address in the memory that corresponds to a first phase of a first chip sequence and a second fmger select value to access a memory address in the memory that corresponds to a second phase of the first chip sequence.

12. An apparatus as described in claim 10, the chip sequence reader configured to deliver a first phase of a second chip sequence to a third finger of the RAKE receiver.

13. An apparatus as described in claim 12, the chip sequence reader using a first fmger select value to access a memory address in the memory that corresponds to the first phase of the first chip sequence, a second fmger select value to access a memory address in the memory that corresponds to the second phase of the first chip sequence, and a third finger select value to access a memory address in the memory that corresponds to the first phase of the second chip sequence.

14. An apparatus as described in claim 1, the chip sequence reader configured to deliver multiple phases of one or more chip sequences to a searcher receiver.

15. An apparatus as described in claim 1, the chip sequence reader configured to deliver a first counter value to a digital receiver before a sleep mode and a second counter value after the sleep mode.

16. An apparatus as described in claim 15, a difference between the second counter value and the first value equal to a number of clock cycles in the sleep mode.

17. An apparatus as described in claim 1, further comprising a controller, the controller configured to deliver instructions to the chip sequence generator.

18. An apparatus as described in claim 17, the controller configured to instruct the chip sequence generator to generate new chip sequences as needed.

19. An apparatus as described in claim 18, the controller configured to instruct the chip sequence generator to write new chip sequences to an address that was used to store a chip sequence that is no longer needed.

20. An apparatus as described in claim 18, wherein at least one of the new chip sequences is a chip sequence necessary to listen for a page.

21. An apparatus for accessing one or more paging sequences, the apparatus comprising: a memory suitable for storing paging sequences; a chip sequence generator configured to write at least one paging sequence to the memory; and, a chip sequence reader configured to read the at least one paging sequence from the memory.

22. An apparatus as described in claim 21, the chip sequence reader configured to read the at least one paging sequence during a period of time preceding an assigned paging frame.

23. A method for providing different chip sequences and different phases of the different chip sequences and different phases of the different chip sequences, the method comprising the steps of: generating a chip sequence; storing the chip sequence in a memory having address locations; and reading different address locations to access different phases of the different chip sequences.

24. A method as described in claim 23, the method further comprising the step of calculating an address location in the memory.

25. A method as described in claim 23, the method further comprising the step of designating a fmger select valve, the finger select valve corresponding to a chip sequence and a phase offset.

26. A method as described in claim 25, furthering comprising the step of calculating a memory address based on the fmger select value.

27. A method as described in claim 23, the method further comprising the step of designating a counter value, the counter value corresponding to a position in time.

28. A method as described in claim 27, the method further comprising the step of calculating a memory address based on the counter value.

29. A method as described in claim 27, the method further comprising the step of advancing the counter value a number of clock cycles in a sleep period.

30. A method as described in claim 23, the step of storing the chip sequence including the step of writing to an address that is used to store a chip sequence that is no longer needed.