WO2000003439A1 - Noise and temperature shield for an integrated circuit - Google Patents

Noise and temperature shield for an integrated circuit Download PDF

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Publication number
WO2000003439A1
WO2000003439A1 PCT/US1999/015335 US9915335W WO0003439A1 WO 2000003439 A1 WO2000003439 A1 WO 2000003439A1 US 9915335 W US9915335 W US 9915335W WO 0003439 A1 WO0003439 A1 WO 0003439A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
conductive layer
substrate
bonding pad
heat
Prior art date
Application number
PCT/US1999/015335
Other languages
French (fr)
Inventor
Akira Ishikawa
Original Assignee
Ball Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ball Semiconductor, Inc. filed Critical Ball Semiconductor, Inc.
Publication of WO2000003439A1 publication Critical patent/WO2000003439A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1017—Shape being a sphere

Definitions

  • the invention relates generally to semiconductor integrated circuits, and more particularly, to an apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit.
  • Electrical devices such as semiconductor integrated circuits are advancing in many ways. For example, many devices are seeing an increase in operating speed, overall size, and number of transistors. These advancements, while creating smaller and faster electrical devices, result in increased electronic noise from the device. Furthermore, power consumption and heat generation inside the device have greatly increased.
  • heat convection is a heat spreader thermally coupled to the device. Heat flows from the device to the heat spreader. The heat spreader is sufficiently large so that it can receive a large amount of heat from the device and can efficiently radiate the heat, thereby cooling the device.
  • convection is a heat sink thermally coupled to the device, combined with a moving air mass. Heat flows from the device to the heat sink, and as the air mass moves across the surface of the heat sink, heat is transferred to the air mass, where it is carried away from the heat sink and the attached device.
  • Chips are formed from a flat surface semiconductor wafer.
  • the semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
  • the present invention accordingly, provides an apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit.
  • a device such as a spherical-shaped semiconductor integrated circuit.
  • one embodiment provides an integrated circuit formed around a spherical substrate.
  • the integrated circuit includes one or more bonding pads for connecting to power supplies and/or other devices.
  • Surrounding the integrated circuit is a conductive layer.
  • the conductive layer is not connected to the integrated circuit, except through a power supply bonding pad.
  • the conductive layer serves to absorb energy such as heat and/or electromagnetic noise.
  • One advantage of the present invention is that the conductive layer is physically part of the integrated circuit device. This facilitates both energy absorption and handing of the device.
  • Fig. 1 illustrates a spherical shaped integrated circuit device according to one embodiment of the invention.
  • Fig. 2 is a cutaway view of the device of Fig. 1.
  • Fig. 3 illustrates a flat shaped integrated circuit device according to another embodiment of the invention.
  • Fig. 4 is a cutaway view of the device of Fig. 3.
  • Fig. 5 is a flowchart for one embodiment of the present invention.
  • the reference numeral 10 designates, in general, a semiconductor integrated circuit device, preferably of a generally spherical shape.
  • the device could be of the same type formed according to the technique disclosed in the above-identified Patent Application Ser. No. 08/858,004.
  • the device 10 is covered by a protective outer coat 12, which may also serve as an identification means for detecting a type (e.g., memory, logic) of the device.
  • a metal shielding layer 14 Located inside the outer coat 12 is a metal shielding layer 14.
  • the shielding layer 14 may be formed by an inductively coupled plasma powder vaporization technique disclosed in Patent Application Ser. No. 09/033,180 filed March 2, 1998 or metal chemical vapor deposition.
  • the outer coat 12 and shielding layer 14 may be one single layer.
  • the device 10 includes several bonding pads, including pads 16a, 16b, 16c, and 16d.
  • the bonding pad 16c is a power pad (e.g., a ground pad). It is understood that other power supplies and/or additional bonding pads may be used to facilitate the functionality of bonding pad 16c.
  • Solder bumps 18a, 18b, 18c, and 18d are electrically attached to bonding pads 16a, 16b, 16c, and 16d, respectively.
  • the metal shielding layer 14 is connected to the bonding pad 16c and solder bump 18c.
  • energy in the form of heat and/or electromagnetic noise is absorbed through the metal shielding layer 14.
  • heat is dissipated through the layer 14 and convected through the solder bump 18c to an external ground (not shown).
  • the reference numeral 50 designates, in general, another, separate embodiment of a semiconductor integrated circuit device, preferably of a generally flat shape.
  • the device 50 is covered by a protective outer coat 52, which may also serve as an identification means for detecting a type (e.g., memory, logic) of the device.
  • the outer coat 52 may include assembly packaging, such as a leadframe, and a packaging material.
  • the packaging material may be plastic, ceramic, or other suitable material.
  • the device 50 includes several bonding pads, including pads 56a - 56i.
  • the bonding pad 56c is a power pad (e.g., a ground pad). It is understood that other power supplies and/or additional bonding pads may be used to facilitate the functionality of bonding pad 56c.
  • Solder bumps 58a - 58i are electrically attached to bonding pads 56a - 56i, respectively.
  • the metal shielding layer 54 is connected to the bonding pad 56c and solder bump 58c.
  • energy in the form of heat and/or electromagnetic noise is absorbed through the metal shielding layer 54.
  • heat is dissipated through the layer 54 and convected through the solder bump 58c to an external ground (not shown).
  • a cutaway view of the device 50 is provided.
  • the cutaway view illustrates a semiconductor substrate 60 and an integrated circuit pattern layer 62.
  • the metal shielding layer 54 actually goes completely around the device 50.
  • one, two or three sides of the metal shielding layer 54, such as a side 54a may be absent.
  • a method 100 may be used to create one or more of the shielding layers on a semiconductor integrated circuit device.
  • the integrated circuit is first fabricated onto the device.
  • the integrated circuit may be completely finished, or may still require a few more fabrications steps.
  • the shielding layer is applied to the outer surface of the integrated circuit.
  • the shielding layer may be a second metal layer applied to the entire integrated circuit.
  • the shielding layer may be applied after the device has been separated from one or more adjoining devices, such as being sawed from a wafer.
  • portions of the shield are removed, as necessary.
  • the shielding layer When the shielding layer is applied to the outer surface, it will electrically connect all of the pads of the device. Since this is seldom desired, portions of the shielding layer must be removed. Specifically, portions that create undesired electrical or magnetic interference must be removed.
  • This removal process can be mechanical, such as a chemi-mechanical polish, chemical such as a wet or dry etch, or by some other means. Certain removal processes are more applicable to different shaped devices, and it is understood that those of ordinary skill in the art can implement the appropriate process.
  • the device is assembled. It is understood, however, that one or more intervening process steps may occur before assembly, such as adding a protective coating on the outside of the shielding layer. It is also understood that different assembly processes are required for different devices. Certain devices, such as the spherical shaped device 10 of Figs. 1-2 may have a relatively simple assembly process of applying a protective coat to the device's outer surface. Other devices, such as the chip 50 of Figs. 3-4, may be mounted onto a lead frame and packaged accordingly.

Abstract

An apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit (10). The integrated circuit is formed around a spherical substrate (20). Surrounding the integrated circuit is a conductive layer (14). The conductive layer (14) is only connected to at least one bonding pad of the integrated circuit. The conductive layer (14) serves to absorb energy such as heat and/or electromagnetic noise.

Description

NOISE AND TEMPERATURE SHIELD FOR AN INTEGRATED CIRCUIT
Background of the Invention
The invention relates generally to semiconductor integrated circuits, and more particularly, to an apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit. Electrical devices such as semiconductor integrated circuits are advancing in many ways. For example, many devices are seeing an increase in operating speed, overall size, and number of transistors. These advancements, while creating smaller and faster electrical devices, result in increased electronic noise from the device. Furthermore, power consumption and heat generation inside the device have greatly increased.
The detrimental effects of noise inside a device, such as cross-talk and signal distortion, are well known in the art. As a result, designers of computers and other electronic circuits have utilized various techniques to isolate, or dampen, noise from the electrical device. Two such techniques involve physical separation and shielding. Physical separation relies on the principle that noise diminishes over distance. Shielding, on the other hand, is to place a separate physical structure between the electrical device and any other devices to absorb noise. For example, components of a computer power supply are often placed in a metal box to shield noise from the computer's motherboard. The detrimental effects of excessive heat inside a device, such as reduction of the extended life and reliability of the device, are also well known in the art. As a result, designers of computers and other electronic circuits have utilized various techniques to remove, or dissipate, heat from the electrical device. Two such techniques involve heat convection and conduction. An example of conduction is a heat spreader thermally coupled to the device. Heat flows from the device to the heat spreader. The heat spreader is sufficiently large so that it can receive a large amount of heat from the device and can efficiently radiate the heat, thereby cooling the device. An example of convection is a heat sink thermally coupled to the device, combined with a moving air mass. Heat flows from the device to the heat sink, and as the air mass moves across the surface of the heat sink, heat is transferred to the air mass, where it is carried away from the heat sink and the attached device.
Conventional devices, or "chips," are formed from a flat surface semiconductor wafer. The semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
In co-pending U.S. Patent Application Ser. No. 08/858,004 filed on May 16, 1997, a method and apparatus for manufacturing spherical-shaped semiconductor integrated circuit devices is disclosed. Being spherical-shaped and having a relatively large surface area, noise and heat are often accentuated. The present invention provides an apparatus and method for reducing noise and heat on devices such as those that are spherical in shape. Summary of the Invention
The present invention, accordingly, provides an apparatus and method for reducing noise and/or heat on a device such as a spherical-shaped semiconductor integrated circuit. To this end, one embodiment provides an integrated circuit formed around a spherical substrate. The integrated circuit includes one or more bonding pads for connecting to power supplies and/or other devices. Surrounding the integrated circuit is a conductive layer. The conductive layer is not connected to the integrated circuit, except through a power supply bonding pad. The conductive layer serves to absorb energy such as heat and/or electromagnetic noise.
One advantage of the present invention is that the conductive layer is physically part of the integrated circuit device. This facilitates both energy absorption and handing of the device. Brief Description of the Drawings
Fig. 1 illustrates a spherical shaped integrated circuit device according to one embodiment of the invention.
Fig. 2 is a cutaway view of the device of Fig. 1. Fig. 3 illustrates a flat shaped integrated circuit device according to another embodiment of the invention.
Fig. 4 is a cutaway view of the device of Fig. 3. Fig. 5 is a flowchart for one embodiment of the present invention. Description of the Preferred Embodiment Referring to Fig. 1, the reference numeral 10 designates, in general, a semiconductor integrated circuit device, preferably of a generally spherical shape. For the sake of example, the device could be of the same type formed according to the technique disclosed in the above-identified Patent Application Ser. No. 08/858,004. The device 10 is covered by a protective outer coat 12, which may also serve as an identification means for detecting a type (e.g., memory, logic) of the device. Immediately inside the outer coat 12 is a metal shielding layer 14. For the sake of example, the shielding layer 14 may be formed by an inductively coupled plasma powder vaporization technique disclosed in Patent Application Ser. No. 09/033,180 filed March 2, 1998 or metal chemical vapor deposition. In some embodiments, the outer coat 12 and shielding layer 14 may be one single layer. The device 10 includes several bonding pads, including pads 16a, 16b, 16c, and 16d. In the present example, the bonding pad 16c is a power pad (e.g., a ground pad). It is understood that other power supplies and/or additional bonding pads may be used to facilitate the functionality of bonding pad 16c. Solder bumps 18a, 18b, 18c, and 18d are electrically attached to bonding pads 16a, 16b, 16c, and 16d, respectively.
In the present example, the metal shielding layer 14 is connected to the bonding pad 16c and solder bump 18c. As a result, when the device 10 is operating, energy in the form of heat and/or electromagnetic noise is absorbed through the metal shielding layer 14. Also, heat is dissipated through the layer 14 and convected through the solder bump 18c to an external ground (not shown).
Referring also to Fig. 2, to better understand the position of the metal shielding layer 14, a cutaway view of the device 10 is provided. The cutaway view illustrates a semiconductor substrate 20 and an integrated circuit pattern layer 22. In the present embodiment, there is no electrical or thermal connection between the integrated circuit pattern layer 22 and the metal shielding layer 14 except through the bonding pad 16c. It is understood, however, that other such connections may indeed exist. Referring to Fig. 3, the reference numeral 50 designates, in general, another, separate embodiment of a semiconductor integrated circuit device, preferably of a generally flat shape. The device 50 is covered by a protective outer coat 52, which may also serve as an identification means for detecting a type (e.g., memory, logic) of the device. The outer coat 52 may include assembly packaging, such as a leadframe, and a packaging material. The packaging material may be plastic, ceramic, or other suitable material.
Immediately inside the outer coat 52 is a metal shielding layer 54. In some embodiments, the outer coat 52 and shielding layer 54 may be one single layer. The device 50 includes several bonding pads, including pads 56a - 56i. In the present example, the bonding pad 56c is a power pad (e.g., a ground pad). It is understood that other power supplies and/or additional bonding pads may be used to facilitate the functionality of bonding pad 56c. Solder bumps 58a - 58i are electrically attached to bonding pads 56a - 56i, respectively.
In the present example, the metal shielding layer 54 is connected to the bonding pad 56c and solder bump 58c. As a result, when the device 50 is operating, energy in the form of heat and/or electromagnetic noise is absorbed through the metal shielding layer 54. Also, heat is dissipated through the layer 54 and convected through the solder bump 58c to an external ground (not shown). Referring also to Fig. 4, to better understand the position of the metal shielding layer 54, a cutaway view of the device 50 is provided. The cutaway view illustrates a semiconductor substrate 60 and an integrated circuit pattern layer 62. In the present embodiment, there is no electrical or thermal connection between the integrated circuit pattern layer 52 and the metal shielding layer 54, except through the bonding pad 56c. It is understood, however, that other such connections may indeed exist. The metal shielding layer 54 actually goes completely around the device 50. In alternate embodiments, one, two or three sides of the metal shielding layer 54, such as a side 54a, may be absent.
Referring now to Fig. 5, a method 100 may be used to create one or more of the shielding layers on a semiconductor integrated circuit device. At step 102, the integrated circuit is first fabricated onto the device. The integrated circuit may be completely finished, or may still require a few more fabrications steps. At step 104, once fabricated, the shielding layer is applied to the outer surface of the integrated circuit. In some embodiments, such as the spherical shaped device 10 of Fig. 1, the shielding layer may be a second metal layer applied to the entire integrated circuit. In other embodiments, such as the flat chip device 50 of Fig. 3, the shielding layer may be applied after the device has been separated from one or more adjoining devices, such as being sawed from a wafer.
At step 106, portions of the shield are removed, as necessary. When the shielding layer is applied to the outer surface, it will electrically connect all of the pads of the device. Since this is seldom desired, portions of the shielding layer must be removed. Specifically, portions that create undesired electrical or magnetic interference must be removed. This removal process can be mechanical, such as a chemi-mechanical polish, chemical such as a wet or dry etch, or by some other means. Certain removal processes are more applicable to different shaped devices, and it is understood that those of ordinary skill in the art can implement the appropriate process.
At step 108, the device is assembled. It is understood, however, that one or more intervening process steps may occur before assembly, such as adding a protective coating on the outside of the shielding layer. It is also understood that different assembly processes are required for different devices. Certain devices, such as the spherical shaped device 10 of Figs. 1-2 may have a relatively simple assembly process of applying a protective coat to the device's outer surface. Other devices, such as the chip 50 of Figs. 3-4, may be mounted onto a lead frame and packaged accordingly.
The above description is merely an example of certain embodiments of the present invention. Modifications, changes and substitutions are intended in the foregoing disclosure and in some instances some features of the invention will be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Claims

WHAT IS CLAIMED IS:
1. An integrated circuit device comprising: a substrate; an integrated circuit formed on the substrate; at least one bonding pad connected to the integrated circuit; a conductive layer surrounding the integrated circuit and connected to the at least one bonding pad.
2. The device of claim 1 wherein the conductive layer is electrically disconnected from the integrated circuit except through the bonding pad.
3. The device of claim 1 wherein the conductive layer substantially surrounds the substrate.
4. The device of claim 1 wherein the conductive layer is a thermal conductor.
5. The device of claim 1 wherein the conductive layer is an electromagnetic shield.
6. The device of claim 1 wherein a portion of the conductive layer is removed to provide electrical isolation from another bonding pad connected to the integrated circuit.
7. The device of claim 1 further comprising: an assembly package surrounding the conductive layer.
8. The device of claim 7 wherein the assembly package is applied directly to the conductive layer.
9. The device of claim 1 wherein the substrate is spherical shaped.
10. A method for insulating an integrated circuit device formed on a substrate, the integrated circuit having a plurality of external connectors, the method comprising the steps of: applying a conductive layer around the substrate and the integrated circuit for covering a significant portion thereof; connecting the conductive layer to a first one of the external connectors; and isolating the conductive layer from a second one of the external connectors.
11. The method of claim 10 wherein there is no direct electrical connection between the conductive layer and the integrated circuit, except through the first external connector.
12. The method of claim 10 wherein the conductive layer is a thermal conductor for the integrated circuit device.
13. The method of claim 10 wherein the conductive layer is an electromagnetic shield for the integrated circuit device.
14. The method of claim 10 further comprising: applying an assembly package surrounding the conductive layer for supporting the integrated circuit device.
15. The method of claim 14 wherein the assembly package is applied directly to the conductive layer.
16. The method of claim 10 wherein the substrate is spherical shaped.
PCT/US1999/015335 1998-07-10 1999-07-07 Noise and temperature shield for an integrated circuit WO2000003439A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US9364998P 1998-07-10 1998-07-10
US60/093,649 1998-07-10
US34735999A 1999-07-06 1999-07-06
US09/347,359 1999-07-06

Publications (1)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126812A (en) * 1976-12-20 1978-11-21 Texas Instruments Incorporated Spherical light emitting diode element and character display with integral reflector
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5945725A (en) * 1996-12-04 1999-08-31 Ball Semiconductor, Inc. Spherical shaped integrated circuit utilizing an inductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126812A (en) * 1976-12-20 1978-11-21 Texas Instruments Incorporated Spherical light emitting diode element and character display with integral reflector
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5945725A (en) * 1996-12-04 1999-08-31 Ball Semiconductor, Inc. Spherical shaped integrated circuit utilizing an inductor

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