WO2000005813A2

WO2000005813A2 - Electrical high power pulse generator

Info

Publication number: WO2000005813A2
Application number: PCT/IL1999/000382
Authority: WO
Inventors: Israel Smilanski
Original assignee: Rotem Industries Ltd.
Priority date: 1998-07-23
Filing date: 1999-07-12
Publication date: 2000-02-03
Also published as: AU4645799A; CA2338111A1; JP2002521995A; IL125490A0; WO2000005813A3

Abstract

A system for providing high power pulses into a load, the system comprising: a load (6); a Capacitor Charging Power Supply (CCPS) (14) for providing a plurality of low power pulses; a pulsed power circuit receiving the low power pulses, and providing high power pulses to the load, said pulsed power circuit comprising: a) a first storage capacitor (C1); b) controlled switching means (S1), for allowing the first storage capacitor to discharge; and c) pulse compression means (C2, LS), said pulse compression means receiving a current pulse resulting from the first storage capacitor discharge, and providing to the load a pulse of higher current and shorter duration than the current pulse it received. The system comprises an inductor (L4) of high inductance in the branch linking the CCPS and the pulsed power circuit, said inductor enabling recovery of the energy reflected, from the load, and protecting components of the CCPS from damage that may be caused by said reflected energy.

Description

IMPROVEMENT TO PULSED POWER

Field of the Invention

The invention relates to pulsed power circuits. More particularly, the invention

relates to means for providing energy recovery, increasing efficiency, and

improving the reliability of pulsed power circuits.

Background of the Invention

Pulsed power is widely used in the art when it is needed to provide to a load

pulses of high power. Pulsed power is used, for example, for exciting lasers, for

activating magnetrons or klystrons in radar systems, or in other applications

where a supply of high-power pulses is required. In order to provide high

energy and short-duration pulses, i.e., high power pulses, it is common to use a

circuit comprising a storage capacitor, to charge the same with an electric

charge, and to rapidly discharge the capacitor into the load. In some cases, the

storage capacitor is replaced by a Pulse Forming Network (P.F.N), which is a

network comprising a plurality of capacitors (hereinafter, when the term

"storage capacitor" is used, it should be noted that it may also refer to the use

of a P.F.N)

Pulsed power circuits are typically fed by a device, generally called Capacitor

Charging Power Supply (CCPS), which provides charge to the storage

capacitor. One typical circuitry for that purpose is a pulse generator, which generates a series of low power pulses for providing a uni-polar charge to the

storage capacitor during a period designated for charging, said period

hereinafter referred to as "the charging period". During the charging period, a

switching element, such as an SCR, Thyratron, Spark gape, etc., which is

located in the branch connecting the storage capacitor and the load, is kept in

an "Off' state, thereby inhibiting current flow and discharge of the storage

capcitor to the load, and allowing charge accumulation in said capacitor. When

the charge in the storage capacitor reaches a predetermined desired level, the

operation of the CCPS is deactivated, and a control signal is generally provided

to the control of the switching element, thereby to cause the capacitor to

rapidly discharge its accumulated charge into the load. Said capacitor

discharge takes place during a period hereinafter referred to as "the

discharging period", a period which is much shorter than the above-mentioned

charging period. Therefore, the pulsed power circuit actually provides a power

gain of the ratio τ τi, wherein τi is the charging period, and τ₂ is the discharging

period.

Some pulsed power also comprises pulse compression means in the form of one

or more stages in which each stage comprises a serial saturable-core inductor

and a parallel capacitor, connected between the switching means and the load.

Such pulse compression means are known, and are discussed, for example, in

WO 96/25778. Some variations to the compression stage have also been

suggested, e.g., in US 5,079,689. Generally, the CCPS comprises at its output at least one diode. Said diode of

the CCPS is connected in parallel to the storage capacitor, or is essentially in

parallel to the same, due to the low output impedance of the CCPS.

Generally, the load to which the power pulses are supplied is not purely

resistive, but has a complex nature. To the complex nature of the load may

further be contributed parasitic inductivity of the circuit conductors, the

inductivity of the magnetic compression elements, if existing, or any complex

contribution from other possible elements in the circuit. This complex nature, if

mismatched with the previous circuitry, allows only a portion of the energy to

dissipate on the load, and causes the rest of the energy to reflect back from it in

the form of some damped oscillations. These oscillations, above and below the

z&ro potential level, tend to cause the storage capacitor to alternatively charge

and discharge in alternating directions. These oscillations may continue as long

as the switching element is ON, and stop only when it switches to OFF. The

switching OFF of the switching element occurs only after a characteristic

recovery period of the switching element lapses, in which the current through it

is below some current level Ih. The said oscillations, which in some cases

involve energy reflection from the load of as high as 20% of the total storage

capacitor discharge energy, present two major problems:

1. When the storage capacitor is negatively charged by the current

reflection from the load, a current flows in the direction back to the CCPS, through the CCPS output diode, and as this diode is often a low power diode, it

can cause this diode to fail.

2. If the switching element switches back to OFF when the potential of

the storage capacitor is negatively charged, i.e., in opposite polarity than

required, in the next charging period it will be required to provide higher

charging energy from the CCPS to the storage capacitor, in order to first empty

the storage capacitor from the said reverse polarity charge, and then to

recharge the capacitor with energy in the right direction. It would be desirable

to provide energy recovery by reversing the direction of the charge accumulated

in the storage capacitor before the beginning of the new charging period, and in

doing so, to reuse this energy in the next charging-discharging cycle of the

storage capacitor.

WO 96/25778 discloses means for providing recovery of the energy reflected

from the load in pulsed power. Said means include providing a diode and a

serial inductor, both in parallel to the storage capacitor. However, it has been

found that with the arrangement disclosed in said publication, energy recovery

cannot be obtained due to a reason that is hereinafter discussed in more detail.

Moreover, the solution of WO 96/25778 may cause the one or more output

diodes of the charging circuitry (generally a CCPS) to fail. It is therefore an object of the invention to provide means for preventing

damage to components of the CCPS due to power reflection from the pulsed

power circuit.

It is another object of the invention to increase the efficiency of existing pulsed

power, by enabling to utilize the energy reflected from the load in the next

storage capacitor recharging period.

It is a further object of the invention to provide said means in a simple and

compact and inexpensive manner.

Other objects and advantages of the invention will become apparent as the

description proceeds.

Summary of the Invention

The invention relates to a system for providing high power pulses into a load,

the said system comprising: A load; a Capacitor Charging Power Supply

(CCPS) for providing plurality of low power pulses; a pulsed power circuit

receiving the low power pulses from the CCPS, and providing high power

pulses to the load, said pulsed power circuit comprising:

a. A first storage capacitor (or a P.F.N) for storing the charge, said

charge resulting from a plurality of said low power pulses; b. Controlled switching means, said switching means being timely

turned ON for allowing the first storage capacitor to discharge the

accumulated charge resulting from the plurality of low power pulses

received, thereby providing a pulse of current; and

c. Pulse compression means, said pulse compression means receiving a

current pulse resulting from the first storage capacitor discharge, and

providing to the load a pulse of higher current and shorter duration than

the current pulse it received.

The system is characterized in that it comprises an inductor of high inductance

in the branch Hnking the CCPS and the pulsed power, said inductor of high

inductance enabling recovery of the energy reflected from the load, and

protecting components of the CCPS from damage that may be caused by said

energy reflected from the load.

According to one embodiment of the invention, the system comprises a load; a

Capacitor Charging Power Supply (CCPS) for providing pulses of low power; a

pulsed power circuit receiving the low power pulses from the CCPS, and

providing high power pulses to the load, said pulsed power circuit comprising:

a. A first storage capacitor for storing the charge, said first storage

capacitor receiving a plurality of said low power pulses from the CCPS;

b. Controlled switching means connected at its first end to the first

storage capacitor and at its second end to a first end of a first inductor, which in turn is connected at its second end to a pulse compression

means, said switching means being timely turned ON for allowing the

first storage capacitor to discharge the accumulated charge resulting

from the plurality of low power pulses received, thereby providing a

pulse of current to said pulse compression means through said first

inductor; and

c. Pulse compression means connected at its first end to the second end of

the first inductor and at its second end to the load, the pulse compression

means receiving a current pulse resulting from the first storage capacitor

discharge, and providing to the load a pulse of higher current and shorter

duration than the current pulse it received;

The system is characterized in that it comprises a second inductor of high

inductance in the branch linking the CCPS with the first storage capacitor of

the pulsed power, said inductor of high inductance enabling recovery of the

energy reflected from the load, and for protecting components of the CCPS from

damage caused by said energy reflected from the load.

In the system of the invention, the energy recovery is provided by current

flowing from the second end of the first storage capacitor, through the second

inductor, therough the CCPS, to the first end of the first storage capacitor. Preferably, the inductance of the second inductor is much higher than that of

the inductance of the first inductor, preferably at least two to three times

greater than the inductance of the first inductor.

Preferably, the pulse compression means comprises at least one stage of a

pulse compression unit, wherein each stage of pulse compression unit

comprises a second storage capacitor which receives the current pulse resulting

from the first storage capacitor discharge or from a previous stage of pulse

compression unit; and a saturated core inductor, . timely saturated for allowing

a rapid discharge of said second capacitor, thereby providing a pulse of high

current and short duration to the load, or to the next stage of the pulse

compression unit.

According to another embodiment of the invention, the system further

comprises a diode in series with a third inductor, both being in a branch

parallel to the first storage capacitor, for providing recovery of the energy

reflected from the load. In such a case, the inductance of the third inductor

should preferably be much larger than that of the first inductor, and the

inductance of the second inductor should be much larger still than the

inductance of the said third inductor. By the term "much larger" herein, is

meant to indicate a relation of at least two to three times. In many cases, the CCPS and the pulsed power circuitry are manufactured by-

two separate manufacturers, and are packaged in two separate casings. The

second inductor according to the invention can be positioned in either one of

the said casings, as long as it is located serially in the branch connecting the

CCPS with the pulsed power circuitry.

Brief Description of the Drawings

In the drawings:

- Fig. 1 shows a principle basic scheme of a pulsed power circuit according to

the prior art;

- Fig. 2a and 2b are timing diagrams illustrating respectively the voltage V_cι on

the first storage capacitor Ci and the current Is through the SCR Si, according

in the circuit of Fig. 1;

- Fig. 3 shows shows the circuit of Fig. 1 connected to a CCPS;

- Fig. 4a and 4b are timing diagrams illustrating respectively the voltage V_cι on

the first storage capacitor Cl and the current Is through the SCR Si, according

to the circuit of Fig. 3 when L2 » Li; Fig. 5a and 5b are timing diagrams illustrating respectively the voltage V_cι oh"

the first storage capacitor Cl and the current Is through the SCR Si, according

to the circuit of Fig. 3 when L 2 « Li;

- Fig. 6 shows still another principle scheme of a pulsed power, seemingly with

means for energy recovery, according to the prior art;

- Fig. 7 shows a principle scheme of a pulsed power circuit, according to one

embodiment of the invention;

- Fig. 8 shows a principle scheme of a pulsed power, according to another

embodiment of the invention;

Detailed Description of Preferred Embodiments

Fig. 1 shows a principle scheme of a pulsed power circuit. It should be noted

here that throughout the description, principle schemes indicating only

essential elements are discussed. Of course, in most cases, pulsed power

circuits comprise additional components which are not indicated or discussed

herein, for the sake of brevity. However, the description, and particularly the

invention is good also for these more comphcated variants of pulsed power

circuits. As shown in Fig. 1, a typical pulsed power circuit basically comprises a first

storage capacitor Ci, a switching component such as an SCR, Si, an inductor

Li, second storage capacitor C2, a saturable-core inductor L_s, and a load 6, for

example, a laser. Hereinafter, reference will be made to a switching component

Si of the SCR type, although another suitable controlled switching component

may be used, as is well known to those skilled in the art.

Fig. 2a is a timing diagram illustrating the voltage V_cι on the storage capacitor

Ci versus time, during a typical operation of the pulsed power circuit of Fig. 1.

Fig. 2b is a timing diagram illustrating the current I_s through the SCR Si.

Initially, the SCR Si is in the OFF state. During the charging period, which is

not indicated in Fig. 1, the capacitor Ci is charged by CCPS 14 to the desired

amount. When the charge in the capacitor Ci has accumulated the desired

amount, the supply of the charge from the CCPS 14 lapses. At that time, the

CCPS has finished its task of charging Ci, until the next charging period.

Assuming that at this stage CCPS 14 is disconnected from the circuit, at any

later desired time, to the control 7 of Si is provided with a control signal to turn

the SCR Si into an ON state. Then, a current through the SCR Si starts to

flow, while the voltage on the capacitor Ci decreases, as described by the

following formulas:

In the above formulas, Vo indicates the voltage of capacitor Ci at to. The

formulas are for the case when Ci = C2, which provides the best energy

delivery. At ti, when the capacitor Ci is essentially discharged, the current I_s is

essentially zero. At that time, most of the charge of the storage capacitor Ci

has been transferred to the second capacitor C2, which is charged such that the

potential of its plate 8 is higher than that of its plate 9. Hereinafter, the term

"positively charged" capacitor, when referred to capacitors Ci or C2, intends to

relate to a state in which plate 12 or plate 8 has a higher potential than plate

13 or 9 of the capacitor, respectively. The term "negatively charged" capacitor,

when referred to capacitor Ci or C₂, intends to relate to a state in which plate

12 or plate 8 has a lower potential than plate 13 or plate 9 of the capacitor,

respectively. In other words, at ti the voltage of Ci and the current I_s are

essentially zero, and the capacitor C2 is positively charged. After a delay, which

takes the core of L_s to saturate, the inductance of L_s dramatically falls, thereby

allowing the current through it to rapidly rise, and causing C2 to rapidly

discharge through L_s to the load 6. Ideally, in cases when the load 6 is matched

with the pulsed power circuitry, all the energy which is first stored in capacitor Ci, and later transferred to C2, is dissipated on the load 6. In such an ideal

case, when the load 6 is matched, the voltage on Ci remains essentially zero

until the next charging period. However, it is hard to assure a complete match

between the load and the previous circuitry, and generally, in most cases, the

load is mismatched. In such cases, not the whole of the energy that C2 provides

to the load is dissipated on it, but some of it is reflected back, in the form of

resonance current fluctuations. The current during the first half period of the

resonance fluctuations has a direction as shown by arrow 11. As at this stage

the inductance of Li is significantly higher than that of L_s, and although Si is

still ON, this current negatively charges C2 and does not charge Ci. More

particularly, between t₂ and t3, C2 transfers its energy to the load, and then it is

negatively charged by the energy reflected from the load, which energy in

many cases is a significant portion of the energy that C₂ provides to the load.

Then, at t2, C2 is negatively charged, while the potential of Ci is essentially

zero. Next, as at this stage the SCR Si is still ON, between t2 and t3, C2 starts

to discharge, and now negatively charges Ci. This process of charge tranfer

from C2 to Ci, which takes place between t2 and t3, is also shown in Figs. 2a

and 2b, and can be described by the following formulas:

wherein V2 indicates the voltage of capacitor C2 at t₂. The minus sign

indicates that at t₂, the second capacitor C2 is negatively charged, and therefore

between t2 and t3, the capacitor Ci also negatively charges. The direction of the

current through Si, however, still remains the same as before. Formulas (3)

and (4) are for the case in which Ci = C2 is the prefered case. This charge

transfer from C2 to Ci, which starts at t2, continues as long as Si is ON, as also

shown in Figs. 2a and 2b. After a while, at t3, when the potential of Ci reaches

a specific negative level, while the current I_s is essentially zero, a recovery of

the SCR Si takes place, and it switches to OFF.

Let us now examine a more realistic case, as shown in Fig. 3. The transform

circuit of the CCPS 14 of Fig. 1 can be realized as an inductor L2, in series with

a diode Di. Diode Di symbolically indicates here the one or more diodes in the

output of the CCPS. Let us now examine two cases:

In both of the said cases (I) and (II), the operation of the pulsed power of Fig. 3

is identical to the operation of the circuit of Fig. 1 in the timing interval to to t₂.

Figs. 4a and 4b are timing diagrams describing respectively the voltage V_cι and

the current I_cι for the first case (I), when L2 » Li in the circuit of Fig. 3. The

operation of the circuit of Fig. 3 is identical to the operation of the circuit of Fig.

1 in the time intervals between to-tβ. At t3, after the switching OFF of SCR Si,

Ci is negatively charged. The capacitor Ci cannot discharge through the SCR

Si, as Si is OFF and does not allow current flow through it. The only route that

remains for Ci to discharge is through L2 and Di of the CCPS 14. Di is

forwardly biased in t3 because, as said, Ci is negatively charged at that time.

Therefore, between tβ and t₄ a current I_p will flow in the direction as indicated.

The current I_p and the voltage V_cι in the time interval t3-t can be described by

the following formulas: -

As is clear from formula (6), the current I_p substantially depends on the value

of L2. However, as according to condition (I) the inductance of L2 is high, and

therefore the current I_p is relatively low in all the time interval t3-t . At t it

can be seen that the capacitor Ci is positively charged, and the SCR Si is OFF.

The circuit is ready for the next charging period, and the charge of Ci at t , as accumulated from the energy reflected from the load, can be utilized in the"

next charging period. In other words, the reflected energy is recovered and can

be used.

Figs. 5a and Fig. 5b are timing diagrams describing, respectively, the voltage

Vci and the current I_cι for the second case (II), when L2 « Li in the circuit of

Fig. 3. The operation of the circuit of Fig. 3 in case (II) is identical to the

operation of the circuit of Fig. 1 only in the time intervals of to-t2. In that case,

when the inductance of L2 is extremely low, and can be negligible, at t2, the

second capacitor C2 is negatively charged as before, and the diode Di is

forwardly biased. When forwardly biased, this diode actually shorts the storage

capacitor Ci, and does not allow it to charge. The second capacitor C2 will

therefore discharge through the inductor L2 and the diode Di, the switching

component Si, and inductor Li. Si will remain ON, as the potential on its anode

will not reduce below zero. There will be no energy recovery. The current flow

through the diode Di in the interval t2-tβ will be:

As in this case L2 « Li, formula (7) can be reduced to:

This is a very high current that in many cases may cause diode Di to fail. In conventional CCPS, the inductance of L2 is very low, and condition (II), i.e.,

L2 « Li, holds. WO 96/25778 discusses a pulsed power with means for energy

recovery, as basically shown in Fig. 6. Said means include a diode D2 in series

with inductor L3, both being in parallel to the capacitor Ci. According to WO

96/25778, the negatively charged Ci can discharge through diode D2 and

inductor L3 in the interval t3-t₄, in order to obtain energy recovery as discussed

above for case (I). However, the condition of case (I) does not hold in any

conventional CCPS, but the condition of case (II) holds. That means that the

addition of diode D2 and inductor L3 in WO 96/25778 does not affect the circuit

at all. They are both shorted by the extremely low inductance of L2 and the

diode Di which is forwardly biased in the interval t2-t₄. Therefore, the energy

recovery means of D2 and L3 cannot function, no energy recovery can be

achieved by said means, and no solution can be provided by WO 96/25778 ±o

the danger introduced by the high current through the one or more diodes of

the CCPS, which are symbolically indicated herein as Di.

A solution to this problem is provided by the present invention. As shown in

Fig. 7, according to the invention, an inductor L₄ is provided in the branch

Hnking the CCPS with the pulsed power circuitry. The inductor L₄, having

inductance much larger than of Li, adds to the very low inductance of L2,

(which is actually the internal inductance of the CCPS), and makes the circuit

essentially as of case (I). According to one embodiment of the invention, as shown in Fig. 7, the simple

inclusion of L₄ having high inductance in the branch linking the CCPS to the

storage capacitor of Ci, by itself provides energy recovery and protection to the

one or more diodes Di of the CCPS. The energy recovery is provided by the

current flowing through the said inductor L₄, through L2, and through the one

or more diodes Di during the time interval t3-t₄. In said time interval, the

current is described by the following formula:

wherein V3 is the voltage on C2 at t3. In such a case, the one or more diodes Di

should be able to support at least the maximum of the current I_p, given by

formula (9). The above solution is preferable when it can be assured that Di

ean support this maximal current flowing through it, during the period that

the energy recovery takes place, i.e., between t3 and t₄.

In some cases the CCPS and the pulsed power circuit are produced by two

different manufacturers, and are packaged in two separate housings, and the

type of Di and the current that this diode can maintain is unknown. In these

cases, it is preferable not to carry out the energy recovery through L₄, L2, and

diode Di of the CCPS, but to use in combination high inductance L₄ for

preventing the reflected current from flowing through components of the

CCPS, and separate means for carrying out the energy recovery. Fig. 8 shows a circuit according to another embodiment of the invention for carrying out

energy recovery, while still protecting components of the CCPS from

overcurrent. The circuit of Fig. 8 comprises a branch in parallel to the first

storage capacitor Ci, which includes an inductor L3 in series with diode D₂.

Preferably, the following relations should be maintained between the

inductors:

(10). L₄» Lι;

(ll). L₃ » Lι; and

(12). L₃ < L₄;

In this case, the large inductance of L essentially eliminates current flow

through it from the pulsed power to the CCPS between t3 and t₄. At that time,

the current flows in the branch of D2 and L3 because of condition (12) above.

The formula essentially describing this current during the time interval t3 - t

is:

Therefore, in this case, the components of the CCPS are protected from

overcurrent in the time interval t3 - t , and also energy recovery is carried out

during this period. In the circuits above, the exact values of the inductors Li, L3, and L₄ depend on

specific cases and design considerations. However, when carrying out the

invention into practice, the inductors values can be easily selected by those

skilled in the art, keeping in mind the relations given above.

While some embodiments of the invention have been described by way of

illustration, it will be apparent that the invention can be carried into practice

with many modifications, variations and adaptations, and with the use of

numerous equivalents or alternative solutions that are within the scope of

persons skilled in the art, without departing from the spirit of the invention or

exceeding the scope of the claims.

Claims

1. A system for providing high power pulses into a load, the system comprising:

- A load;

- A Capacitor Charging Power Supply (CCPS) for providing a plurality of low

power pulses;

- A pulsed power circuit receiving the low power pulses from the CCPS, and

providing high power pulses to the load, said pulsed power circuit comprising:

a. A first storage capacitor for storing the charge, said charge resulting

from a plurality of said low power pulses;

b. Controlled switching means, said switching means being timely

turned ON for allowing the first storage capacitor to discharge the

accumulated charge resulting from the plurality of low power pulses

received, thereby providing a pwlse of current; and

c. Pulse compression means, said pulse compression means receiving a

current pulse resulting from the first storage capacitor discharge, and

providing to the load a pulse of higher current and shorter duration than

the current pulse it received;

Said system is characterized in that it comprises an inductor of high

inductance in the branch hnking the CCPS and the pulsed power, said inductor

of high inductance for enabhng recovery of the energy reflected from the load, and for protecting components of the CCPS from damage that may be caused-

by said energy reflected from the load.

2. A system according to claim 1 for providing high power pulses into a load,

the system comprising:

- A load;

- A Capacitor Charging Power Supply (CCPS) for providing pulses of low

power;

- A pulsed power circuit receiving the low power pulses from the CCPS, and

providing high power pulses to the load, said pulsed power circuit comprising:

a. A first storage capacitor for storing the charge, said first storage

capacitor receiving a plurality of said low power pulses from the CCPS;

b. Controlled switching means connected at its first end to the first

storage capacitor and at its second end to a first end of,a first inductor,

which in turn is connected at its second end to a pulse compression

means, said switching means being timely turned ON for allowing the

first storage capacitor to discharge the accumulated charge resulting

from the plurality of low power pulses it received, thereby providing a

pulse of current to said pulse compression means through said first

inductor; and

c. Pulse compression means connected at its first end to the second end of

the first inductor and at its second end to the load, said pulse

compression means receiving a current pulse resulting from the first storage capacitor discharge, and providing to the load a pulse of higher

current and shorter duration than the current pulse it received;

Said system is characterized in that it comprises a second inductor of high

inductance in the branch hnking the CCPS with the first storage capacitor of

the pulsed power, said inductor of high inductance for enabhng recovery of the

energy reflected from the load, and for protecting components of the CCPS from

damage that may be caused by said energy reflected from the load.

3. A system according to claim 2, wherein the inductance of the second inductor

is much higher than that of the inductance of the first inductor.

4. A system according to claim 3, wherein the inductance of the second inductor

is at least two to three times greater than that of the first inductee'.

5. A system according to claim 1 or 2, wherein the pulse compression means

comprise at least one stage of pulse compression unit.

6. A system according to claim 5, wherein each stage of pulse compression unit

comprises:

- A second storage capacitor which receives the current pulse resulting from the

first storage capacitor discharge or from a previous stage of pulse compression

unit; and - A saturated core inductor, timely saturated for allowing a rapid discharge of

said second capacitor, thereby providing a pulse of high current and short

duration to the load, or to the next stage of pulse compression unit.

7. A system according to claim 2, further comprising a diode in series with a

third inductor, both in a branch parallel to the first storage capacitor, for

providing recovery of the energy reflected from the load.

8. A system according to claim 7, wherein the inductance of the said third

inductor is larger than that of the first inductor, and the inductance of the

second inductor is larger than the inductance of the said third inductor.

9. A system according to claim 2, wherein the energy recovery is provided by

current flowing from the second end of the first storage capacitor, through the

second inductor, through the CCPS, to the first end of the first storage

capacitor.

10. A system according to claim 7, wherein the energy recovery is provided by

current flowing from the second end of the first storage capacitor, through the

branch of the third inductor and diode, to the first end of the first storage

capacitor.

11. A system according to claim 1 or 2, wherein the second inductor is located^*

in the pulsed power casing.

12. A system according to claim 1 or 2, wherein the second inductor is located

in the CCPS casing.

13. A system according to claim 1 wherein the first storage capacitor is a P.F.N.

14. A system according to claim 1, essentially as described and illustrated.