WO2000010195A3 - Preparation of metal-precipitates permeable insulator for soi substrate - Google Patents

Preparation of metal-precipitates permeable insulator for soi substrate Download PDF

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Publication number
WO2000010195A3
WO2000010195A3 PCT/US1999/018085 US9918085W WO0010195A3 WO 2000010195 A3 WO2000010195 A3 WO 2000010195A3 US 9918085 W US9918085 W US 9918085W WO 0010195 A3 WO0010195 A3 WO 0010195A3
Authority
WO
WIPO (PCT)
Prior art keywords
metal
precipitates
preparation
soi substrate
wafer
Prior art date
Application number
PCT/US1999/018085
Other languages
French (fr)
Other versions
WO2000010195A2 (en
Inventor
Robert J Falster
Robert A Craven
Original Assignee
Memc Electronic Materials
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials filed Critical Memc Electronic Materials
Priority to AU54742/99A priority Critical patent/AU5474299A/en
Publication of WO2000010195A2 publication Critical patent/WO2000010195A2/en
Publication of WO2000010195A3 publication Critical patent/WO2000010195A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Abstract

A process for inhibiting the formation of metal-precipitate defects in an SOI wafer is disclosed. The process includes heating the wafer for a time sufficient to reduce metal concentration in the monocrystalline film through diffusion into the bulk of the wafer. The insulator structure is made permeable via holes, channels, or streets spaced at a predetermined distance (L) apart to allow the diffusion of metals to occur.
PCT/US1999/018085 1998-08-10 1999-08-10 Preparation of metal-precipitates permeable insulator for soi substrate WO2000010195A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU54742/99A AU5474299A (en) 1998-08-10 1999-08-10 Process for preparation of silicon on insulator substrates with improved resistance to formation of metal precipitates

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9587898P 1998-08-10 1998-08-10
US60/095,878 1998-08-10

Publications (2)

Publication Number Publication Date
WO2000010195A2 WO2000010195A2 (en) 2000-02-24
WO2000010195A3 true WO2000010195A3 (en) 2000-05-18

Family

ID=22254002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/018085 WO2000010195A2 (en) 1998-08-10 1999-08-10 Preparation of metal-precipitates permeable insulator for soi substrate

Country Status (2)

Country Link
AU (1) AU5474299A (en)
WO (1) WO2000010195A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7987716B2 (en) 2008-03-26 2011-08-02 Endevco Corporation Coupled pivoted acceleration sensors

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860697A (en) * 1981-09-30 1983-04-11 Nec Corp Forming method of silicon single crystal film
JPS60144949A (en) * 1984-01-06 1985-07-31 Nec Corp Manufacture of semiconductor device
JPH02237121A (en) * 1989-03-10 1990-09-19 Fujitsu Ltd Manufacture of semiconductor device
JPH05129309A (en) * 1991-10-31 1993-05-25 Nec Corp Pasted substrate
US5672526A (en) * 1993-12-28 1997-09-30 Nippon Steel Corporation Method of fabricating a semiconductor device using element isolation by field shield
US5753560A (en) * 1996-10-31 1998-05-19 Motorola, Inc. Method for fabricating a semiconductor device using lateral gettering
US5753353A (en) * 1994-11-07 1998-05-19 Nec Corporation Soi Substrate
US5757063A (en) * 1994-03-25 1998-05-26 Kabushiki Kaisha Toshiba Semiconductor device having an extrinsic gettering film
US5840590A (en) * 1993-12-01 1998-11-24 Sandia Corporation Impurity gettering in silicon using cavities formed by helium implantation and annealing
JPH1126735A (en) * 1997-07-04 1999-01-29 Texas Instr Japan Ltd Bonded soi wafer
US5894037A (en) * 1995-11-22 1999-04-13 Nec Corporation Silicon semiconductor substrate and method of fabricating the same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860697A (en) * 1981-09-30 1983-04-11 Nec Corp Forming method of silicon single crystal film
JPS60144949A (en) * 1984-01-06 1985-07-31 Nec Corp Manufacture of semiconductor device
JPH02237121A (en) * 1989-03-10 1990-09-19 Fujitsu Ltd Manufacture of semiconductor device
JPH05129309A (en) * 1991-10-31 1993-05-25 Nec Corp Pasted substrate
US5840590A (en) * 1993-12-01 1998-11-24 Sandia Corporation Impurity gettering in silicon using cavities formed by helium implantation and annealing
US5672526A (en) * 1993-12-28 1997-09-30 Nippon Steel Corporation Method of fabricating a semiconductor device using element isolation by field shield
US5757063A (en) * 1994-03-25 1998-05-26 Kabushiki Kaisha Toshiba Semiconductor device having an extrinsic gettering film
US5753353A (en) * 1994-11-07 1998-05-19 Nec Corporation Soi Substrate
US5894037A (en) * 1995-11-22 1999-04-13 Nec Corporation Silicon semiconductor substrate and method of fabricating the same
US5753560A (en) * 1996-10-31 1998-05-19 Motorola, Inc. Method for fabricating a semiconductor device using lateral gettering
JPH1126735A (en) * 1997-07-04 1999-01-29 Texas Instr Japan Ltd Bonded soi wafer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WOLF S.: "Silicon Processing for the VLSI Era", LATTICE PRESS, vol. 1, 1986, SUNSET BEACH, CA, pages 61 - 72, XP002925678 *

Also Published As

Publication number Publication date
AU5474299A (en) 2000-03-06
WO2000010195A2 (en) 2000-02-24

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