WO2000014792A1 - Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry - Google Patents
Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry Download PDFInfo
- Publication number
- WO2000014792A1 WO2000014792A1 PCT/US1999/019009 US9919009W WO0014792A1 WO 2000014792 A1 WO2000014792 A1 WO 2000014792A1 US 9919009 W US9919009 W US 9919009W WO 0014792 A1 WO0014792 A1 WO 0014792A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive
- forming
- line
- runner
- plug
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000003672 processing method Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000004891 communication Methods 0.000 claims abstract description 11
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims 3
- 239000012634 fragment Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry comprising such contact openings and electrical connections and interconnections Background Art
- a semiconductor wafer fragment is indicated generally at 10 and comprises a semiconductive substrate 12
- semiconductive substrate ' is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials)
- substrate refers to any suppo rting structure , including, but not limited to, the semiconductive substrates described above
- Substrate 12 comprises a field oxide region 13 having an outer surface 14 (Fig 2) over which a plurality of conductive runners or conductive lines 16, 18, and 20 are formed
- the illustrated conductive lines or runners include conductive portions and insulative portions Exemplary conductive portions are constituted, in this example , by a respective polysi con layer 22 and an overlying si cide layer 24 The insulative portions of the runners or lines are constituted by respective overlying caps 26 and associated sidewall space
- An insulative layer 30 such as borophosphosihcate glass is formed over runners 16, 18, and 20 and a contact opening 32 is formed through a masked etch of layer 30 to outwardly expose a portion of sihcide layer 24 Thereafter, conductive material such as conductively doped polysihcon is formed within contact opening 32 to provide a conductive contact 34 to conductive line 18 A metal layer 36 is provided thereover to form an electrical connection with conductive line 18 A typical practice within the semiconductor industry is to provide a conductive line or runner with a widened landing pad in order to accommodate mask misalignments when contact openings are formed. An exemplary widened landing pad is shown in Figs. 1 and 2 at 38.
- contact opening 32 can shift left or right some distance relative to the position shown in Figs. 1 and 2 without making undesirable contact with the substrate .
- landing pad 38 includes the conductive and insulative portions of conductive line 18; and the conductive portions of conductive line 18 define a contact pad with which electrical communication is desired.
- a contact pad is defined by polysihcon layer 22 and suicide layer 24 of conductive line 18.
- the contact pad defines a target area A inside of which it is desirable to form a contact opening.
- An electrical connection through contact opening 32 can be formed anywhere within target area A and still effectively make a desirable connection with the conductive contact pad.
- the target area tolerates a contact opening mask misalignment on either side of the illustrated and desired contact opening 32.
- a tradeoff for improved mask misalignment tolerance is a reduction in wafer real estate available for supporting conductive lines and other integrated circuitry components. This is due largely in part to the increased area which is occupied by the widened landing pad 38. This also adversely impacts the conductive line spacing such that desired minimum spacing adjacent conductive lines is not achieved. Hence , integrated circuitry cannot be packed as densely upon a wafer as is desirable when the widened landing pads are used.
- Fig. 1 is a top plan view of a prior art semiconductor wafer fragment and a plurality of conductive lines supported thereon.
- Fig. 2 is a view which is taken along line 2-2 in Fig. 1 at a subsequent processing step .
- Fig. 3 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with one implementation of the invention.
- Fig. 4 is a view of the Fig. 3 wafer fragment at another processing step .
- Fig. 5 is a view of the Fig. 3 wafer fragment at another processing step .
- Fig. 6 is a view of the Fig. 3 wafer fragment at another processing step.
- Fig. 7 is a view which is similar to the Fig. 6 view, but which shows an alternate embodiment in accordance with another implementation of the invention.
- Fig. 8 is a view of the Fig. 3 wafer fragment at another processing step.
- Figs. 9 and 10 are top plan views of semiconductor wafer fragments which have been processed in accordance with the inventive methodologies. Best Modes for Carrying Out the Invention and Disclosure of Invention
- a plurality of conductive runners or lines 16a, 18a, and 20a are formed over outer surface 14, and can be formed over oxide isolation regions 40.
- Exemplary isolation regions include shallow trench isolation regions or field oxide regions formed through LOCOS techniques.
- the conductive lines comprise respective outermost surfaces 44 portions of which define respective conductive line heights h outwardly of outer surface 14.
- Diffusion regions 42 can be provided between the conductive lines, and preferably comprise n- regions having doping concentrations of 1 x 10 cm .
- the diffusion regions can be provided in a separate doping step, or through outdiffusion of dopant from conductive material which will become more apparent below.
- An outer contact opening target area B is defined by conductive line
- an insulating material layer 46 is formed over substrate 12.
- An exemplary material is borophosphosilicate glass.
- At least one, and preferably a pair of contact openings 48, 50 are formed through layer 46 and preferably outwardly expose respective portions of outer surface 14.
- the contact openings can be formed through a suitable masked etch of layer 46.
- the individual contact openings are essentially self-aligned at and to the substrate at two locations 48a, 48b, and 50a, 50b respectively, along a line extending laterally from conductive runner or line 18a.
- one of the two locations for the individual contact openings is defined by conductive runner 18a. Even more preferably, the other of the two respective locations are defined by respective next adjacent conductive lines 16a, 20a.
- first conductive material 52, 54 is formed within contact openings 48, 50, between the illustrated conductive lines and laterally proximate or adjacent the contact pad defined by conductive line 18a.
- An exemplary and preferred first conductive material is conductively doped polysihcon, which can serve as a source of outdiffused dopant for regions 42.
- the polysihcon can be chemical vapor deposited over the substrate and subsequently removed through conventional processing to provide conductive plugs 56, 58.
- Such conventional processing can include planarization processing to isolate conductive material within the respective contact openings, followed by a suitable timed etch to recess the conductive material within the contact openings.
- conductive plugs are formed on both sides of conductive line 18a. It is possible, however, for only one conductive plug to be formed on either side of conductive line 18a.
- the individual conductive plugs are essentially self-aligned at and to the substrate at the same locations as are the contact openings in which each is formed.
- the illustrated conductive plugs are formed to preferably extend outwardly from outer surface 14 a distance which is greater than conductive runner height h. Because the plugs in this example are formed atop the same surface (outer surface 14) atop which the conductive lines are formed, each extends elevationally beyond the respective conductive line heights. Such plugs could, however, be formed to extend from outer surface 14 a distance which is less than or no further than the conductive runner height. This could, for example, be done by conducting a timed etch for a longer period of time than is suitable for forming the illustrated Fig. 6 plugs. An exemplary construction is shown in Fig. 7.
- individual conductive plugs include portions which overlap with portions of conductive line 18a and the respective next adjacent conductive lines 16a, 20a.
- the respective plugs overlap with the outermost surfaces of the conductive lines adjacent which each is formed. Accordingly, portions of at least one, and preferably both conductive plugs can overlap target area B .
- the conductive material of conductive plugs 56, 58, and the conductive material of conductive line 18a define an effective contact pad having an outermost surface 60, which defines an effectively widened target area A'. The widened target area reduces the wafer area which was formerly required by the prior art widened landing pad (Figs. 1 and 2) described above.
- effective contact pad outermost surface 60 defines a generally non-planar surface .
- at least one of the conductive plugs, and preferably both, define a region of outermost surface 60 having a higher topographical elevation than the region defined by the contact
- a layer 62 of insulative material is formed over the substrate and the effective contact pad A contact opening 64 is etched or otherwise formed through layer 62 to outwardly expose portions of the effective contact pad
- the contact pad of line 18a is exposed, with any mask misalignment resulting in exposure of conductive material of either or both of conductive plugs 56, 58
- a second conductive material 66 is formed within contact opening 64 and in electrical communication with at least portions of the contact pad and, if exposed, an associated portion of a conductive plug
- a bit line 68 can then be formed over the substrate and m electrical communication with material 66
- conductive lines 16a, 18a and 20a have first respective line widths W
- the second line width corresponds to a line location where at least a portion of contact opening 64 is formed
- the first and second line widths are essentially the same or equivalent This is made possible because the above-described conductive plugs 56, 58 (shown in dashed lines in Figs 9 and 10) reduce , if not eliminate , the requirement of the Fig 1 widened landing pad
- the illustrated conductive plugs provide an effective contact pad width which is greater than second line width w 2 , and include respective portions proximate the first line width W
- the plugs can also include portions which overlap with corresponding portions of conductive lines 16a, 20a This compensates for a contact opening mask misalignment by enabling desired contact
- first and second line widths w, , w 7 respectively are different with second line width w 2 being greater than first line width w,
- the second line width defines a portion of a landing pad which is smaller in dimension than the Fig 1 landing pad
- Portions of conductive lines 16b and 20b laterally proximate respective conductive plugs 56, 58 can be tapered or otherwise configured to accommodate the somewhat wider landing pad
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000569439A JP3703081B2 (en) | 1998-09-03 | 1999-08-17 | Semiconductor processing method, method of forming contact opening, and integrated circuit |
AU56824/99A AU5682499A (en) | 1998-09-03 | 1999-08-17 | Semiconductor processing methods of forming contact openings, methods of formingelectrical connections and interconnections, and integrated circuitry |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/146,840 | 1998-09-03 | ||
US09/146,840 US6242302B1 (en) | 1998-09-03 | 1998-09-03 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000014792A1 true WO2000014792A1 (en) | 2000-03-16 |
Family
ID=22519198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/019009 WO2000014792A1 (en) | 1998-09-03 | 1999-08-17 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
Country Status (6)
Country | Link |
---|---|
US (9) | US6242302B1 (en) |
JP (1) | JP3703081B2 (en) |
KR (1) | KR100417891B1 (en) |
AU (1) | AU5682499A (en) |
TW (1) | TW429580B (en) |
WO (1) | WO2000014792A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016003595A1 (en) * | 2014-07-01 | 2016-01-07 | Qualcomm Incorporated | Self-aligned via for gate contact of semiconductor devices |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242302B1 (en) * | 1998-09-03 | 2001-06-05 | Micron Technology, Inc. | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
US6713378B2 (en) * | 2000-06-16 | 2004-03-30 | Micron Technology, Inc. | Interconnect line selectively isolated from an underlying contact plug |
US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
KR100408414B1 (en) * | 2001-06-20 | 2003-12-06 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US6784076B2 (en) * | 2002-04-08 | 2004-08-31 | Micron Technology, Inc. | Process for making a silicon-on-insulator ledge by implanting ions from silicon source |
KR100445638B1 (en) * | 2002-07-26 | 2004-08-25 | 삼성전자주식회사 | Interconnection structure connecting electrically isolated regions and method of fabricatinging the same |
US6831006B2 (en) * | 2003-01-15 | 2004-12-14 | International Business Machines Corporation | Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner |
US7126200B2 (en) * | 2003-02-18 | 2006-10-24 | Micron Technology, Inc. | Integrated circuits with contemporaneously formed array electrodes and logic interconnects |
KR100933147B1 (en) * | 2003-08-07 | 2009-12-21 | 삼성전자주식회사 | Apparatus and method for receiving signal in mobile communication system using adaptive antenna array method |
US20060228862A1 (en) * | 2005-04-06 | 2006-10-12 | International Business Machines Corporation | Fet design with long gate and dense pitch |
US7528065B2 (en) * | 2006-01-17 | 2009-05-05 | International Business Machines Corporation | Structure and method for MOSFET gate electrode landing pad |
US9379058B2 (en) | 2014-02-14 | 2016-06-28 | Qualcomm Incorporated | Grounding dummy gate in scaled layout design |
US9277122B1 (en) * | 2015-08-13 | 2016-03-01 | Legend3D, Inc. | System and method for removing camera rotation from a panoramic video |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5100838A (en) * | 1990-10-04 | 1992-03-31 | Micron Technology, Inc. | Method for forming self-aligned conducting pillars in an (IC) fabrication process |
US5229326A (en) * | 1992-06-23 | 1993-07-20 | Micron Technology, Inc. | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device |
EP0587399A2 (en) * | 1992-09-11 | 1994-03-16 | STMicroelectronics Limited | Semiconductor device incorporating a contact and manufacture thereof |
EP0599592A1 (en) * | 1992-11-25 | 1994-06-01 | STMicroelectronics, Inc. | Self-aligned via |
US5350712A (en) * | 1992-09-18 | 1994-09-27 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor IC device having multilayer interconnection structure |
US5700706A (en) * | 1995-12-15 | 1997-12-23 | Micron Technology, Inc. | Self-aligned isolated polysilicon plugged contacts |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4024626A (en) | 1974-12-09 | 1977-05-24 | Hughes Aircraft Company | Method of making integrated transistor matrix for flat panel liquid crystal display |
US4700473A (en) * | 1986-01-03 | 1987-10-20 | Motorola Inc. | Method of making an ultra high density pad array chip carrier |
US4700276A (en) * | 1986-01-03 | 1987-10-13 | Motorola Inc. | Ultra high density pad array chip carrier |
US5187604A (en) * | 1989-01-18 | 1993-02-16 | Hitachi, Ltd. | Multi-layer external terminals of liquid crystal displays with thin-film transistors |
US5219793A (en) | 1991-06-03 | 1993-06-15 | Motorola Inc. | Method for forming pitch independent contacts and a semiconductor device having the same |
US5208170A (en) * | 1991-09-18 | 1993-05-04 | International Business Machines Corporation | Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnect and via landing |
US5278438A (en) | 1991-12-19 | 1994-01-11 | North American Philips Corporation | Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure |
US5633201A (en) | 1992-11-30 | 1997-05-27 | Hyundai Electronics Industries, Co., Ltd. | Method for forming tungsten plugs in contact holes of a semiconductor device |
US6004361A (en) | 1993-03-05 | 1999-12-21 | Mobil Oil Corporation | Low emissions diesel fuel |
KR0123751B1 (en) * | 1993-10-07 | 1997-11-25 | 김광호 | Semiconductor device and the fabricating method thereof |
KR0135803B1 (en) * | 1994-05-13 | 1998-04-24 | 김광호 | Semiconductor memory device and manufacture therefor |
GB9416899D0 (en) * | 1994-08-20 | 1994-10-12 | Philips Electronics Uk Ltd | Manufacture of electronic devices comprising thin-film circuitry |
US5506450A (en) * | 1995-05-04 | 1996-04-09 | Motorola, Inc. | Semiconductor device with improved electromigration resistance and method for making the same |
US5661054A (en) * | 1995-05-19 | 1997-08-26 | Micron Technology, Inc. | Method of forming a non-volatile memory array |
US5654589A (en) | 1995-06-06 | 1997-08-05 | Advanced Micro Devices, Incorporated | Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application |
JP3124913B2 (en) * | 1995-08-08 | 2001-01-15 | 信越化学工業株式会社 | Purification method of fluorinated polyether having vinyl-containing acid amide group at terminal |
WO1997014185A1 (en) | 1995-10-11 | 1997-04-17 | Paradigm Technology, Inc. | Semiconductor device with a planarized interconnect with poly-plug and self-aligned contacts |
US5700731A (en) | 1995-12-07 | 1997-12-23 | Vanguard International Semiconductor Corporation | Method for manufacturing crown-shaped storage capacitors on dynamic random access memory cells |
US6110798A (en) * | 1996-01-05 | 2000-08-29 | Micron Technology, Inc. | Method of fabricating an isolation structure on a semiconductor substrate |
JPH1048610A (en) * | 1996-07-31 | 1998-02-20 | Furontetsuku:Kk | Liquid crystal display element |
EP0847081A1 (en) * | 1996-12-09 | 1998-06-10 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
US5872056A (en) * | 1997-02-07 | 1999-02-16 | Micron Technology, Inc. | Semiconductor processing methods of forming self-aligned contact openings |
JPH10242422A (en) * | 1997-02-28 | 1998-09-11 | Toshiba Corp | Semiconductor storage device and its manufacture |
US6157430A (en) | 1997-03-24 | 2000-12-05 | Mitsubishi Denki Kabushiki Kaisha | Active matrix liquid crystal device including brush-clearable multiple layer electrodes and a method of manufacturing the same |
JPH118379A (en) | 1997-06-16 | 1999-01-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
US6159788A (en) * | 1997-11-21 | 2000-12-12 | United Microelectronics Corp. | Method to increase DRAM cell capacitance |
US5972758A (en) * | 1997-12-04 | 1999-10-26 | Intel Corporation | Pedestal isolated junction structure and method of manufacture |
US6004861A (en) * | 1997-12-19 | 1999-12-21 | Advanced Micro Devices | Process for making a discontinuous source/drain formation for a high density integrated circuit |
TW368731B (en) | 1997-12-22 | 1999-09-01 | United Microelectronics Corp | Manufacturing method for self-aligned local-interconnect and contact |
US5879986A (en) * | 1998-02-27 | 1999-03-09 | Vangaurd International Semiconductor Corporation | Method for fabrication of a one gigabit capacitor over bit line DRAM cell with an area equal to eight times the used minimum feature |
US6080620A (en) * | 1998-06-03 | 2000-06-27 | Vanguard International Semiconductor Corporation | Method for fabricating interconnection and capacitors of a DRAM using a simple geometry active area, self-aligned etching, and polysilicon plugs |
US6033962A (en) | 1998-07-24 | 2000-03-07 | Vanguard International Semiconductor Corporation | Method of fabricating sidewall spacers for a self-aligned contact hole |
US6242302B1 (en) * | 1998-09-03 | 2001-06-05 | Micron Technology, Inc. | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry |
-
1998
- 1998-09-03 US US09/146,840 patent/US6242302B1/en not_active Expired - Lifetime
-
1999
- 1999-08-17 WO PCT/US1999/019009 patent/WO2000014792A1/en active IP Right Grant
- 1999-08-17 JP JP2000569439A patent/JP3703081B2/en not_active Expired - Lifetime
- 1999-08-17 KR KR10-2001-7002808A patent/KR100417891B1/en not_active IP Right Cessation
- 1999-08-17 AU AU56824/99A patent/AU5682499A/en not_active Abandoned
- 1999-10-22 TW TW088115108A patent/TW429580B/en not_active IP Right Cessation
-
2000
- 2000-05-04 US US09/565,196 patent/US6323087B1/en not_active Expired - Fee Related
- 2000-05-04 US US09/565,197 patent/US6476490B1/en not_active Expired - Lifetime
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2001
- 2001-03-14 US US09/808,886 patent/US6468883B2/en not_active Expired - Lifetime
- 2001-09-18 US US09/956,274 patent/US6753241B2/en not_active Expired - Fee Related
-
2002
- 2002-09-12 US US10/244,122 patent/US6855628B2/en not_active Expired - Lifetime
- 2002-10-09 US US10/268,737 patent/US7291917B2/en not_active Expired - Fee Related
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2005
- 2005-09-01 US US11/218,004 patent/US20060014379A1/en not_active Abandoned
-
2006
- 2006-07-31 US US11/496,843 patent/US20060273459A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5100838A (en) * | 1990-10-04 | 1992-03-31 | Micron Technology, Inc. | Method for forming self-aligned conducting pillars in an (IC) fabrication process |
US5229326A (en) * | 1992-06-23 | 1993-07-20 | Micron Technology, Inc. | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device |
EP0587399A2 (en) * | 1992-09-11 | 1994-03-16 | STMicroelectronics Limited | Semiconductor device incorporating a contact and manufacture thereof |
US5350712A (en) * | 1992-09-18 | 1994-09-27 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor IC device having multilayer interconnection structure |
EP0599592A1 (en) * | 1992-11-25 | 1994-06-01 | STMicroelectronics, Inc. | Self-aligned via |
US5700706A (en) * | 1995-12-15 | 1997-12-23 | Micron Technology, Inc. | Self-aligned isolated polysilicon plugged contacts |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016003595A1 (en) * | 2014-07-01 | 2016-01-07 | Qualcomm Incorporated | Self-aligned via for gate contact of semiconductor devices |
Also Published As
Publication number | Publication date |
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US6323087B1 (en) | 2001-11-27 |
US6242302B1 (en) | 2001-06-05 |
US20030054621A1 (en) | 2003-03-20 |
US6476490B1 (en) | 2002-11-05 |
US20030089989A1 (en) | 2003-05-15 |
US20010010969A1 (en) | 2001-08-02 |
US6855628B2 (en) | 2005-02-15 |
US20020013047A1 (en) | 2002-01-31 |
KR100417891B1 (en) | 2004-02-11 |
AU5682499A (en) | 2000-03-27 |
KR20010073109A (en) | 2001-07-31 |
TW429580B (en) | 2001-04-11 |
JP2002524875A (en) | 2002-08-06 |
JP3703081B2 (en) | 2005-10-05 |
US7291917B2 (en) | 2007-11-06 |
US6753241B2 (en) | 2004-06-22 |
US6468883B2 (en) | 2002-10-22 |
US20060273459A1 (en) | 2006-12-07 |
US20060014379A1 (en) | 2006-01-19 |
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