WO2000014892B1 - Spread-spectrum continuous-time analog correlator and method therefor - Google Patents

Spread-spectrum continuous-time analog correlator and method therefor

Info

Publication number
WO2000014892B1
WO2000014892B1 PCT/US1999/020525 US9920525W WO0014892B1 WO 2000014892 B1 WO2000014892 B1 WO 2000014892B1 US 9920525 W US9920525 W US 9920525W WO 0014892 B1 WO0014892 B1 WO 0014892B1
Authority
WO
WIPO (PCT)
Prior art keywords
correlator
input signal
multiplier
output
signal
Prior art date
Application number
PCT/US1999/020525
Other languages
French (fr)
Other versions
WO2000014892A1 (en
Inventor
Gregory T Uehara
Original Assignee
Univ Hawaii
Gregory T Uehara
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Hawaii, Gregory T Uehara filed Critical Univ Hawaii
Priority to AU63847/99A priority Critical patent/AU6384799A/en
Publication of WO2000014892A1 publication Critical patent/WO2000014892A1/en
Publication of WO2000014892B1 publication Critical patent/WO2000014892B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/709—Correlator structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers

Abstract

The present invention is a correlator for use in spread spectrum applications which utilizes continuous-time analog domain signal processing. The correlator includes a multiplier (260) which is coupled to an integration capacitance (315), and an integration reset circuit (354) which is coupled to the integration capacitance (315). The correlator is designed to receive a first input signal (120) and a second input signal (125). The multiplier (260) multiplies the first input signal (120) and the second input signal (125) to produce a multiplier output current (310a, 310b). The multiplier output current is then integrated by the integration capacitance (315) which produces a correlator output voltage (330). The integration reset circuit (354) then resets the integration capacitance (315) to a reset voltage.

Claims

AMENDED CLAIMS[received by the International Bureau on 31 March 2000 (31.03.00); original claims 1-12, 16, 18, 22, 23, 27-35, 37, 40-42 and 45-47 amended; remaining claims unchanged (10 pages)]
1. A correlator for analog domain signal processing, comprising: an integrated circuit correlator having a first input signal and a second input signal, a multiplier coupled with an integration and dump circuit; the multiplier multiplies the first input signal and the second input signal producing a multiplier output; and the multiplier output is integrated by the integrate and dump circuit producing a correlator output.
2. The correlator as claimed in claim 1, further comprising: a reset circuit coupled with the integrate and dump circuit; and the integration reset circuit resets the integrate and dump circuit.
3. The correlator as claimed in claim 2, wherein: the multiplier output is a current.
4. The correlator as claimed in claim 3, wherein: the integrate and dump circuit includes integration capacitance.
5. The correlator as claimed in claim 1, wherein: the integrate and dump circuit is coupled with the multiplier through a current coupling circuit.
6. The correlator as claimed in claim 5, wherein: the second input signal is generated from a level translator coupled with the multiplier to provide the second input signal to the multiplier.
7. A correlator for spread spectrum applications utilizing continuous-time analog domain signal processing, comprising: a correlator receiving a first input signal and a second input signal; the correlator comprising a multiplier coupled with an integration capacitance and an integration reset circuit coupled with the integration capacitance; the multiplier multiplies the first input signal and the second input signal producing a multiplier output current; the multiplier output current is integrated by the integration capacitance producing a correlator output voltage; and the integration reset circuit resets the integration capacitance to a reset voltage.
8. The correlator as claimed in claim 7, further comprising: a current coupling circuit; and the integration capacitance is coupled with the multiplier through the current coupling circuit configured to forward at least a portion of the multiplier output current to the integration capacitance.
9. The correlator as claimed in claim 7, wherein: the second input signal is generated from a pseudorandom noise (PN) code generator coupled with a PN code level translator which couples with the multiplier such that the PN code level translator translates an output from the PN code generator to provide the second input signal to the multiplier as a binary signal.
10. A correlator for use in continuous-time analog spread spectrum applications, comprising: a correlator having a first input signal and a second input signal; the correlator comprising a multiplier, a current coupling circuit, an integration capacitance and an integration reset circuit; the multiplier is coupled with the current coupling circuit, the current coupling circuit is further coupled with the integration capacitance, such that the multiplier multiplies the first input signal and the second input signal producing a multiplier output current; at least a portion of the multiplier output current is coupled through the current coupling circuit to the integration capacitance to be integrated by the integration capacitance producing a correlator output voltage; and the integration reset circuit is coupled with the integration capacitance and periodically resets the integration capacitance.
11. The correlator as claimed in claim 10, wherein: the second input signal is a binary pseudorandom noise (PN) code signal.
12. The correlator as claimed in claim 11, further comprising: a PN code level translator coupled with the multiplier; and the PN code level translator generates the binary PN code signal as the second input to the multiplier.
13. The correlator as claimed in claim 12, wherein: the PN code level translator having a translation circuit such that the translation circuit consumes substantially zero DC power.
14. The correlator as claimed in claim 12, wherein: the PN code level translator includes a plurality of control switches to generate the second input signal.
15. The correlator as claimed in claim 14, wherein: the PN code level translator having two separately generated bias voltages; and the plurality of switches having a first state and a second state, wherein each switch couples to one of the two bias voltages when in the first state.
16. The correlator as claimed in claim 12, wherein: the PN code level translator includes PN code translator logic which controls a plurality of control switches, the control switches generate the binary PN code signal.
17. The correlator as claimed in claim 10, wherein: the correlator is configured in a fully-differential architecture.
18. The correlator as claimed in claim 10, wherein: the integration capacitance includes a first integration capacitance and a second integration capacitance producing a differential correlator voltage output.
19. The correlator as claimed in claim 10, wherein: the correlator is configured in a telescopic architecture.
20. The correlator as claimed in claim 10, wherein: the correlator is configured in a folded-cascode architecture.
21. The correlator as claimed in claim 10, wherein: the first input signal is in an analog domain.
22. The correlator as claimed in claim 10, wherein: the first input signal having a series of binary data bits; and the integration capacitance is reset once per data bit following an end of a data bit correlation.
23. The correlator as claimed in claim 10, wherein: the correlator output is coupled to a sample block which samples the correlator output producing a sampled output; and the sample block is coupled to an accumulator which sums the sampled output producing a composite correlator output.
24. The correlator as claimed in claim 10, wherein: the multiplier is a Gilbert Multiplier.
25. The correlator as claimed in claim 24, wherein: the Gilbert multiplier includes a first upper transistor pair and a second upper transistor pair and a lower transistor pair; and the lower transistor pair includes a plurality of degeneration resistors.
26. The correlator as claimed in claim 10, wherein: the first input signal is an arbitrary shape signal; and the second input signal is a binary sequence signal. - -
27. A communication channel receiver for baseband signal processing, comprising: a multiplier coupled to an integrate-and-dump circuit; the multiplier receives a first input signal and a second input signal such that the multiplier multiplies the first input signal and the second input signal and produces a multiplier output; and the multiplier output is integrated by the integrate-and-dump circuit which produces a correlator output proportional to the product of the first input signal and the second input signal;
28. The communication channel receiver as claimed in claim 27, wherein: the second input is a binary pseudorandom noise (PN) code.
29. The communication channel receiver as claimed in claim 28, further comprising: a PN code level translator coupled with the multiplier such that the PN code level translator generates the second input signal inputted into the multiplier to be multiplied with the first input signal.
30. The communication channel receiver as claimed in claim 27, wherein: the communication channel receiver is configured in a fully-differential architecture.
31. The communication channel receiver of claim 30, wherein: the integrate-and-dump includes at least one integration capacitance coupled with a integration reset circuit; the multiplier output is integrated by the integration capacitance; and the integration reset circuit resets the integration capacitance to allow the integration capacitance to again integrate the multiplier output.
32. The communication channel receiver as claimed in claim 31 , wherein: - -
the integrate-and-dump includes a sampling circuit which is coupled with the integration capacitance; and the sampling circuit samples the integration capacitance prior to the integration capacitance being reset by the integration reset circuit.
33. The communication channel receiver as claimed in claim 32, wherein: the multiplier output is a current which is integrated by the integration capacitance.
34. The cornmunication channel receiver as claimed in claim 27, wherein: the integrate-and-dump circuit includes an integration capacitance such that the multiplier output is integrated by the integration capacitance.
35. The communication channel receiver as claimed in claim 33, wherein: the communication channel receiver including the integration capacitance is formed on a single IC die.
36. A communication channel receiver, comprising: a correlator having two inputs, a receive baseband input signal and a receive PN code signal and generating a continuous time correlator output voltage proportional to the product of the receive baseband signal and the PN code signal; the correlator is coupled to an analog to digital converter which converts the correlator output voltage to a digital signal; the analog to digital converter is coupled to a decision device and a synchronization circuit such that the digital signal is directed to both; the decision device generates output bits; the synchronization circuit generates a control signal; the synchronization circuit is coupled to a controlled oscillator which receives the control signal and generates a clock signal; the controlled oscillator is coupled to a receive PN code generator which receives the clock signal which produces a PN code generator output; and -40-
the PN code generator is coupled to a PN code level translator which receives the PN code generator output and produces the receive PN code signal which is inputted into the correlator.
37. A method for correlating two signals utilizing a continuous-time signal analog implementation, comprising: multiplying a first input signal with a second input signal producing a multiplier output current; coupling the multiplier output current through a current coupling circuit to an integration capacitance; integrating the multiplier output current using the integration capacitance generating a correlator output voltage across the integration capacitance; and periodically reinitializing the integration capacitance.
38. The method of correlating two signals as claimed in claim 37, wherein: integrating the multiplier output current by the integration capacitance for a correlator correlation period; sampling the correlator output voltage at least once during each correlator correlation period producing a correlator output sample; reinitializing the integration capacitance once every correlator correlation period; and accumulating the correlator output sample over the duration of a data bit period.
39. The method of correlating two signals as claimed in claim 38, wherein: the data bit period exceeds the correlator correlation period.
40. The method of correlating two signals as claimed in claim 38, further comprising: sampling the correlator output voltage; generating a sample output signal; converting the sample output signal from an analog domain to a digital domain, producing a digital representation of the correlator output signal; and -41-
looping the digital representation of the correlator output signal through a synchronization loop generating the second input signal, to be multiplied with the first input signal.
41. The method of correlating two signals as claimed in claim 40, further comprising: translating a signal from the synchronization loop using at least two reference voltages generating the second input signal.
42. The method of correlating two signals as claimed in claim 37, further comprising: generating the second input signal from a PN code level translator.
43. The method of correlating two signals as claimed in claim 37, wherein: correlating the first input signal with the second input signal for a finite duration.
44. The method of correlating two signals as claimed in claim 37, wherein: correlating the first input signal with the second input signal periodically.
45. A method of correlating a communication signal for use in a communication channel receiver, comprising: continuously converting an analog first input signal from a voltage to a current including: multiplying the first input signal with a second input signal producing the current; integrating the current by an integrate-and-dump circuit generating an output voltage thus effecting correlation; periodically resetting the integrate-and-dump circuit to a reference voltage; and looping the output voltage back to provide the second input signal including translating the output voltage to a binary signal.
46. The method of correlating a communication signal as claimed in claim 45, wherein: multiplying the first input signal with the second input signal through a switch matrix. - -
47. A method of performing a finite duration correlation of a first input signal and a second input signal, the first input signal having an arbitrary shape, the second input signal having binary levels, comprising: multiplying the first input signal with the second input signal through a network of switches producing an output; coupling at least a portion of the output to an integration capacitance; integrating the output through the integration capacitance generating a correlator output; and periodically resetting the integration capacitance.
48. The method of performing a finite duration correlation as claimed in claim 47, wherein: converting the first input signal to a current domain prior to multiplying the first input signal with the second input signal.
49. A correlator for spread spectrum applications utilizing analog domain signal processing, comprising: a means for multiplying a first input signal and a second input signal to generate a multiplied output current; and a means for coupling the multiplied output current to an integration means; the integration means for integrating the multiplied output current producing a correlated output voltage.
50. A code level translator for translating a binary signal, comprising: a logic block receiving an input signal; and the logic block controls a plurality of switches; the plurality of switches coupling to at least one reference voltage such that when the switch is in a first state, an output proportional to the reference voltage is generated.
51. A code level translator for use in the correlation of a binary signal, comprising: an input signal is coupled to a PN code level translator logic block; - -
the PN code level translator logic block is coupled to a plurality of switches; the plurality of switches having a first state and a second state; the PN code level translator generating switch control signals to control the plurality of switches to shift between the first state and the second state; and the plurality of switches coupling to a reference voltage in the first state generating an output voltage.
-44-
STATEMENT UNDER ARTICLE 19
Applicant submits that the claimed invention is novel and has the requisite inventive step over the cited art.
Applicant notes that Jerrim (US4567588) does not disclose or suggest the use of an integrated circuit correlator. Nor does the Jerrim reference suggest a correlator with a reset circuit, integration capacitance, a PN code level translator, a synchronization loop. The
Jerrim reference fails to disclose any details regarding the implementation of the integrator or integrate and dump shown in FIGS.7 and 11. The Jerrim reference also failed to disclose or suggest the use of differential circuit design. The Jerrim reference further describes the use of three input signals. The Jerrim reference does not disclose the implementation of a correlator for correlating an information signal applying two input signals into the correlator.
The Jerrim reference does discuss the multiplication of three signals and the integration of the products, without any further details, but does not have the structure or function recited in Applicant's amended claims.
Magill (US 5574721) describes a communication system which implements a multiplier and an integration, but fails to the structure or function recited in Applicant's amended claims. Magill also fails to disclose any implementation of the multiplier, the integrator, and accumulation and dump. The Magill reference does not disclose an integrated circuit correlator. Magill makes no reference to the implementation of a differential circuit. The Magill reference does not disclose or suggest a PN code level translator, current coupling circuit, a reset circuit, integration capacitance and many other elements and structure of the claimed invention.
Jehnert (US5822423) teaches a data reporting system or alarm systm which includes a multiplier and integrate and dump filter but fails to provide any implementation of these components. Jehnert does not disclose a correlator nor an integrated circuit correlator. The Jehnert reference does not teach the use of a PN code level translator, a differential architecture, a synchronization loop, reset circuit, current coupling circuit or integration capacitance, just to list some of the elements and structure of the claimed invention. In order to determine whether an invention was easy to invent, one must assess the skill of a practitioner in the art and the state of the prior-art at the time the invention was made. In the instant case, it appears that the hindsight of the knowledge of the invention may have been used to hunt for references that disclose certain features generally similar to those of the claimed invention. Hindsight cannot serve as the basis for defeating novelty or inventive step. Applicant therefore submits that the amended and substituted claims are novel and have the requisite inventive step over the cited art.
PCT/US1999/020525 1998-09-08 1999-09-07 Spread-spectrum continuous-time analog correlator and method therefor WO2000014892A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU63847/99A AU6384799A (en) 1998-09-08 1999-09-07 Spread-spectrum continuous-time analog correlator and method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9950798P 1998-09-08 1998-09-08
US60/099,507 1998-09-08

Publications (2)

Publication Number Publication Date
WO2000014892A1 WO2000014892A1 (en) 2000-03-16
WO2000014892B1 true WO2000014892B1 (en) 2000-05-18

Family

ID=22275335

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/020525 WO2000014892A1 (en) 1998-09-08 1999-09-07 Spread-spectrum continuous-time analog correlator and method therefor

Country Status (3)

Country Link
US (1) US6330274B1 (en)
AU (1) AU6384799A (en)
WO (1) WO2000014892A1 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6493404B1 (en) 1999-03-01 2002-12-10 Sharp Kabushiki Kaisha Recycling integrator correlator
TW483255B (en) * 1999-11-26 2002-04-11 Fujitsu Ltd Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
US7339526B2 (en) 2004-07-30 2008-03-04 Novariant, Inc. Synchronizing ranging signals in an asynchronous ranging or position system
US7532160B1 (en) 2004-07-30 2009-05-12 Novariant, Inc. Distributed radio frequency ranging signal receiver for navigation or position determination
US7339525B2 (en) 2004-07-30 2008-03-04 Novariant, Inc. Land-based local ranging signal methods and systems
US7342538B2 (en) 2004-07-30 2008-03-11 Novariant, Inc. Asynchronous local position determination system and method
US7205939B2 (en) 2004-07-30 2007-04-17 Novariant, Inc. Land-based transmitter position determination
US7339524B2 (en) * 2004-07-30 2008-03-04 Novariant, Inc. Analog decorrelation of ranging signals
US7271766B2 (en) 2004-07-30 2007-09-18 Novariant, Inc. Satellite and local system position determination
US7315278B1 (en) 2004-07-30 2008-01-01 Novariant, Inc. Multiple frequency antenna structures and methods for receiving navigation or ranging signals
US7428259B2 (en) * 2005-05-06 2008-09-23 Sirf Technology Holdings, Inc. Efficient and flexible GPS receiver baseband architecture
US20070149113A1 (en) * 2005-12-28 2007-06-28 Fitzrandolph David K Signal presence detection
US7746274B2 (en) * 2006-06-20 2010-06-29 Atheros Communications, Inc. Global positioning receiver with PN code output
US7782252B2 (en) * 2007-06-02 2010-08-24 Inchul Kang System and method for GPS signal acquisition
US8049665B1 (en) 2007-06-02 2011-11-01 Inchul Kang System and method for selecting a local C/A code for GPS signal processing
WO2010046957A1 (en) * 2008-10-24 2010-04-29 株式会社アドバンテスト Orthogonal amplitude demodulator, demodulation method, semiconductor device using them, and test device
US8232831B2 (en) * 2009-11-24 2012-07-31 Bae Systems Information And Electronic Systems Integration Inc. Multiple input/gain stage Gilbert cell mixers
US8638888B2 (en) * 2011-07-21 2014-01-28 Infineon Technologies Ag Analog correlation technique for ultra low power receivers
US9048937B2 (en) 2011-07-28 2015-06-02 Elmos Semiconductor Ag Method for operating a UWB device
DE102012019342A1 (en) 2012-10-03 2014-04-03 Johann Christoph Scheytt Mixed-signal PSSS receiver
US10084983B2 (en) * 2014-04-29 2018-09-25 Fermi Research Alliance, Llc Wafer-scale pixelated detector system
GB201500723D0 (en) * 2015-01-16 2015-03-04 Secr Defence A method of satellite positioning and a satellite positioning receiver
CN110081991B (en) * 2019-05-05 2021-02-09 聚辰半导体股份有限公司 Decimal signal amplifying device and method for temperature sensor

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2461411B1 (en) 1979-07-13 1985-10-31 Trt Telecom Radio Electr DATA TRANSMISSION SYSTEM USING SPECTRUM SPREADING PRINCIPLES
US4400790A (en) 1981-01-06 1983-08-23 E-Systems, Inc. Transversal correlator
US4475208A (en) * 1982-01-18 1984-10-02 Ricketts James A Wired spread spectrum data communication system
US4567588A (en) 1984-03-23 1986-01-28 Sangamo Weston, Inc. Synchronization system for use in direct sequence spread spectrum signal receiver
JPS6484933A (en) * 1987-09-26 1989-03-30 Kenwood Corp Receiver
US5146471A (en) 1989-03-23 1992-09-08 Echelon Systems Corporation Correlator for spread spectrum communications systems
JP2720076B2 (en) * 1989-07-17 1998-02-25 京セラ株式会社 Automatic calibration device for direct spread spectrum receiver
CH679718A5 (en) 1989-10-19 1992-03-31 Ascom Zelcom Ag
GB9027716D0 (en) * 1990-12-20 1991-02-13 British Telecomm Optical communications system
US5175557A (en) * 1991-07-18 1992-12-29 Motorola, Inc. Two channel global positioning system receiver
US5388126A (en) 1992-12-21 1995-02-07 Rypinski; Chandos A. Baseband signal processor for a microwave radio receiver
US5276705A (en) 1993-01-06 1994-01-04 The Boeing Company CCD demodulator/correlator
US5488629A (en) 1993-02-17 1996-01-30 Matsushita Electric Industrial Co., Ltd. Signal processing circuit for spread spectrum communications
US5574721A (en) * 1994-12-09 1996-11-12 Stanford Telecommunications, Inc. Orthogonal code tracking system having phantom carrier signal
US5768700A (en) 1996-03-14 1998-06-16 Advanced Micro Devices, Inc. High conversion gain CMOS mixer
US5822423A (en) * 1996-03-20 1998-10-13 Numerex Investment Corporation Apparatus and method for supervising derived channel communications
JPH10229378A (en) * 1996-04-02 1998-08-25 Sharp Corp Matched filter
US5872446A (en) 1997-08-12 1999-02-16 International Business Machines Corporation Low voltage CMOS analog multiplier with extended input dynamic range
US5847623A (en) 1997-09-08 1998-12-08 Ericsson Inc. Low noise Gilbert Multiplier Cells and quadrature modulators

Also Published As

Publication number Publication date
US6330274B1 (en) 2001-12-11
AU6384799A (en) 2000-03-27
WO2000014892A1 (en) 2000-03-16

Similar Documents

Publication Publication Date Title
WO2000014892B1 (en) Spread-spectrum continuous-time analog correlator and method therefor
CA2659665C (en) Selective noise cancellation of a spread spectrum signal
KR100450838B1 (en) Symbol-matched filter having a low silicon and power requirement
US5856997A (en) Spread spectrum receiving apparatus
JP3441301B2 (en) Receiver and synchronization acquisition circuit
KR960020139A (en) Data Transmitter and Receiver in Spread Spectrum Communication System Using Pilot Channel
KR960006320A (en) Pseudo-Noise Code Synchronizer Using Adaptive Threshold
US20010005394A1 (en) Data transmitter and receiver of a DS-CDMA communication system
US3916313A (en) PSK-FSK spread spectrum modulation/demodulation
JPH0799487A (en) Spread spectrum communication equipment and radio communication equipment
KR970072739A (en) Spectrum spread communication system for high speed communication
JP2007295544A (en) Signal generating method, preamble signal, transmitter, receiver and synchronization method
US20100310072A1 (en) Symbol duration dithering for secured chaotic communications
CN103560803A (en) Code-hopping direct spread communication method and system based on OVSF codes
JP3160718B2 (en) Synchronization method for pseudo-random number sequence with code ambiguity in communication system
US5796774A (en) Spread spectrum communication apparatus with conversion of input patterns to uniform spectral patterns
US5668806A (en) Spread spectrum communication apparatus
WO2001022608A1 (en) Correlator
AU2002215133A1 (en) A rake receiver and a method of providing a frequency error estimate
KR100994982B1 (en) Method for selecting Adaptive Frequency Baseband of Walsh codes, Adaptive Frequency Selective Spreader using the same and Apparatus for Transmitting and Receiving using the same
JPH0758669A (en) Digital matched filter
WO1999038337A2 (en) Method and system for generating a complex pseudonoise sequence for processing a code division multiple access signal
Cartier Partial correlation properties of pseudonoise (PN) codes in noncoherent synchronization/detection schemes
Hakizimana et al. A new M-ary wideband communication system with application to multipath channels-part i: system performance
JP3666623B2 (en) Correlator

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref country code: AU

Ref document number: 1999 63847

Kind code of ref document: A

Format of ref document f/p: F

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: B1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: B1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

B Later publication of amended claims
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase