WO2000015133A2 - A method of a decomposition and an assembling of general microcomputer systems - Google Patents
A method of a decomposition and an assembling of general microcomputer systems Download PDFInfo
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- WO2000015133A2 WO2000015133A2 PCT/CZ1999/000032 CZ9900032W WO0015133A2 WO 2000015133 A2 WO2000015133 A2 WO 2000015133A2 CZ 9900032 W CZ9900032 W CZ 9900032W WO 0015133 A2 WO0015133 A2 WO 0015133A2
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- hardware
- software entities
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000000354 decomposition reaction Methods 0.000 title claims abstract description 9
- 230000006870 function Effects 0.000 claims abstract description 16
- 238000013461 design Methods 0.000 claims abstract description 8
- 230000011664 signaling Effects 0.000 claims abstract description 7
- 230000003993 interaction Effects 0.000 claims abstract description 5
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 238000003491 array Methods 0.000 claims description 6
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 23
- 244000046052 Phaseolus vulgaris Species 0.000 description 23
- 238000004891 communication Methods 0.000 description 11
- 230000000977 initiatory effect Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- WGCNASOHLSPBMP-UHFFFAOYSA-N Glycolaldehyde Chemical compound OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
- G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
Definitions
- Scope of technology __ The invention relates to a method of decomposition of general microcomputer systems and their subsequent assembling to operational units.
- Integrated circuits and microcomputers are designed so as to allow adding hardware entities, such as various peripherals and simple circuits in further layers of a chip onto a microprocessor core. These circuits are interconnected by a common bus with the microprocessor core. Outputs of single circuits are connected to output te ⁇ ninals of the microcomputer.
- the microcomputers are accompanied with catalogue sheets and manuals provided with data for a designer to create microcomputer systems out of different microcomputer peripheries.
- a drawback of the present day state of technology resides in that a design incorporating complex microprocessors in a microcomputer system by hardware and software means represents time consuming work of hardware and software developers, thus becoming a hindrance slowing down a development of new electronic products.
- the decomposition consists in that the system is divided into embedded elementary hardware and software entities defined as embedded beans, whereafter the manufacturers data or measurement serve to define characteristics of each embedded entity that can be used for setting the behavior of the embedded elementary entity, procedures and functions for an interaction of the program with the embedded elementary entity, and also a way of signaling a change of an internal status of the embedded elementary entity.
- These embedded elementary hardware and software entities are selected from a group consisting of a processor core, of peripheries on a processor chip, peripheries created outside the processor chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware functions by way of software, and pure software implementation.
- Another subject of the invention consists in die way of assembling microcomputer systems wherein the development of a final microcomputer system with required characteristics and functions is achieved by way -of developing the interconnection of embedded elementary hardware and software entities, whereafter at least one microcomputer is selected in which the necessary embedded elementary hardware and software entities are chosen that are defined between its single inputs and outputs, and such embedded elementary hardware and software entities are connected according to the original design of the interconnection of embedded elementary hardware and software entities.
- Such embedded elementary hardware and software entities are selected from the group consisting of the processor core, of peripheries on the processor chip, peripheries created outside the processor chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware functions by way of software, and pure software implementations.
- Fig. 1 shows an exemplifying mask for setting the characteristics of an embedded elementary hardware and software entity by way of a dialog with the computer
- Fig. 2 shows an exemplifying mask for setting the procedures and functions of an elementary hardware and software entity by way of a dialog with the computer
- Fig. 3 shows an exemplifying mask for setting the basic ways of signaling a change of the internal status of the asynchronous serial master by way of a dialog with the computer
- Fig. 4 shows an exemplifying microcomputer system assembled according to the present invention.
- the microcomputer should be at first divided into embedded elementary hardware and software entities defined between single inputs and outputs, or possibly groups of inputs and outputs, of a microcomputer system.
- embedded elementary hardware and software entities called embedded beans by those familiar with the art, are selected from a group consisting of the processor core, of peripheries on the processor chip, peripheries created outside the chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware operations by way of software, and pure software implementation.
- microprocessor series such as Toshiba
- Tlcs900, Motorola HC12 and Atmel AV90 these basic embedded elementary hardware and software entities, or in other words embedded beans, can be defined as follows: A general 1-bit input/output, general multibit input/output, general 1-Byte input/output (1 to 8 bites), a general 1 word 16 bit input/output, a general 3-Byte input/output, a general 4-Byte mput/output, a general 32-bit input/output, an external 8-bit input/output, an external 16-bit input/output, an external 32-bit input/output, an external interruption, an 8-bit idlmg run counter, a 16-bit idling run counter, a 32-bit idling run counter, an 8-bit counter of events, a 16-bit counter of events, a 32- bit counter of events, a circuit of time and date, a periodical interruption, an output of bistable flip-flop circuit 1 :1 , a programmable impulse
- an asynchronous serial master embedded bean can be mentioned.
- Such embedded bean in co- operation with an asynchronous serial slave, supports the master-slave communication. This allows up to 257 control microentities to be connected, namely one master and 256 slaves. Each slave has its unique identification, numbered from 1 to 255.
- a communication format has one information bh-and one initiation or transmission bit.
- the slaves are in a sleeping mode as to commimication, waiting for the unit level of an initiation bit.
- the master sends an 8-bit address of the slave wishing to communicate with the unit level as the initiation bit. All the slaves awake and receive the information.
- the slave with the same identification, i.e. the chosen slave starts communicating with the master, whereas the others return mto the sleeping mode regarding coirimunication.
- the master sends 8 bits of data and a logical zero as the initiation bit. No other slave, accordingly, gets interrupted.
- Basic features utilisable for adjusting the behavior of the asynchronous serial master can be characterised as follows:
- Channel - a channel used for a serial communication
- Initialisation starting set-up, i.e. adjusting after switching on or re-setting.
- Activation in initialisation code - the channel will be activated
- Events activated during initialisation - the events will be activated
- Priority - priority of the embedded bean Baud rate the modulation speed after switching on or resetting that can not be altered
- Input buffer size the size of the input buffer in bytes
- the procedures and functions for the interaction of a program with the asynchronous serial master can be divided into 5 basic categories.
- __ The first category are enable/disable functions used for the activation/blocking of channels/events:
- Enable - activates the channel, i.e. activates transmission/reception
- the second category are Send/receive methods, used for the transmission and the reception of data.
- RecvChar in case of the reception of data it returns one character, or else - the code returns errors and does not wait for the data
- RecvBlock in case of the reception of the data, the block and its length are returned, including possible error, or else it returns the error code without waiting for the data.
- the third category are State methods that are used for a learning the status of the buffer and failures of the channel:
- GetError - returns the set of errors in the channel, namely errors that can not be returned in the current way. These errors are accumulated in a set. After GetError this set is returned and deleted.
- the fourth category are Master-slave methods, used for the control of the master/slave communication:
- SelectSlave - the selection of slave equals sending the slave address for initiating the communication, the initiating bit bemg at the level of logical i.
- the fourth category are BreakMethods, used for an interrupting function: SetBreak - sends the interruption sequence to the output line GetBreak - tests the internal input interruption label, returning it irrespective of whether there has been an interruption or not, and deletes the same.
- the setting of these procedures and functions is enabled by the dialog with the computer, an example of a mask for such dialog being shown in Fig. 2.
- the basic ways for signalling a change of the internal status of an asynchronous serial master can be characterised as follows: BeforeNewSpeed - this event is initialised due to a change of a speed mode of the basic unit while using methods of the basic unit prior to a change. AfterNewSpeed - this event is initialised due to the change of the speed mode of the basic unit while using methods of the basic unit prior to the change OnError - this event is initialised if an error of the channel occurs, not the error reflected by the given method. The errors can be read by way of GetError. OnRxChar - this event is initiated after the correct character has been received
- OnTxChar - this event is initiated after the character has been sent OnFreeTxBuff - this event is initiated after the last character of the output buffer has been sent OnFullRxBuf - tins event is initiated when the output buffer is full
- OnBreak - this event is initiated when an interruption at the input appears, it does not change the status of the internal interruption label, the latter being set permanently, see methods GetBreak.
- Selected events the following data arrays are valid for the chosen event_ Procedure name is a name of a procedure inscribed by the user processing the given event
- Priority is the priority of the user, e.g. it can be set as uninterruptable
- These basic methods for signaling the change of the internal status of the asynchronous serial master can be set by a way of a dialog with the computer, a preferable embodiment of a mask for tins dialog bemg shown in Fig. 3.
- Fig. 4 shows such microcomputer system drafted so as to periodically calculate date and time, to evaluate eight logical states and to signal the status changes of one logical output.
- This microcomputer system consisting of the microprocessor Toshiba TMP96C141AF applies the following: a circuit of time and date - TD, a circuit of mterruption by timer - Tmrlnt, a general byte input/output - Bean 1 and a bit input/output 1 - BitlOl.
- Single microprocessor pins in the figure are marked with labels denoting the embedded bean in the microprocessor to which they belong.
- some microprocessor pins are provided with earth labels, with AdrDat label denoting an address or a date bus or a combined bus, CTRL label denoting the control bus, an OTHER label denoting pins allocated by the manufacturer that can not be used for embedded beans and a USER label that the user has reserved for himself in a CPU configuration.
- AdrDat label denoting an address or a date bus or a combined bus
- CTRL label denoting the control bus
- an OTHER label denoting pins allocated by the manufacturer that can not be used for embedded beans
- a USER label that the user has reserved for himself in a CPU configuration.
- the decomposition of d e microprocessor to single embedded beans allows the developer to assemble the developed circuit by interconnecting single embedded beans, irrespective of the microprocessor that will be used in the developed circuit at the final stage. Accordingly, the developer can devote himself to a genuine creative work, delegating problems with the physical construction of the microcomputer system to routine programmers or to the computer that will design the interconnection of the inputs and outputs of the microcomputer for the described scheme of single embedded beans. If the computer system requires more embedded beans than the number provided by the given microprocessor or, possibly, if it requires other embedded beans than diose available in the existing microcomputer, yet another microcomputer comprising the required embedded beans will be added to the system. This system of development allows, if it is required, to transfer the developed microcomputer system to another hardware while the routine programmer or the computer can design only a different interconnection of the inputs and outputs of another type of the microcomputer for the already developed interconnection of embedded beans.
Abstract
The solution relates to a method of decomposition and assembling general microcomputer systems. In the course of decomposition the system is divided into embedded elementary hardware and software entities defined between single inputs and outputs or, possibly, by groups of inputs and outputs of the microcomputer system, whereupon for each embedded elementary entity its characteristics derived from a manufacturers data or by a measurement are defined that are utilisable for setting the behavior of the embedded elementary entity, further procedures and functions for an interaction of a program with the embedded elementary entity and a method for signaling a change of an internal state of the embedded elementary entity. When assembling the required microprocessor systems, an interconnection of the embedded elementary hardware and software entities is developed for a design of the final microcomputer system with required characteristics and functions, whereupon at least one microcomputer is selected in which the necessary embedded elementary hardware and software entities are chosen that are defined between its single inputs and outputs, and these embedded elementary hardware and software entities are connected accroding to the original design of the interconnection of the embedded elementary hardware and software entities.
Description
A method of a decomposition and an assembling of general microcomputer systems
Scope of technology __ The invention relates to a method of decomposition of general microcomputer systems and their subsequent assembling to operational units.
Prior state of art
Integrated circuits and microcomputers are designed so as to allow adding hardware entities, such as various peripherals and simple circuits in further layers of a chip onto a microprocessor core. These circuits are interconnected by a common bus with the microprocessor core. Outputs of single circuits are connected to output teπninals of the microcomputer. The microcomputers are accompanied with catalogue sheets and manuals provided with data for a designer to create microcomputer systems out of different microcomputer peripheries.
A drawback of the present day state of technology resides in that a design incorporating complex microprocessors in a microcomputer system by hardware and software means represents time consuming work of hardware and software developers, thus becoming a hindrance slowing down a development of new electronic products.
Summary of the invention
The above disadvantages of the present day state of art are considerably eliminated by a way of decomposition and assembling of general microcomputer systems wherein the decomposition consists in that the system
is divided into embedded elementary hardware and software entities defined as embedded beans, whereafter the manufacturers data or measurement serve to define characteristics of each embedded entity that can be used for setting the behavior of the embedded elementary entity, procedures and functions for an interaction of the program with the embedded elementary entity, and also a way of signaling a change of an internal status of the embedded elementary entity. These embedded elementary hardware and software entities are selected from a group consisting of a processor core, of peripheries on a processor chip, peripheries created outside the processor chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware functions by way of software, and pure software implementation. Another subject of the invention consists in die way of assembling microcomputer systems wherein the development of a final microcomputer system with required characteristics and functions is achieved by way -of developing the interconnection of embedded elementary hardware and software entities, whereafter at least one microcomputer is selected in which the necessary embedded elementary hardware and software entities are chosen that are defined between its single inputs and outputs, and such embedded elementary hardware and software entities are connected according to the original design of the interconnection of embedded elementary hardware and software entities. Such embedded elementary hardware and software entities are selected from the group consisting of the processor core, of peripheries on the processor chip, peripheries created outside the processor chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware functions by way of software, and pure software implementations.
Brief description of the drawings
The invention will be further described in more detail according to the accompanying drawings where Fig. 1 shows an exemplifying mask for setting the characteristics of an embedded elementary hardware and software entity by way of a dialog with the computer, Fig. 2 shows an exemplifying mask for setting the procedures and functions of an elementary hardware and software entity by way of a dialog with the computer, Fig. 3 shows an exemplifying mask for setting the basic ways of signaling a change of the internal status of the asynchronous serial master by way of a dialog with the computer and Fig. 4 shows an exemplifying microcomputer system assembled according to the present invention.
Examples of preferred embodiments of the invention
For perfoπning the method according to the invention the microcomputer should be at first divided into embedded elementary hardware and software entities defined between single inputs and outputs, or possibly groups of inputs and outputs, of a microcomputer system. These embedded elementary hardware and software entities called embedded beans by those familiar with the art, are selected from a group consisting of the processor core, of peripheries on the processor chip, peripheries created outside the chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware operations by way of software, and pure software implementation. Thus for microprocessor series, such as Toshiba
Tlcs900, Motorola HC12 and Atmel AV90, these basic embedded elementary hardware and software entities, or in other words embedded beans, can be defined as follows: A general 1-bit input/output, general multibit input/output,
general 1-Byte input/output (1 to 8 bites), a general 1 word 16 bit input/output, a general 3-Byte input/output, a general 4-Byte mput/output, a general 32-bit input/output, an external 8-bit input/output, an external 16-bit input/output, an external 32-bit input/output, an external interruption, an 8-bit idlmg run counter, a 16-bit idling run counter, a 32-bit idling run counter, an 8-bit counter of events, a 16-bit counter of events, a 32- bit counter of events, a circuit of time and date, a periodical interruption, an output of bistable flip-flop circuit 1 :1 , a programmable impulse generator, an impulse width modulator, a frequency meter, a period meter, an impulse width meter, a generator of one impulse from an external starting impulse, a generator of one impulse from an external starting impulse with delay, a meter of two signals, a synchronous serial communication, an asynchronous serial comiΩunication-master, an asynchronous serial communication-slave, a master for the synchronous serial communication, a slave for the synchronous serial communication, an analogue-digital converter, a monitoring unit (watch dog), an external converter of a binary file, a converter of text chains, an 8-character display with 8 segments per character, a LCD display and a keyboard. These single entities or embedded beans are always defined between one or more inputs into the microprocessor and one or more outputs of the same microprocessor. Then, for each embedded elementary entity of this type, three categories of data are defined from the characteristics of the manufacturer or by the measurement, namely its features utilisable for setting the behavior of an embedded elementary entity, procedures and functions for the interaction of the program with the embedded elementary entity, and the way for signaling a change of the internal status of the embedded elementary entity.
As example of an embodiment of the above procedure an asynchronous serial master embedded bean can be mentioned. Such embedded bean, in co-
operation with an asynchronous serial slave, supports the master-slave communication. This allows up to 257 control microentities to be connected, namely one master and 256 slaves. Each slave has its unique identification, numbered from 1 to 255. A communication format has one information bh-and one initiation or transmission bit.
At the start the slaves are in a sleeping mode as to commimication, waiting for the unit level of an initiation bit. The master sends an 8-bit address of the slave wishing to communicate with the unit level as the initiation bit. All the slaves awake and receive the information. The slave with the same identification, i.e. the chosen slave, starts communicating with the master, whereas the others return mto the sleeping mode regarding coirimunication. h the course of communication with the selected slave the master sends 8 bits of data and a logical zero as the initiation bit. No other slave, accordingly, gets interrupted. Basic features utilisable for adjusting the behavior of the asynchronous serial master can be characterised as follows:
Channel - a channel used for a serial communication
Stop bit - number of stop bits
Break enabled - opemng/closing of a communication interruption - special condition of the channel used for renewmg the original communication status. Initialisation - starting set-up, i.e. adjusting after switching on or re-setting. Activation in initialisation code - the channel will be activated Events activated during initialisation - the events will be activated Priority - priority of the embedded bean Baud rate - the modulation speed after switching on or resetting that can not be altered
Input buffer size - the size of the input buffer in bytes
Operates in speed modes - speed modes in which the embedded bean works.
These characteristics can be set by way of dialog with the computer, while an example of a mask of this dialogue is shown in Fig. 1.
The procedures and functions for the interaction of a program with the asynchronous serial master can be divided into 5 basic categories. __ The first category are enable/disable functions used for the activation/blocking of channels/events:
Enable - activates the channel, i.e. activates transmission/reception
Disable - closes the channel, i.e. blocks a transmission/reception
EnableEvents - activates events DisbaleEvents - blocks events
The second category are Send/receive methods, used for the transmission and the reception of data.
SendChar - sends one character to a channel
RecvChar - in case of the reception of data it returns one character, or else - the code returns errors and does not wait for the data
SendBlock - a block of characters is sent to the channel
RecvBlock - in case of the reception of the data, the block and its length are returned, including possible error, or else it returns the error code without waiting for the data. The third category are State methods that are used for a learning the status of the buffer and failures of the channel:
CharsInRxBuf - returns the number of characters in the internal buffer
CharsInTcBuf - returns the number of characters in the output buffer
GetError - returns the set of errors in the channel, namely errors that can not be returned in the current way. These errors are accumulated in a set. After GetError this set is returned and deleted.
The fourth category are Master-slave methods, used for the control of the master/slave communication:
SelectSlave - the selection of slave equals sending the slave address for initiating the communication, the initiating bit bemg at the level of logical i. The fourth category are BreakMethods, used for an interrupting function: SetBreak - sends the interruption sequence to the output line GetBreak - tests the internal input interruption label, returning it irrespective of whether there has been an interruption or not, and deletes the same. The setting of these procedures and functions is enabled by the dialog with the computer, an example of a mask for such dialog being shown in Fig. 2. The basic ways for signalling a change of the internal status of an asynchronous serial master can be characterised as follows: BeforeNewSpeed - this event is initialised due to a change of a speed mode of the basic unit while using methods of the basic unit prior to a change. AfterNewSpeed - this event is initialised due to the change of the speed mode of the basic unit while using methods of the basic unit prior to the change OnError - this event is initialised if an error of the channel occurs, not the error reflected by the given method. The errors can be read by way of GetError. OnRxChar - this event is initiated after the correct character has been received
OnTxChar - this event is initiated after the character has been sent OnFreeTxBuff - this event is initiated after the last character of the output buffer has been sent OnFullRxBuf - tins event is initiated when the output buffer is full
OnBreak - this event is initiated when an interruption at the input appears, it does not change the status of the internal interruption label, the latter being set permanently, see methods GetBreak. Selected events - the following data arrays are valid for the chosen event_ Procedure name is a name of a procedure inscribed by the user processing the given event
Priority is the priority of the user, e.g. it can be set as uninterruptable These basic methods for signaling the change of the internal status of the asynchronous serial master can be set by a way of a dialog with the computer, a preferable embodiment of a mask for tins dialog bemg shown in Fig. 3.
The developer can draft the interconnection of the above described and adjusted embedded beans to create a microprocessor system that will be provided with embedded beans of required features calculable in advance. Fig. 4 shows such microcomputer system drafted so as to periodically calculate date and time, to evaluate eight logical states and to signal the status changes of one logical output. This microcomputer system consisting of the microprocessor Toshiba TMP96C141AF applies the following: a circuit of time and date - TD, a circuit of mterruption by timer - Tmrlnt, a general byte input/output - Bean 1 and a bit input/output 1 - BitlOl. Single microprocessor pins in the figure are marked with labels denoting the embedded bean in the microprocessor to which they belong. In addition to these labels some microprocessor pins are provided with earth labels, with AdrDat label denoting an address or a date bus or a combined bus, CTRL label denoting the control bus, an OTHER label denoting pins allocated by the manufacturer that can not be used for embedded beans and a USER label that the user has reserved for himself in a CPU configuration. The features of this microcomputer system, given by the configuration of the embedded beans
implemented can be used and its behavior can be affected, on the one hand, by setting embedded beans and, on the other hand, by adding further embedded beans or by adding a user code. The decomposition of d e microprocessor to single embedded beans allows the developer to assemble the developed circuit by interconnecting single embedded beans, irrespective of the microprocessor that will be used in the developed circuit at the final stage. Accordingly, the developer can devote himself to a genuine creative work, delegating problems with the physical construction of the microcomputer system to routine programmers or to the computer that will design the interconnection of the inputs and outputs of the microcomputer for the described scheme of single embedded beans. If the computer system requires more embedded beans than the number provided by the given microprocessor or, possibly, if it requires other embedded beans than diose available in the existing microcomputer, yet another microcomputer comprising the required embedded beans will be added to the system. This system of development allows, if it is required, to transfer the developed microcomputer system to another hardware while the routine programmer or the computer can design only a different interconnection of the inputs and outputs of another type of the microcomputer for the already developed interconnection of embedded beans.
Claims
1. A method of a decomposition of general microcomputer systems characterised by dividing the system to embedded elementary hardware- and software entities defined between single inputs and outputs, or possibly groups of inputs and outputs of the microcomputer system, whereafter for each said embedded elementary entity a following is defined from a manufacturer's data or by a measurement
- its characteristics utilisable for setting the behavior of the embedded elementary entity,
- procedures and functions for an interaction of a program with the embedded elementary entity, and
- a method for signaling a change of an internal state of the embedded elementary entity.
2. The method according to claim 1, characterised in that the embedded hardware and software entities are selected from a group consisting of a processor core, peripheries on a processor chip, peripheries created outside the processor chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware functions by way of a software, and pure software implementations.
3. A method of composing a microcomputer system, characterised in that for a design of the final microcomputer system with required characteristics and functions an interconnection of embedded elementary hardware and software entities is developed, whereupon at least one microcomputer is chosen in which the necessary embedded elementary hardware and software entities are selected between its single inputs and outputs, and these embedded hardware and software entities are interconnected according to the original design of the interconnection of the embedded elementary hardware and software entities.
4. The method according to claim 3, characterised in that the embedded hardware and software entities are selected from a group consisting of a processor core, peripheries on a processor chip, peripheries created outside the processor chip, such as intelligent controllers in special circuits or programmable logical arrays, virtual peripheries simulating hardware functions by way of a software, and pure software implementations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU56161/99A AU5616199A (en) | 1998-09-14 | 1999-09-14 | A method of a decomposition and an assembling of general microcomputer systems |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CZPV2918-98 | 1998-09-14 | ||
| CZ19982918A CZ291898A3 (en) | 1998-09-14 | 1998-09-14 | Decomposition and assembly process of microcomputer systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2000015133A2 true WO2000015133A2 (en) | 2000-03-23 |
| WO2000015133A3 WO2000015133A3 (en) | 2000-08-31 |
Family
ID=5465828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CZ1999/000032 WO2000015133A2 (en) | 1998-09-14 | 1999-09-14 | A method of a decomposition and an assembling of general microcomputer systems |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU5616199A (en) |
| CZ (1) | CZ291898A3 (en) |
| WO (1) | WO2000015133A2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293479A (en) * | 1991-07-08 | 1994-03-08 | Quintero Smith Incorporated | Design tool and method for preparing parametric assemblies |
| US5357440A (en) * | 1991-02-26 | 1994-10-18 | Texas Instruments Incorporated | Method and apparatus for aiding system design |
| US5544067A (en) * | 1990-04-06 | 1996-08-06 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
| US5675748A (en) * | 1993-12-21 | 1997-10-07 | Object Technology Licensing Corp. | Method and apparatus for automatically configuring computer system hardware and software |
-
1998
- 1998-09-14 CZ CZ19982918A patent/CZ291898A3/en unknown
-
1999
- 1999-09-14 AU AU56161/99A patent/AU5616199A/en not_active Abandoned
- 1999-09-14 WO PCT/CZ1999/000032 patent/WO2000015133A2/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5544067A (en) * | 1990-04-06 | 1996-08-06 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
| US5357440A (en) * | 1991-02-26 | 1994-10-18 | Texas Instruments Incorporated | Method and apparatus for aiding system design |
| US5293479A (en) * | 1991-07-08 | 1994-03-08 | Quintero Smith Incorporated | Design tool and method for preparing parametric assemblies |
| US5675748A (en) * | 1993-12-21 | 1997-10-07 | Object Technology Licensing Corp. | Method and apparatus for automatically configuring computer system hardware and software |
Also Published As
| Publication number | Publication date |
|---|---|
| CZ291898A3 (en) | 2000-03-15 |
| AU5616199A (en) | 2000-04-03 |
| WO2000015133A3 (en) | 2000-08-31 |
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