WO2000019222A2 - Semiconductor switching circuit with an integrated self-testing circuit - Google Patents

Semiconductor switching circuit with an integrated self-testing circuit Download PDF

Info

Publication number
WO2000019222A2
WO2000019222A2 PCT/DE1999/003117 DE9903117W WO0019222A2 WO 2000019222 A2 WO2000019222 A2 WO 2000019222A2 DE 9903117 W DE9903117 W DE 9903117W WO 0019222 A2 WO0019222 A2 WO 0019222A2
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
self
semiconductor
circuits
test
Prior art date
Application number
PCT/DE1999/003117
Other languages
German (de)
French (fr)
Other versions
WO2000019222A3 (en
Inventor
Helmut Schneider
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2000019222A2 publication Critical patent/WO2000019222A2/en
Publication of WO2000019222A3 publication Critical patent/WO2000019222A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention relates to a semiconductor switching circuit with a self-testing circuit. Said self-testing circuit (BIST) is located under a connection pad (P), which is provided for operating the self-testing circuit (BIST).

Description

Beschreibungdescription
Halbleiterschaltkreis mit integrierter SelbsttestschaltungSemiconductor circuit with integrated self-test circuit
Die vorliegende Erfindung betrifft einen Halbleiterschalt¬ kreis mit einer integrierten Selbsttestschaltung.The present invention relates to a semiconductor circuit with an integrated self-test circuit.
Häufig werden Halbleiterschaltkreise nach deren Herstellung auf einem Wafer, noch vor Umhüllen mit einem Gehäuse, einem sogenannten Burn-In unterzogen. Dabei werden die Halbleiterschaltkreise für eine gegebene Zeit einer Temperatur ausgesetzt, die in der Regel höher ist als die vom Hersteller vorgegebene maximale Lagertemperatur. Sinn dieser Prozedur ist es, daß der Halbleiterschaltkreis vorzeitig altert, und daß dadurch alterungsbedingte Ausfälle nicht erst beim Kunden auftreten, sondern bereits beim Hersteller und daß gegebenenfalls vorhandene Zulässigkeitsprobleme möglichst frühzeitig erkannt werden. Deshalb werden die Halbleiterschaltkreise während der Burn-In-Phase auch ständig auf Funktionsfähigkeit getestet. Während früher dazu notwendige Testschaltungen schaltkreisextern angeordnet waren (z. B. auf sogenannten Burn-In-Boards, auf denen die Halbleiterschaltkreise während der Burn-In-Prozedur aufgebracht sind) , werden diese Testschaltungen heutzutage als sogenannte Selbsttestschaltungen in den Halbleiterschaltkreis mit integriert, weshalb die Fläche eines solchen Halbleiterschaltkreises naturgemäß größer ist als die Fläche eines funktionidentischen Halbleiter- schaltkreises ohne Selbsttestschaltung.Semiconductor circuits are often subjected to a so-called burn-in after their manufacture on a wafer, even before they are encased in a housing. The semiconductor circuits are exposed to a temperature for a given time, which is usually higher than the maximum storage temperature specified by the manufacturer. The purpose of this procedure is that the semiconductor circuit ages prematurely, and that age-related failures do not only occur at the customer's, but already at the manufacturer's, and that any existing admissibility problems are recognized as early as possible. That is why the semiconductor circuits are constantly tested for functionality during the burn-in phase. While previously necessary test circuits were arranged outside the circuit (e.g. on so-called burn-in boards, on which the semiconductor circuits are applied during the burn-in procedure), these test circuits are now integrated into the semiconductor circuit as so-called self-test circuits, which is why the area of such a semiconductor circuit is naturally larger than the area of a functionally identical semiconductor circuit without a self-test circuit.
Ziel aller Halbleiterschaltkreishersteller ist es seit jeher, mit einer möglichst geringen Fläche für einen Halbleiterschaltkreis auszukommen, denn je geringer die benötigte Fläche ist, desto billiger ist der Schaltkreis herstellbar (die absoluten Herstellungskosten sind lediglich abhängig von der Größe eines Wafers, auf dem die Schaltkreise herzustellen sind, nicht jedoch von der Anzahl der herzustellenden Schaltkreise pro Wafer, so daß die Herstellungskosten je Halblei- terschaltkreis umso niedriger ausfallen, je mehr Halbleiter¬ schaltkreise auf einem Wafer gegebener Größe Platz finden, oder, anders ausgedrückt: je geringer die Fläche des Halblei¬ terschaltkreises ist) .It has always been the goal of all semiconductor circuit manufacturers to get by with the smallest possible area for a semiconductor circuit, because the smaller the area required, the cheaper the circuit can be manufactured (the absolute manufacturing costs only depend on the size of a wafer on which the circuits are manufactured are, but not on the number of circuits to be manufactured per wafer, so that the manufacturing costs per semiconductor terschaltkreis more be lower, the more semiconductor ¬ find circuits on a given wafer size area, or in other words: the smaller the area of the semiconducting ¬ is terschaltkreises).
Aufgabe der vorliegenden Erfindung ist es, einen gattungsgemäßen Halbleiterschaltkreis mit einer möglichst geringen Fläche zu schaffen.The object of the present invention is to create a generic semiconductor circuit with the smallest possible area.
Erfindungsgemäß ist dazu vorgesehen, eine Selbsttestschaltung so anzuordnen, daß sie unterhalb eines Anschlußpads des Halbleiterschaltkreises liegt, welches zum Betrieb der Selbttest- schaltung vorgesehen ist (das Anschlußpad wird während des Burn-In-Vorganges mittels einer Prüfspitze elektrisch kontak- tiert) .According to the invention, it is provided to arrange a self-test circuit so that it lies below a connection pad of the semiconductor circuit which is provided for operating the self-test circuit (the connection pad is electrically contacted by means of a test probe during the burn-in process).
Ein erfindungsgemäßer Halbleiterschaltkreis ist in der Zeichnung, stark schematisiert und ausschnittsweise, dargestellt:A semiconductor circuit according to the invention is shown in the drawing, highly schematic and in sections:
Ein Halbleiterkörper S enthält die für die Funktion des Halbleiterschaltkreises typischen elektrischen Schaltungen (nicht dargestellt) sowie eine Selbsttestschaltung BIST. Diese ist unterhalb eines der Selbsttestschaltung BIST zugeordneten Anschlußpads P angeordnet (es können gegebenenfalls auch mehre- re Anschlußpads P sein) und mit diesem elektrisch verbunden, beispielsweise mittels eines sogenannten Kontaktloches (nicht dargestellt) . Die Selbsttestschaltung BIST ist weiterhin, wie allgemein üblich, mit wenigstens einem Teil der für die Funktion des Halbleiterschaltkreises typischen elektronischen Schaltungen elektrisch verbunden (ebenfalls nicht dargestellt) . Dadurch, daß die Selbsttestschaltung BIST unterhalb des Anschlußpads P angeordnet ist, wird dieser (bislang nicht genutzte) Platz des Chips des Halbleiterschaltkreises sinnvoll ausgenutzt und die notwendige Gesamtfläche des Chips läßt sich entsprechend verringern. Sollte Gefahr bestehen, daß beim nachfolgenden Bonden von weiteren Anschlußflächen des Halbleiterschaltkreises die Selbsttestschaltung BIST (die dann ja nicht mehr benötigt wird, da das Bonden erst nach dem Burn-IN-Vorgang erfolgt) beschädigt wird (was als solches ohne Belang ist, denn die Selbsttestschaltung wird nach dem Burn-IN-Vorgang ja nicht mehr benötigt) mit der Folge, daß durch diese Beschädigung die weiteren elektronischen Schaltungen des Halbleiterschaltkreises, die dessen elektronische Funktion bestimmen, ungün- stig beeinflußt werden könnten, so können an der Schnittstelle Selbsttestschaltung BIST - weitere elektronische Schaltungen als Schalter fungierende Elemente vorgesehen werden, die während der Burn-In-Prozedur die Selbsttestschaltung BIST mit den weiteren elektronischen Schaltungen verbinden und die an- sonsten die Selbsttestschaltung BIST von den weiteren elektronischen Schaltungen abkoppeln. A semiconductor body S contains the electrical circuits (not shown) which are typical for the function of the semiconductor circuit and a self-test circuit BIST. This is arranged below a connection pad P assigned to the self-test circuit BIST (there may also be several connection pads P) and electrically connected to it, for example by means of a so-called contact hole (not shown). The self-test circuit BIST is also, as is generally customary, electrically connected to at least some of the electronic circuits typical of the functioning of the semiconductor circuit (likewise not shown). Because the self-test circuit BIST is arranged below the connection pad P, this (previously unused) space of the chip of the semiconductor circuit is used in a sensible manner and the necessary total area of the chip can be reduced accordingly. If there is a risk that the subsequent bonding of further connection areas of the semiconductor circuit will damage the self-test circuit BIST (which is then no longer required since the bonding only takes place after the burn-in process) (which as such is irrelevant because the Self-test switching is no longer required after the burn-in process), with the result that this damage could adversely affect the other electronic circuits of the semiconductor circuit that determine its electronic function, so self-test switching BIST can be carried out at the interface. further electronic circuits are provided as elements which act as switches and which connect the self-test circuit BIST to the further electronic circuits during the burn-in procedure and which otherwise decouple the self-test circuit BIST from the further electronic circuits.

Claims

Patentanspruch Claim
1. Halbleiterschaltkreis mit integrierter Selbsttestschaltung, dadurch gekennzeichnet, daß die Selbsttestschaltung (BIST) unterhalb eines Anschlußpads (P) angeordnet ist, welches zum Betrieb der Selbsttestschaltung (BIST) vorgesehen ist. 1. Semiconductor circuit with integrated self-test circuit, characterized in that the self-test circuit (BIST) is arranged below a connection pad (P) which is provided for operating the self-test circuit (BIST).
PCT/DE1999/003117 1998-09-30 1999-09-28 Semiconductor switching circuit with an integrated self-testing circuit WO2000019222A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19845064.8 1998-09-30
DE1998145064 DE19845064A1 (en) 1998-09-30 1998-09-30 Semiconductor circuit with integrated self-test circuit

Publications (2)

Publication Number Publication Date
WO2000019222A2 true WO2000019222A2 (en) 2000-04-06
WO2000019222A3 WO2000019222A3 (en) 2000-06-08

Family

ID=7882943

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/003117 WO2000019222A2 (en) 1998-09-30 1999-09-28 Semiconductor switching circuit with an integrated self-testing circuit

Country Status (3)

Country Link
DE (1) DE19845064A1 (en)
TW (1) TW432572B (en)
WO (1) WO2000019222A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10345470A1 (en) * 2003-09-30 2004-12-30 Infineon Technologies Ag Semiconductor chip wafer contact structure has cup shaped test contact surfaces and active connection multiplexer circuit in sawing grid areas

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US5965903A (en) * 1995-10-30 1999-10-12 Lucent Technologies Inc. Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246668A (en) * 1984-05-22 1985-12-06 Mitsubishi Electric Corp Semiconductor integrated circuit
JPH04365347A (en) * 1991-06-13 1992-12-17 Mitsubishi Electric Corp Element structure for monitor apparatus in semiconductor chip
JPH0794683A (en) * 1993-09-27 1995-04-07 Nec Corp Semiconductor integrated circuit device having self-diagnostic function
JP3157715B2 (en) * 1996-05-30 2001-04-16 山形日本電気株式会社 Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751065A (en) * 1993-08-05 1998-05-12 Lucent Technologies Inc. Integrated circuit with active devices under bond pads
US5965903A (en) * 1995-10-30 1999-10-12 Lucent Technologies Inc. Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 108 (E-398), 23. April 1986 (1986-04-23) & JP 60 246668 A (MITSUBISHI DENKI KK), 6. Dezember 1985 (1985-12-06) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 241 (E-1364), 14. Mai 1993 (1993-05-14) & JP 04 365347 A (MITSUBISHI ELECTRIC CORP), 17. Dezember 1992 (1992-12-17) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 04, 31. März 1998 (1998-03-31) -& JP 09 321104 A (NEC YAMAGATA LTD), 12. Dezember 1997 (1997-12-12) -& US 5 923 048 A *

Also Published As

Publication number Publication date
TW432572B (en) 2001-05-01
DE19845064A1 (en) 2000-04-13
WO2000019222A3 (en) 2000-06-08

Similar Documents

Publication Publication Date Title
EP1224482B1 (en) Method and device for the data protecting self-test of a microcontroller
EP2542905B1 (en) Method for testing an integrated circuit
DE10138556C1 (en) Method for testing input / output drivers of a circuit and corresponding test device
DE102006030360A1 (en) Method and apparatus for selectively accessing and configuring individual chips of a semiconductor wafer
US6998865B2 (en) Semiconductor device test arrangement with reassignable probe pads
DE10339940A1 (en) System and method for heterogeneous multi-point testing
DE60013210T2 (en) One-chip microcomputer and its control method
DE69432016T2 (en) Process for manufacturing integrated circuits and semiconductor wafer produced
Vollertsen Burn-in
DE102006007439B4 (en) Semiconductor chip, system and method for testing semiconductors using integrated circuit chips
US5751151A (en) Integrated circuit test apparatus
DE60106300T2 (en) INPUT / OUTPUT THROUGH TEST MODE CIRCUIT
DE19917586C2 (en) Arrangement for carrying out burn-in treatments of semiconductor devices at the wafer level
DE19808664C2 (en) Integrated circuit and method for testing it
WO2000019222A2 (en) Semiconductor switching circuit with an integrated self-testing circuit
DE10146177C2 (en) Wafer with additional circuit parts in the kerf area for testing integrated circuits on the wafer
DE19832307C2 (en) Integrated circuit with a self-test facility
DE102004043063B4 (en) Method for operating a semiconductor device with a test module
DE10029835C1 (en) Integrated circuit with test facility has test switch closed by applied test signal to allow test voltage to be applied to irreversible programmable switches
EP0945735A3 (en) Appliance for detecting contact faults during testing integrated circuits
EP0898283A2 (en) Semiconductor component and method of testing and operating the semiconductor component
DE69824226T2 (en) Contactless testing of connection buffers on a wafer
DE2938567A1 (en) Highly integrated semiconductor device - has housing with fine connecting wires and thicker conductors for both operating and testing contacts
DE19917336C2 (en) Circuit arrangement for the burn-in test of a semiconductor device
DE102004042074A1 (en) Method for testing a memory by means of external test chip and device for carrying out the method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

122 Ep: pct application non-entry in european phase