WO2000019504A3 - Methods for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures - Google Patents
Methods for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures Download PDFInfo
- Publication number
- WO2000019504A3 WO2000019504A3 PCT/US1999/021633 US9921633W WO0019504A3 WO 2000019504 A3 WO2000019504 A3 WO 2000019504A3 US 9921633 W US9921633 W US 9921633W WO 0019504 A3 WO0019504 A3 WO 0019504A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- oxide
- ono
- teos
- layer
- interpoly
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 239000003989 dielectric material Substances 0.000 title 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract 2
- 150000004767 nitrides Chemical class 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000000280 densification Methods 0.000 abstract 1
- 230000003628 erosive effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Abstract
A method of forming an improved interpoly oxide-nitride-oxide (ONO) structure in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology). This step also tends to encourage formation of a very thin silicon oxynitride layer at the interface of the nitride and TEOS layers, thus helping to cure 'pinholes' typically associated the nitride layer and further increasing the quality and reliability of the ONO structure. The improved interpoly ONO structure is found to show lower leakage current for applied electrice fields between 1 to 15MV/cm as compared to prior art.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/160,834 | 1998-09-25 | ||
| US09/160,834 US6339000B1 (en) | 1998-09-25 | 1998-09-25 | Method for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2000019504A2 WO2000019504A2 (en) | 2000-04-06 |
| WO2000019504A3 true WO2000019504A3 (en) | 2000-07-13 |
Family
ID=22578657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1999/021633 WO2000019504A2 (en) | 1998-09-25 | 1999-09-17 | Methods for fabricating interpoly dielectrics in non-volatile stacked-gate memory structures |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6339000B1 (en) |
| WO (1) | WO2000019504A2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100386611B1 (en) * | 2000-05-08 | 2003-06-02 | 주식회사 하이닉스반도체 | A array of flash memory cell and method for programming of data thereby and method for erased thereby |
| JP3617435B2 (en) * | 2000-09-06 | 2005-02-02 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| DE10122075B4 (en) * | 2001-05-07 | 2008-05-29 | Qimonda Ag | Semiconductor memory cell and its manufacturing method |
| JP2003224214A (en) * | 2002-01-31 | 2003-08-08 | Oki Electric Ind Co Ltd | Method for fabricating semiconductor element |
| US6969689B1 (en) * | 2002-06-28 | 2005-11-29 | Krishnaswamy Ramkumar | Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices |
| US6777764B2 (en) * | 2002-09-10 | 2004-08-17 | Macronix International Co., Ltd. | ONO interpoly dielectric for flash memory cells and method for fabricating the same using a single wafer low temperature deposition process |
| KR100518577B1 (en) * | 2003-05-26 | 2005-10-04 | 삼성전자주식회사 | One time programmable memory device, integrated circuit including the same and method for fabricating thereof |
| US7407820B2 (en) * | 2005-02-09 | 2008-08-05 | Macronix International Co., Ltd. | Method for monitoring oxide film deposition |
| US8587049B2 (en) * | 2006-07-17 | 2013-11-19 | Spansion, Llc | Memory cell system with charge trap |
| US10796969B2 (en) * | 2018-09-07 | 2020-10-06 | Kla-Tencor Corporation | System and method for fabricating semiconductor wafer features having controlled dimensions |
| US11385187B1 (en) | 2020-03-19 | 2022-07-12 | Kla Corporation | Method of fabricating particle size standards on substrates |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5219774A (en) * | 1988-05-17 | 1993-06-15 | Xicor, Inc. | Deposited tunneling oxide |
| US5619052A (en) * | 1994-09-29 | 1997-04-08 | Macronix International Co., Ltd. | Interpoly dielectric structure in EEPROM device |
| US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677867A (en) * | 1991-06-12 | 1997-10-14 | Hazani; Emanuel | Memory with isolatable expandable bit lines |
| JPH07123146B2 (en) | 1990-07-05 | 1995-12-25 | 株式会社東芝 | Method of manufacturing nonvolatile semiconductor memory device |
-
1998
- 1998-09-25 US US09/160,834 patent/US6339000B1/en not_active Expired - Lifetime
-
1999
- 1999-09-17 WO PCT/US1999/021633 patent/WO2000019504A2/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5219774A (en) * | 1988-05-17 | 1993-06-15 | Xicor, Inc. | Deposited tunneling oxide |
| US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
| US5619052A (en) * | 1994-09-29 | 1997-04-08 | Macronix International Co., Ltd. | Interpoly dielectric structure in EEPROM device |
Non-Patent Citations (1)
| Title |
|---|
| YATER J A ET AL: "High temperature oxide for NVM interpoly dielectric applications", SILICON FRONT-END TECHNOLOGY - MATERIALS PROCESSING AND MODELLING. SYMPOSIUM, SILICON FRONT-END TECHNOLOGY - MATERIALS PROCESSING AND MODELLING. SYMPOSIUM, SAN FRANCISCO, CA, USA, 13-15 APRIL 1998, 1998, Warrendale, PA, USA, Mater. Res. Soc, USA, pages 153 - 158, XP000909173, ISBN: 1-55899-438-6 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US6339000B1 (en) | 2002-01-15 |
| WO2000019504A2 (en) | 2000-04-06 |
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