WO2000022668A1 - Electronic module, especially a multichip module, with multi-layer metallization and corresponding production method - Google Patents

Electronic module, especially a multichip module, with multi-layer metallization and corresponding production method Download PDF

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Publication number
WO2000022668A1
WO2000022668A1 PCT/DE1999/003247 DE9903247W WO0022668A1 WO 2000022668 A1 WO2000022668 A1 WO 2000022668A1 DE 9903247 W DE9903247 W DE 9903247W WO 0022668 A1 WO0022668 A1 WO 0022668A1
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Prior art keywords
wiring
module
underside
carrier
multilayer wiring
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PCT/DE1999/003247
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German (de)
French (fr)
Inventor
Harry Hedler
Gregor Feiertag
Peter Deml
Franz Petter
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Tyco Electronics Logistics Ag
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Application filed by Tyco Electronics Logistics Ag filed Critical Tyco Electronics Logistics Ag
Priority to JP2000576488A priority Critical patent/JP2002527906A/en
Publication of WO2000022668A1 publication Critical patent/WO2000022668A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/181—Encapsulation

Definitions

  • Electronic module in particular multichip module, with multi-layer wiring and method for its production
  • the invention relates to an electronic module, in particular a multichip module, with multilayer wiring, on the component side of which at least one IC component is applied, the module being covered on one side on the component side with a hermetic housing, and with contact pads on the underside of the module, with which the contacting and integration of the module into a next higher module level can be established.
  • the invention also relates to a method for producing an electronic module, in particular a multi-chip module, with multi-layer wiring.
  • Multichip modules have been known for some time, by means of which an intermediate carrier substrate with high wiring density, HDI (High Density Interconnect), is introduced as an additional level in the hierarchy of the system structure. Typical of this are the use of several unhoused chips and a high area coverage of the multichip substrate.
  • HDI High Density Interconnect
  • a similar well-known new development relates to the chip size package (CSP), in which a single bare chip is applied to an intermediate carrier substrate that is hardly larger than the chip area, and in which the space-saving contact to the next architecture level directly below the chip area is used becomes.
  • CSP chip size package
  • the technologies of the printed circuit board manufacture enable wiring supports which allow the electrical through-plating from the chip side to the underside by means of through-plating holes which are relatively easy to produce. They are less advantageous with regard to the production of laterally small designs, in particular for multi-chip modules, since the wiring densities are too low.
  • vias in particular cannot be positioned precisely enough between the interconnect levels because of the shrinkage of the laminate materials. Uncertainties of typically up to 200 ⁇ m remain, which is made to fit by coarsening the structure around the Via (Land). Because of the shrinkage, high-density wiring carriers can only be realized if they are not produced on the inexpensive large panels, for example 600 x 600 mm, but on extremely small ones, for example 150 x 150 mm. This makes large-format production in circuit board technology as expensive as thin-film technology.
  • the technologies of thin-film production enable high wiring densities through their structurally fine processes and there are due to the solid carrier materials (the actual carrier for the multi-layer wiring consists of ceramic, silicon, glass or metal) no shrinkage problem.
  • the solid carrier materials the actual carrier for the multi-layer wiring consists of ceramic, silicon, glass or metal
  • other aspects of this technology are problematic, in particular the costly detours to be made when realizing the electrical connection from the carrier top to the carrier bottom, for example drilling or punching holes in the solid core materials, adjustment problems, metallizing the holes, etc.
  • the density the plated-through holes are limited by the substrate thickness and the technology used to produce the hole.
  • there is also a high risk of breakage of the carriers in the thin-film process which, moreover, does not allow a transition to inexpensive large-format production.
  • the present invention has for its object to provide an improved module of the type mentioned, in particular with a reduced overall height, and to provide a method for its production.
  • the object is achieved in a method of the type mentioned at the outset in that multilayer wiring with contact pads on its underside is applied only to the top of a plate-shaped wiring carrier made of solid material, so that IC or other electronic components are electrically and mechanically connected the assembly level of the multi layer wiring are connected, that the component side of the multi-layer wiring is provided with a hermetic housing adhering to its component-free areas, and that the solid carrier material is then removed again and the underside of the multi-layer wiring forming the underside of the module is exposed.
  • the invention achieves the desired improvements by not only the processes of the actual interconnect
  • ultra-thin modules can be produced, although on the one hand the advantages of thin-film technology, in particular the use of solid carrier materials or materials with high temperature stability (up to 400 ° C) remain, while on the other hand a high wiring density can be achieved without restrictions and can be produced with large-format panels, for example 400 x 400 mm.
  • process steps are advantageously saved.
  • a metallic wiring carrier 1 is shown, on the top of which the actual interconnect, i.e.
  • FIG. 1B shows a module in which, compared to FIG.
  • Multi-layer wiring 2 can form.
  • the customary molding compounds can be used, since these are compatible with the insulation materials used as the top layer of the multi-layer wiring 2, such as polyid, PBO, BCB or Ormocere, that is to say they are liable.
  • FIG. IC shows a module in which the next process step, the removal of the carrier material 1, has already been carried out. This can be done, for example, by dissolving the carrier material, in particular by wet chemical etching in one of the commercially available etching systems used, for example, in the highly integrated semiconductor technology.
  • the contact pads 6 are, of course, on the Un ⁇ underside of the multi-layer wiring 2, which are designed to provide 3 of the module with the contacts of the next higher module level via feedthroughs and connections to the conductor rail system the electrical connection of the components exposed.
  • cf. Figure ID for contacting the module solderable material, in particular solder balls 7, applied to the contact pads 6.
  • a passivation layer 15 can be provided for later easier testing of the module, cf. Figure IB.
  • z. B plastic as a carrier material into consideration.
  • FIGS. 2C to 2F show different variants.
  • FIG. 2C shows the result of the etching of pits 8 into the carrier material from the underside, so that the contact points, that is to say the contact pads 6, on the underside of the multilayer wiring 2 are exposed.
  • solderable material 9 eg SnPb
  • solder balls 7 can be electroplated or solder balls 7 using standard methods
  • FIGS. 3A to 3E show a process sequence in which a solder layer 10 is initially applied as an intermediate layer the carrier material is applied, which is then covered with a structured insulation layer 11. According to FIG. 3C, a structured metal level 12 is then produced, which according to FIG. 3D is provided with electronic components and is covered with a hermetic housing 4.
  • a solder layer 10 is initially applied as an intermediate layer the carrier material is applied, which is then covered with a structured insulation layer 11.
  • a structured metal level 12 is then produced, which according to FIG. 3D is provided with electronic components and is covered with a hermetic housing 4.
  • FIG. 3E shows the final result after heating the solder layer 10 and removing the wiring carrier 1, with harmless residues of the solder layer 10 remaining on the solder pads 6 and only there.
  • the metal islands 13 and 14 are connected to one another within the interconnect system of the multilayer wiring 2, which in this special case, which can be produced particularly cost-effectively, consists of only a single metal layer and an insulation layer 12 and 11.
  • a module results in the form of a BGA standard housing, the overall height of which is extremely low, since the remaining multilayer wiring 2, the actual interconnect, has an overall height of less than approximately 100 ⁇ m, usually even less than 60 ⁇ m. Since the chips 3 in the thinned form are typically approximately 300 ⁇ m high and the hermetic housing 4 again has a similar height, minimum housing heights (without
  • Balls of around 600 ⁇ m, while in laminate technology alone the well-known interconnect, i.e. the wiring carrier with multilayer wiring on top, is between 500 ⁇ m and 1000 ⁇ m high.

Abstract

The component side of the multi-layer metallization (2) adheres with its component-free sections to the hermetic housing (4) and the bottom side of the multi-layer metallization (2) having a height of less than 100 νm directly forms, that is, without requiring any additional metallization support, the bottom side of the module.

Description

Beschreibungdescription
Elektronisches Modul, insbesondere Multichipmodul, mit einer Mehrlagenverdrahtung und Verfahren zu seiner HerstellungElectronic module, in particular multichip module, with multi-layer wiring and method for its production
Die Erfindung betrifft ein elektronisches Modul, insbesondere Multichipmodul, mit einer Mehrlagenverdrahtung, auf deren Bestückungsseite wenigstens ein IC-Bauelement aufgebracht ist, wobei das Modul einseitig auf der Bestückungsseite mit einer hermetischen Gehäusung abgedeckt ist, und mit Kontaktpads an der Unterseite des Moduls, mit denen die Kontaktierung und Integration des Moduls in eine nächsthöhere Baugruppenebene herstellbar ist.The invention relates to an electronic module, in particular a multichip module, with multilayer wiring, on the component side of which at least one IC component is applied, the module being covered on one side on the component side with a hermetic housing, and with contact pads on the underside of the module, with which the contacting and integration of the module into a next higher module level can be established.
Die Erfindung betrifft außerdem ein Verfahren zur Herstellung eines elektronischen Moduls, insbesondere Multichipmoduls, mit einer Mehrlagenverdrahtung.The invention also relates to a method for producing an electronic module, in particular a multi-chip module, with multi-layer wiring.
Mit den zunehmend kleiner und schneller werdenden integrier- ten Schaltungen wächst die Herausforderung an ihre Ausbau und Verbindungstechnik. Seit einiger Zeit sind Multichip odule bekannt, durch die ein Zwischenträgersubstrat mit hoher Verdrahtungsdichte, HDI (High Density Interconnect) , als zusätzliche Ebene in die Hierarchie des Systemaufbaus eingeführt wird. Typisch dabei sind die Verwendung mehrerer ungehäuster Chips und eine hohe Flächenbelegung des Multichipsubstrats . Eine ähnliche bekannte Neuentwicklung betrifft das Chip-Size- Package (CSP) , bei dem ein einzelner ungehäuster Chip auf ein Zwischenträgersubstrat aufgebracht wird, das kaum größer als die Chipfläche ist, und bei dem dann die platzsparende Kontaktierung zur nächsten Architekturebene direkt unter der Chipfläche genutzt wird.With the increasingly smaller and faster integrated circuits, the challenge for their expansion and connection technology is growing. Multichip modules have been known for some time, by means of which an intermediate carrier substrate with high wiring density, HDI (High Density Interconnect), is introduced as an additional level in the hierarchy of the system structure. Typical of this are the use of several unhoused chips and a high area coverage of the multichip substrate. A similar well-known new development relates to the chip size package (CSP), in which a single bare chip is applied to an intermediate carrier substrate that is hardly larger than the chip area, and in which the space-saving contact to the next architecture level directly below the chip area is used becomes.
Die wesentlichen Leistungsmerkmale der heutigen Packages für Ein-Chip- oder Mehr-Chip-Anwendungen sind die laterale Abmessung, die Bauhöhe, die Wärmeabführung und der Pitch in der nächsten Architekturebene. Die Nutzung der bekannten Quad Fiat Pack (QFP) -Packages birgt neben dem relativ geringen Chipbedeckungsgrad (Chipfläche/Bauelementfläche) und der relativ hohen Bauform als weiteren Nachteil den Übergang zu extrem kleinen Pitches auf dem Motherboard bei hohem Pincount der Chips. Ebenfalls bekannt ist ein anderer Gehäusetyp, die Ball-Grid-Arrays (BGA) . Bei diesen bilden kleine Lötkugeln, die flächig in einem relativ groben Raster auf der Unterseite des Moduls aufgebracht sind, die Anschlüsse. Mit BGA- Bauformen läßt sich durch die flächige Anordnung der Kontakte die Problematik des Pitches entspannen, und die Bauhöhe prinzipiell verringern. Die Herstellung konventioneller Laminat- /Kunststoff-Interconnect führt jedoch insbesondere für hochdichte Verdrahtungen zu technischen Umwegen und unvorteilhaften Produkteigenschaften. Insgesamt stellt sich die derzeiti- ge Situation wie folgt dar:The main features of today's packages for one-chip or multi-chip applications are the lateral dimensions, the height, the heat dissipation and the pitch in the next architectural level. The use of the well-known quad In addition to the relatively low chip coverage (chip area / component area) and the relatively high design, Fiat Pack (QFP) packages also have the disadvantage of the transition to extremely small pitches on the motherboard with a high pin count of the chips. Another type of housing is also known, the ball grid arrays (BGA). In these, small solder balls, which are applied flat in a relatively coarse grid on the underside of the module, form the connections. With BGA designs, the problem of the pitch can be relaxed by the planar arrangement of the contacts, and the overall height can be reduced in principle. However, the production of conventional laminate / plastic interconnects leads to technical detours and unfavorable product properties, especially for high-density wiring. Overall, the current situation is as follows:
Die Technologien der Leiterplattenherstellung ermöglichen Verdrahtungsträger, welche die elektrische Durchkontaktierung von der Chipseite zur Unterseite mittels relativ einfach her- stellbarer Durchkontaktierungslöcher erlauben. Weniger vorteilhaft sind sie hinsichtlich der Herstellung lateral kleiner Bauformen, insbesondere für Mehrchipmodule, da die Verdrahtungsdichten zu gering sind. Außerdem können insbesondere Vias zwischen den Leiterbahnebenen wegen der Schrumpfung der Laminatmaterialien nicht exakt genug positioniert werden. Es verbleiben Unsicherheiten von typischerweise bis 200 μm, was durch Strukturvergröberung rund um die Via (Land) zur Passfähigkeit gebracht wird. Wegen der Schrumpfung sind hochdichte Verdrahtungsträger nur realisierbar, wenn nicht auf den ko- stengünstigen großen Panels, beispielsweise 600 x 600 mm, sondern auf extrem kleinen, beispielsweise 150 x 150 mm gefertigt wird. Damit ist die Großformatfertigung in Leiterplattentechnik vergleichbar kostenaufwendig wie die Dünnfilmtechnik.The technologies of the printed circuit board manufacture enable wiring supports which allow the electrical through-plating from the chip side to the underside by means of through-plating holes which are relatively easy to produce. They are less advantageous with regard to the production of laterally small designs, in particular for multi-chip modules, since the wiring densities are too low. In addition, vias in particular cannot be positioned precisely enough between the interconnect levels because of the shrinkage of the laminate materials. Uncertainties of typically up to 200 μm remain, which is made to fit by coarsening the structure around the Via (Land). Because of the shrinkage, high-density wiring carriers can only be realized if they are not produced on the inexpensive large panels, for example 600 x 600 mm, but on extremely small ones, for example 150 x 150 mm. This makes large-format production in circuit board technology as expensive as thin-film technology.
Die Technologien der Dünnfilmfertigung ermöglichen durch ihre strukturfeinen Verfahren hohe Verdrahtungsdichten und es gibt aufgrund der festen Trägermaterialien (der eigentliche Träger für die Mehrlagenverdrahtung besteht aus Keramik, Silizium, Glas oder Metall) kein Schrumpfungsproblem. Problematisch sind jedoch andere Aspekte dieser Technologie, insbesondere die bei der Realisierung der elektrischen Verbindung von der Trägeroberseite auf die Trägerunterseite zu gehenden kostenaufwendigen Umwege, beispielsweise Bohren oder Stanzen von Löchern in die festen Kernmaterialien, Justageprobleme, Metallisieren der Löcher, usw. Außerdem ist die Dichte der Durchkontaktierungen durch die Subtratdicke und die jeweilige Technologie zur Herstellung des Loches begrenzt. Generell besteht eine schlechte Kompatibilität der Technologie von Substratträgern mit Löchern einerseits und Prozessen der Dünnfilmtechnik, beispielsweise Spin Coating, andererseits. Schließlich besteht auch eine hohe Bruchgefahr der Träger im Dünnfilmprozeß, der im übrigen auch nicht ohne weiteres einen Übergang auf die kostengünstige Großformatfertigung erlaubt.The technologies of thin-film production enable high wiring densities through their structurally fine processes and there are due to the solid carrier materials (the actual carrier for the multi-layer wiring consists of ceramic, silicon, glass or metal) no shrinkage problem. However, other aspects of this technology are problematic, in particular the costly detours to be made when realizing the electrical connection from the carrier top to the carrier bottom, for example drilling or punching holes in the solid core materials, adjustment problems, metallizing the holes, etc. In addition, the density the plated-through holes are limited by the substrate thickness and the technology used to produce the hole. In general, there is poor compatibility of the technology of substrate carriers with holes on the one hand and processes of thin-film technology, for example spin coating, on the other. Finally, there is also a high risk of breakage of the carriers in the thin-film process, which, moreover, does not allow a transition to inexpensive large-format production.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, ein verbessertes Modul der eingangs genannten Art, insbesondere mit verringerter Bauhöhe, zu schaffen und ein Verfahren zu seiner Herstellung anzugeben.The present invention has for its object to provide an improved module of the type mentioned, in particular with a reduced overall height, and to provide a method for its production.
Diese Aufgabe wird bei einem Modul der eingangs genannten Art dadurch gelöst, daß die Bestückungsseite der Mehrlagenverdrahtung mit ihren bauelementefreien Bereichen an der hermetischen Gehäusung haftet, und daß die Unterseite der weniger als etwa 100 μm hohen Mehrlagenverdrahtung unmittelbar, also ohne zusätzlichen Verdrahtungsträger, die Unterseite des Mo- duls bildet.This object is achieved in a module of the type mentioned above in that the component side of the multilayer wiring adheres to the hermetic housing with its component-free areas, and that the underside of the less than approximately 100 μm high multilayer wiring directly, that is to say without additional wiring supports, the underside of the Module forms.
Die Aufgabe wird bei einem Verfahren der eingangs genannten Art dadurch gelöst, daß nur auf der Oberseite eines platten- förmigen Verdrahtungsträgers aus festem Material eine Mehrla- genverdrahtung mit Kontaktpads an ihrer Unterseite aufgebracht wird, daß IC- bzw. weitere elektronische Bauelemente elektrisch und mechanisch mit der Bestückungsebene der Mehr- lagenverdrahtung verbunden werden, daß die Bestückungsseite der Mehrlagenverdrahtung mit einer hermetischen, an ihren bauelementefreien Bereichen haftenden Gehäusung versehen wird, und daß anschließend das feste Trägermaterial wieder entfernt und die die Unterseite des Moduls bildende Unterseite der Mehrlagenverdrahtung freigelegt wird.The object is achieved in a method of the type mentioned at the outset in that multilayer wiring with contact pads on its underside is applied only to the top of a plate-shaped wiring carrier made of solid material, so that IC or other electronic components are electrically and mechanically connected the assembly level of the multi layer wiring are connected, that the component side of the multi-layer wiring is provided with a hermetic housing adhering to its component-free areas, and that the solid carrier material is then removed again and the underside of the multi-layer wiring forming the underside of the module is exposed.
Weiterbildungen der Erfindung sind Gegenstand von Unteransprüchen.Developments of the invention are the subject of dependent claims.
Die Erfindung wird nachfolgend anhand von Ausführungsbeispielen im Zusammenhang mit den Figuren der Zeichnung näher erläutert. Es zeigen:The invention is explained in more detail below on the basis of exemplary embodiments in connection with the figures of the drawing. Show it:
Figur 1A bis ID in geschnittener Seitenansicht aufeinanderfolgende Stadien des erfindungsgemäßen Herstellungsprozesses in einer ersten Variante,1A to ID in a sectional side view successive stages of the manufacturing process according to the invention in a first variant,
Figur 2A bis 2F in gleicher Darstellung eine andere Variante,2A to 2F in the same representation another variant,
Figur 3A bis 3E in gleicher Darstellung eine weitere Variante.Figure 3A to 3E in the same representation another variant.
Die Erfindung erreicht die angestrebten Verbesserungen, indem nicht nur die Prozesse der eigentlichen Interconnect-The invention achieves the desired improvements by not only the processes of the actual interconnect
Herstellung betrachtet werden, sondern der Gesamtprozeß zur Herstellung eines BGA-Standard-Gehäuses in die erfindungsgemäße Rationalisierung und Umstrukturierung der Prozeßfolgen und damit des Moduls selbst einbezogen werden. Erfindungsge- maß können ultradünne Module hergestellt werden, obwohl es einerseits bei der Nutzung der Vorteile der Dünnfilmtechnik, also insbesondere der Nutzung fester Trägermaterialien bzw. von Materialien mit hoher Temperaturstabilität (bis 400°C) bleibt, während andererseits eine hohe Verdrahtungsdichte un- eingeschränkt erreichbar ist und mit großformatigen Panels, beispielsweise 400 x 400 mm produziert werden kann. Außerdem kommt es vorteilhaft zur Einsparung von Prozeßschritten. In Figur 1A ist ein metallischer Verdrahtungsträger 1 dargestellt, auf dessen Oberseite der eigentliche Interconnect, also die Mehrlagenverdrahtung 2, die durch eine Sequenz von strukturierten Metallebenen gebildet ist, die durch Isolationsschichten elektrisch voneinander getrennt und zwischen denen über Durchleitungen gezielte elektrische Verbindungen hergestellt sind, bereits aufgebracht ist. Als Trägermaterial bieten sich beispielsweise Kupfer bzw. Aluminium an. Ent- scheidend ist, daß die Mehrlagenverdrahtung 2 tatsächlich nur auf der Trägeroberseite aufgebracht ist und daß keine Durchkontaktierungen von der Ober- auf die Unterseite des Verdrahtungsträgers 1 vorgenommen werden. Figur 1B zeigt ein Modul, bei dem gegenüber Figur 1A bereits zwei weitere Fertigungs- schritte vollzogen sind, nämlich das mechanische und elektrische Verbinden von einem oder mehreren Chips 3 und gegebenenfalls von weiteren elektronischen Bauelementen mit der Be- stückungsseite der Mehrlagenverdrahtung 2, beispielsweise durch Chip-and-Wire-Bond oder in Flip-Chip-Technik, und bei dem das bestückte System anschließend durch einseitiges Kunststoffumspritzen in die Form eines Standardpackage (Overmold) gebracht wurde, vgl. Gehäusung 4. Der größte Teil der Bestückungsfläche, also der Oberseite der Mehrlagenverdrahtung 2, ist bauelementefrei, so daß die aufgebrachte Ver- guß- bzw. Klebermasse 4 ausreichende Haftungsflachen 5 zurProduction are considered, but the overall process for the production of a BGA standard housing are included in the rationalization and restructuring of the process sequences and thus the module itself. According to the invention, ultra-thin modules can be produced, although on the one hand the advantages of thin-film technology, in particular the use of solid carrier materials or materials with high temperature stability (up to 400 ° C) remain, while on the other hand a high wiring density can be achieved without restrictions and can be produced with large-format panels, for example 400 x 400 mm. In addition, process steps are advantageously saved. In Figure 1A, a metallic wiring carrier 1 is shown, on the top of which the actual interconnect, i.e. the multilayer wiring 2, which is formed by a sequence of structured metal levels, which are electrically separated from one another by insulation layers and between which targeted electrical connections are made via passages is applied. Copper or aluminum, for example, are suitable as carrier materials. It is crucial that the multi-layer wiring 2 is actually only applied to the top of the carrier and that no through-plating is carried out from the top to the bottom of the wiring carrier 1. FIG. 1B shows a module in which, compared to FIG. 1A, two further production steps have already been carried out, namely the mechanical and electrical connection of one or more chips 3 and, if appropriate, of further electronic components to the component side of the multilayer wiring 2, for example by means of a chip -and-wire-bond or in flip-chip technology, and in which the assembled system was subsequently molded into the shape of a standard package (overmold) by plastic molding on one side, cf. Housing 4. The largest part of the assembly area, that is to say the upper side of the multilayer wiring 2, is component-free, so that the potting compound or adhesive compound 4 applied has sufficient adhesion areas 5 for it
Mehrlagenverdrahtung 2 hin bilden kann. Es können insbesondere die üblichen Moldrαassen eingesetzt werden, da diese sowieso mit den als oberste Schicht der Mehrlagenverdrahtung 2 eingesetzten Isolationmaterialien wie Polyi id, PBO, BCB oder Ormocere, kompatibel, das heißt haftungsfähig sind.Multi-layer wiring 2 can form. In particular, the customary molding compounds can be used, since these are compatible with the insulation materials used as the top layer of the multi-layer wiring 2, such as polyid, PBO, BCB or Ormocere, that is to say they are liable.
Figur IC zeigt ein Modul bei dem der nächste Prozeßschritt, das Entfernen des Trägermaterials 1, bereits vollzogen ist. Dies kann beispielsweise durch Auflösen des Trägermaterials, insbesondere durch naßchemisches Ätzen in einer der handelsüblichen, beispielsweise in der hochintegrierten Halbleitertechnologie eingesetzten Ätzanlagen vollzogen werden. Danach und dadurch sind natürlich auch die Kontaktpads 6 an der Un¬ terseite der Mehrlagenverdrahtung 2, die über Durchführungen und Verbindungen mit dem Leiterbahnsystem den elektrischen Anschluß der Bauelemente 3 des Moduls mit den Kontakten der nächsthöheren Baugruppenebene gewährleisten sollen, freigelegt. Üblicherweise wird anschließend, vgl. Figur ID, zur Kontaktierung des Moduls lötfähiges Material, insbesondere Lötkugeln 7, auf die Kontaktpads 6 aufgebracht. Eine Passi- vierungsschicht 15 kann zum späteren leichteren Testen des Moduls vorgesehen sein, vgl. Figur IB. Prinzipiell kommt auch z. B. Kunststoff als Trägermaterial in Betracht.FIG. IC shows a module in which the next process step, the removal of the carrier material 1, has already been carried out. This can be done, for example, by dissolving the carrier material, in particular by wet chemical etching in one of the commercially available etching systems used, for example, in the highly integrated semiconductor technology. After that and thereby the contact pads 6 are, of course, on the Un ¬ underside of the multi-layer wiring 2, which are designed to provide 3 of the module with the contacts of the next higher module level via feedthroughs and connections to the conductor rail system the electrical connection of the components exposed. Usually, cf. Figure ID, for contacting the module solderable material, in particular solder balls 7, applied to the contact pads 6. A passivation layer 15 can be provided for later easier testing of the module, cf. Figure IB. In principle, z. B. plastic as a carrier material into consideration.
Während Figur 2A und 2B mit den Herstellungsschritten gemäß Figur 1A und 1B übereinstimmen, zeigen Figuren 2C bis 2F ab- weichende Varianten. In Figur 2C ist das Ergebnis des Ätzens von Gruben 8 in das Trägermaterial von der Unterseite her dargestellt, so daß die Kontaktstellen, also die Kontaktpads 6 an der Unterseite der Mehrlagenverdrahtung 2 freigelegt werden. Anschließend kann mittels Galvanik lötfähiges Materi- al 9 (z. B. SnPb) oder mit Standardverfahren Lötkugeln 72A and 2B correspond to the manufacturing steps according to FIGS. 1A and 1B, FIGS. 2C to 2F show different variants. FIG. 2C shows the result of the etching of pits 8 into the carrier material from the underside, so that the contact points, that is to say the contact pads 6, on the underside of the multilayer wiring 2 are exposed. Subsequently, solderable material 9 (eg SnPb) can be electroplated or solder balls 7 using standard methods
(Balls) in die Gruben 8 eingebracht werden, vgl. Figur ID. Erst danach erfolgt das Entfernen des Verdrahtungsträgers 1, wobei dann je nach Wahl des Lötmaterials 8, 9 als Endergebnis Module gemäß Figur 2E oder 2F resultieren.(Balls) are introduced into the pits 8, cf. Figure ID. Only then is the removal of the wiring carrier 1, whereby depending on the choice of the soldering material 8, 9, the end result is modules according to FIG. 2E or 2F.
Als Alternative zum zuvor beschriebenen Entfernen des Trägermaterials durch Auflösen ist auch ein Ablösen des Verdrahtungsträgers 1 von der Mehrlagenverdrahtung 2 eine geeignete Möglichkeit der Separierung. Diese kann insbesondere durch das Auftragen einer Zwischenschicht zwischen Mehrlagenverdrahtung 2 und Verdrahtungsträger 1 realisiert werden. Gut geeignet ist beispielsweise ein niedrigschmelzendes Material, beispielsweise Lot, oder ein Kleber, welcher am Ende des Moldprozesses, beispielsweise durch einen zusätzlichen Wärme- schritt, die Trennung des Moduls vom Verdrahtungsträger 1 erlaubt. In Figur 3A bis 3E ist eine Prozeßfolge dargestellt, bei der zunächst als Zwischenschicht eine Lotschicht 10 auf das Trägermaterial aufgebracht wird, die dann mit einer strukturierten Isolationsschicht 11 abgedeckt wird. Gemäß Figur 3C wird anschließend eine strukturierte Metallebene 12 hergestellt, die gemäß Figur 3D mit elektronischen Bauelemen- ten versehen und mit einer hermetischen Gehäusung 4 abgedeckt wird. Figur 3E zeigt das Endergebnis nach Erwärmen der Lotschicht 10 und Entfernen des Verdrahtungsträgers 1, wobei an den Lotpads 6, und nur dort, noch unschädliche Reste der Lotschicht 10 zurückgeblieben sind. Innerhalb des Leiterbahnsy- stems der Mehrlagenverdrahtung 2, die in diesem besonders kostengünstig herstellbaren Sonderfall nur aus einer einzigen Metall- und einer Isolationsschicht 12 und 11 besteht, sind die Metallinseln 13 und 14 miteinander verbunden. Bei Einsatz eines Klebers als Zwischenschicht sollte darauf geachtet wer- den, daß dieser möglichst rückstandslos ist bzw. es sollte eine Nachreinigung vorgesehen werden.As an alternative to the previously described removal of the carrier material by dissolving, detaching the wiring carrier 1 from the multilayer wiring 2 is also a suitable possibility of separation. This can be achieved in particular by applying an intermediate layer between multilayer wiring 2 and wiring carrier 1. A low-melting material, for example solder, or an adhesive, which allows the module to be separated from the wiring carrier 1 at the end of the molding process, for example by an additional heating step, is particularly suitable. FIGS. 3A to 3E show a process sequence in which a solder layer 10 is initially applied as an intermediate layer the carrier material is applied, which is then covered with a structured insulation layer 11. According to FIG. 3C, a structured metal level 12 is then produced, which according to FIG. 3D is provided with electronic components and is covered with a hermetic housing 4. FIG. 3E shows the final result after heating the solder layer 10 and removing the wiring carrier 1, with harmless residues of the solder layer 10 remaining on the solder pads 6 and only there. The metal islands 13 and 14 are connected to one another within the interconnect system of the multilayer wiring 2, which in this special case, which can be produced particularly cost-effectively, consists of only a single metal layer and an insulation layer 12 and 11. When using an adhesive as an intermediate layer, care should be taken to ensure that it is as residue-free as possible, or that subsequent cleaning should be provided.
Erfindungsgemäß resultiert ein Modul in Form eines BGA- Standard-Gehäuses, dessen Aufbauhöhe extrem niedrig ist, da die allein verbleibende Mehrlagenverdrahtung 2, der eigentliche Interconnect, eine Aufbauhöhe von weniger als etwa 100 μm, meist sogar von weniger als 60 μm, hat. Da die Chips 3 in abgedünnter Form typischerweise ca. 300 μm hoch sind und die hermetische Gehäusung 4 noch mal eine ähnliche Höhe aus- macht, sind erfindungsgemäß minimale Gehäusehöhen (ohneAccording to the invention, a module results in the form of a BGA standard housing, the overall height of which is extremely low, since the remaining multilayer wiring 2, the actual interconnect, has an overall height of less than approximately 100 μm, usually even less than 60 μm. Since the chips 3 in the thinned form are typically approximately 300 μm high and the hermetic housing 4 again has a similar height, minimum housing heights (without
Balls) von etwa 600 μm erreichbar, während beispielsweise in Laminattechnologie allein der bekannte Interconnect, das heißt der Verdrahtungsträger mit darauf liegender Mehrlagenverdrahtung, zwischen 500 μm und 1000 μm hoch ist. Balls) of around 600 μm, while in laminate technology alone the well-known interconnect, i.e. the wiring carrier with multilayer wiring on top, is between 500 μm and 1000 μm high.

Claims

Patentansprüche claims
1. Elektronisches Modul, insbesondere Multichipmodul, mit einer Mehrlagenverdrahtung, auf deren Bestückungsseite wenig- stens ein IC-Bauelement aufgebracht ist, wobei das Modul einseitig auf der Bestückungsseite mit einer hermetischen Gehäusung abgedeckt ist, und mit Kontaktpads an der Unterseite des Moduls, mit denen die Kontaktierung und Integration des Moduls in eine nächsthöhere Baugruppenebene herstellbar ist, dadurch gekennzeichnet, daß die Bestückungsseite der Mehrlagenverdrahtung (2) mit ihrem bauelementefreien Bereichen an der hermetischen Gehäusung (4) haftet, und daß die Unterseite der weniger als etwa 100 μm hohen Mehrlagenverdrahtung (2) unmittelbar, also ohne zusätzlichen Verdrahtungsträger (1), die Unterseite des Moduls bildet.1. Electronic module, in particular multichip module, with multilayer wiring, on the component side of which at least one IC component is applied, the module being covered on one side on the component side with a hermetic housing, and with contact pads on the underside of the module with which the module can be contacted and integrated into a next higher component level, characterized in that the component side of the multilayer wiring (2) adheres to the hermetic housing (4) with its component-free areas, and that the underside of the less than approximately 100 μm high multilayer wiring ( 2) forms the underside of the module directly, i.e. without additional wiring support (1).
2. Modul nach Anspruch 1, dadurch gekennzeichnet, daß die Mehrlagenverdrahtung (2) durch eine Sequenz von strukturierten Metallebenen (12) gebildet ist, die durch Isolationsschichten (11) elektrisch voneinander getrennt und zwischen denen über Durchleitungen gezielt elektrische Ver- bindungen hergestellt sind.2. Module according to claim 1, characterized in that the multi-layer wiring (2) is formed by a sequence of structured metal levels (12) which are electrically separated from one another by insulation layers (11) and between which electrical connections are made in a targeted manner via passages.
3 . Modul nach Anspruch 1 oder 2 , d a d u r c h g e k e n n z e i c h n e t , daß für die Kontaktierung auf die nächste Baugruppenebene lötfähiges Material (7, 9), insbesondere Lötkugeln (7), auf die Kontaktpads (6) auf der Unterseite der Mehrlagenverdrahtung (2) aufgebracht sind, die über Durchleitungen mit der Bestückungsebene elektrisch verbunden sind.3rd Module according to claim 1 or 2, characterized in that for contacting to the next assembly level, solderable material (7, 9), in particular solder balls (7), are applied to the contact pads (6) on the underside of the multilayer wiring (2), which are connected via Feedthroughs are electrically connected to the assembly level.
4. Verfahren zur Herstellung eines elektronischen Moduls nach Anspruch 1, dadurch gekennzeichnet, - daß nur auf der Oberseite eines plattenförmigen Verdrahtungsträgers (1) aus festem Material eine Mehrlagenverdrahtung (2) mit Kontaktpads (6) an ihrer Unterseite aufgebracht wird, - daß IC- bzw. weitere elektronische Bauelemente (3) elektrisch und mechanisch mit der Bestückungsebene der Mehrlagenverdrahtung (2) verbunden werden,4. A method for producing an electronic module according to claim 1, characterized in that - That only on the top of a plate-shaped wiring carrier (1) made of solid material, a multilayer wiring (2) with contact pads (6) is applied to its underside, - that IC or other electronic components (3) electrically and mechanically with the assembly level of Multilayer wiring (2) can be connected,
- daß die Bestückungsseite der Mehrlagenverdrahtung (2) mit einer hermetischen, an ihren bauelementefreien Bereichen haftenden Gehäusung (4) versehen wird,- That the component side of the multi-layer wiring (2) is provided with a hermetic housing (4) adhering to its component-free areas,
- und daß anschließend das feste Trägermaterial wieder entfernt und die die Unterseite des Moduls bildende Unterseite der Mehrlagenverdrahtung (2) freigelegt wird.- And that then the solid carrier material is removed again and the underside of the module forming the underside of the multilayer wiring (2) is exposed.
5. Verfahren nach Anspruch 4, dadurch gekennzeichnet, daß vor Entfernen des insbesondere metallischen Trägermaterials in unterhalb der Kontaktpads (6) liegenden Bereichen, von der Unterseite her Gruben (8) in den Verdrahtungsträger (1) geätzt werden, in die anschließend lötfähiges Material (7, 9) eingebracht wird.5. The method according to claim 4, characterized in that before removal of the in particular metallic carrier material in areas below the contact pads (6), from the underside pits (8) in the wiring carrier (1) are etched, into which subsequently solderable material ( 7, 9) is introduced.
6. Verfahren nach Anspruch 4 oder 5, dadurch gekennzeichnet, daß das Entfernen des insbesondere metallischen Trägermaterials durch Auflösen desselben erfolgt.6. The method according to claim 4 or 5, characterized in that the removal of the particular metallic carrier material is carried out by dissolving the same.
7. Verfahren nach Anspruch 6, dadurch gekennzeichnet, daß das Auflösen durch naßchemisches Ätzen erfolgt.7. The method according to claim 6, characterized in that the dissolution takes place by wet chemical etching.
8. Verfahren nach Anspruch 4 oder 5, dadurch gekennzeichnet, daß das Entfernen des Trägermaterials durch Ablösen des Ver- drahtungsträgers (1) von der Mehrlagenverdrahtung (2) erfolgt. 8. The method according to claim 4 or 5, characterized in that the removal of the carrier material is carried out by detaching the wiring carrier (1) from the multi-layer wiring (2).
9. Verfahren nach Anspruch 8, dadurch gekennzeichnet, daß bei der Herstellung des Moduls auf dem Verdrahtungsträger (1) zunächst eine die spätere Ablösung erleichternde Zwi- schenschicht (10) und erst anschließend, darauf, die Mehrlagenverdrahtung (2) aufgebracht wird.9. The method according to claim 8, characterized in that in the manufacture of the module on the wiring carrier (1) first an intermediate layer (10) which facilitates subsequent detachment and only then, thereon, the multilayer wiring (2) is applied.
10. Verfahren nach Anspruch 9, dadurch gekennzeichnet, daß als Zwischenschicht (10) ein niedrigschmelzendes Material, insbesondere Lot, aufgebracht wird.10. The method according to claim 9, characterized in that a low-melting material, in particular solder, is applied as the intermediate layer (10).
11. Verfahren nach Anspruch 9, dadurch gekennzeichnet, daß als Zwischenschicht ein Kleber aufgebracht wird, der später durch einen zusätzlichen Wärmeschritt die Trennung der Mehrlagenverdrahtung (2) vom Verdrahtungsträger (1) erlaubt.11. The method according to claim 9, characterized in that an adhesive is applied as an intermediate layer, which later allows the separation of the multilayer wiring (2) from the wiring carrier (1) by an additional heat step.
12. Verfahren nach einem der Ansprüche 4 bis 11, dadurch gekennzeichnet, daß die Herstellung der hermetischen Gehäusung (4) durch Kunststoffumspritzen oder durch Bedecken mit Klebemasse erfolgt. 12. The method according to any one of claims 4 to 11, characterized in that the manufacture of the hermetic housing (4) is carried out by extrusion coating or by covering with adhesive.
PCT/DE1999/003247 1998-10-09 1999-10-08 Electronic module, especially a multichip module, with multi-layer metallization and corresponding production method WO2000022668A1 (en)

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JP2000576488A JP2002527906A (en) 1998-10-09 1999-10-08 Electronic module, especially multi-chip module having multilayer metal wiring layer and method of manufacturing the same

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DE19846662.5 1998-10-09
DE19846662A DE19846662A1 (en) 1998-10-09 1998-10-09 Electronic module used in the production of high density interconnects and quad flat pack packages has the assembly side of the wiring adhered to a hermetic housing

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JP2002527906A (en) 2002-08-27

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