WO2000024144A1 - Method and apparatus for de-jittering asynchronous data transfer delay - Google Patents

Method and apparatus for de-jittering asynchronous data transfer delay Download PDF

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Publication number
WO2000024144A1
WO2000024144A1 PCT/US1999/024277 US9924277W WO0024144A1 WO 2000024144 A1 WO2000024144 A1 WO 2000024144A1 US 9924277 W US9924277 W US 9924277W WO 0024144 A1 WO0024144 A1 WO 0024144A1
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WIPO (PCT)
Prior art keywords
buffer
clock signal
output clock
time
rate
Prior art date
Application number
PCT/US1999/024277
Other languages
French (fr)
Inventor
Chi-Ping Nee
Original Assignee
Tiernan Communications, Inc.
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Filing date
Publication date
Application filed by Tiernan Communications, Inc. filed Critical Tiernan Communications, Inc.
Priority to AU65193/99A priority Critical patent/AU6519399A/en
Publication of WO2000024144A1 publication Critical patent/WO2000024144A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5682—Threshold; Watermark

Definitions

  • a synchronous multiplexing scheme having N inputs and one output usually divides the output into N time slots. Each input is periodically transmitted in an assigned time slot.
  • a receiver can predict that the data of a particular channel will arrive every N time slots, and the clock recovery circuitry can be designed accordingly.
  • Variation in the arrival time of the data at the receiver is referred to as jitter.
  • the jitter is in general constrained to fractions of a bit interval or at most several bit intervals. The predictable arrival time found in synchronous multiplexing fails to hold true in asynchronous transfer mode (ATM) or asynchronous multiplexing.
  • ATM synchronous transfer mode
  • the output is also divided into several time slots.
  • the data in each time slot is called a cell or a packet.
  • the assignment of time slots to inputs is no longer fixed. Instead, a header with a label is placed in each cell or packet to associate the cell or packet with a particular channel.
  • the time slots are dynamically assigned to any input that is ready for transmission.
  • asynchronous multiplexing also introduces greater jitter than occurs with synchronous multiplexing. Every time an input misses one time slot, it has to wait for at least one additional time slot before it can be transmitted. Since there exists more than one multiplexing before a cell or packet is delivered to the destination receiver, the end-to-end or transfer delay jitter may range from one to many time slots. Because of the variation in such jitter, the corresponding clock recovery circuitry for asynchronous multiplexing is more complex.
  • One approach to clock recovery in the ATM environment includes a time stamp with the cell or packet.
  • processing the time stamps requires fast and complex hardware, especially when the data rate is relatively high (e.g., broadband video).
  • the present invention uses a buffer-level based, nonlinear, second order phase-lock-loop (PLL) approach to synchronize cells or packets which arrive having bounded but arbitrarily distributed packet transfer delay variation due to asynchronous transfer mode (ATM) or asynchronous multiplexing.
  • PLL phase-lock-loop
  • the arrival of such cells or packets can be de-jittered to a Constant Bit Rate (CBR) service with very low time jitter.
  • CBR Constant Bit Rate
  • a circuit for controlling clock timing at a receiver that receives asynchronous data includes a first buffer, a second buffer and a clock recovery unit.
  • the first buffer has an input for receiving asynchronous data and an output.
  • the second buffer has an input coupled to the output of the first buffer and an output.
  • the clock recovery unit monitors the buffer level of the first buffer and the buffer level of the second buffer and controls clock timing for the first and second buffers in response to the first and second buffer levels, respectively.
  • the clock recovery unit includes means for generating a first output clock signal coupled to the first buffer and means for generating a second output clock signal coupled to the second buffer.
  • Clock timing is controlled by adjusting the rate of the first output clock signal if the first buffer level is outside a range defined by a first upper bound and a first lower bound.
  • the rate of the second output clock signal can be adjusted if the second buffer level is outside a second range defined by a second upper bound and a second lower bound.
  • the clock recovery unit adjusts the first upper and first lower bounds in the same direction as the adjustment of the rate of the first output clock signal.
  • the circuit operates in a transient state and a steady state. The clock recovery unit declares the steady state if the first or second range is exceeded in opposite directions consecutively.
  • the circuit further includes a reassembly unit coupled between the first and second buffers for reassembling received packets or cells into higher layer protocol data units.
  • the clock recovery unit further includes means for generating a third output clock signal coupled to the reassembly unit. Clock timing is further controlled by adjusting the rate of the third output clock signal in relation to the first output clock signal.
  • FIG. 1 is a schematic block diagram of an embodiment of a clock recovery circuit.
  • FIG. 2 is a chart illustrating buffer level changes with respect to a time index for the circuit of FIG. 1.
  • FIG. 3 is a signal timing diagram corresponding to a direct digital synthesizer used to generate clock signals in the circuit of FIG. 1.
  • FIG. 4 is a schematic block diagram of a second embodiment of a clock recovery circuit.
  • FIG. 1 shows a block diagram of a clock recovery circuit 100 for use in a receiver of a communication system which uses asynchronous multiplexing or ATM.
  • the circuit 100 is a double-buffer, double-PLL (i.e., second order) which has better performance and is more robust than known one buffer, single-PLL designs.
  • the circuit 100 includes first and second buffers 102, 104, respectively, and clock recovery unit 106.
  • the clock recovery unit 106 is used to de-jitter cell or packet transfer delay variation due to ATM or asynchronous multiplexing.
  • the clock recovery unit generates two clocks: CLKl 105 and CLK2 11 1.
  • the clock signal CLKl is the byte or bit clock that extract bytes or bits from first buffer 102.
  • the clock signal CLK2 is the byte or bit clock that extracts bytes or bits from second buffer 104.
  • an ATM cell or asynchronously multiplexed packet arriving on line 101 is input to first buffer 102.
  • the data in first buffer 102 is cascaded through the second buffer 104 on line 107 and extracted from second buffer 104 on line 113 as a constant bit rate (CBR) flow with low jitter.
  • clock recovery unit generates clock signals CLKl and CLK2 by monitoring the buffer level of first and second buffers 102, 104, respectively, on corresponding lines 103, 109.
  • clock signal CLKl is updated according to
  • clock signal CLK2 is updated according to
  • the foregoing algorithm operates to update or adjust the clock rate when the buffer level hits an upper or lower bound; otherwise, no rate change is required. It can be seen that the adjustment algorithm is nonlinear by referring to the buffer level chart shown in FIG. 2.
  • the chart shows the buffer level B( ) over time index / and can illustrate the behavior of either buffer 102, 104 (FIG. 1 ) in accordance with update equations (Eq. 2) and (Eq. 4).
  • the buffer level is given as B(/ a ) and there exists an upper bound UBa and a lower bound LBa.
  • the upper and lower bounds form a range equal to twice the threshold TH.
  • the upper bound UBa is reached with buffer level B(/ b ) and the clock rate is adjusted according to the update equation (Eq. 2) or (Eq. 4).
  • the clock rate is updated, the upper and lower bounds are also adjusted.
  • the new upper and lower bounds are given as UBb and LBb, respectively.
  • the thresholds TH,, TH 2 and parameters K,, K 2 can be pre-defined according to the data rate or trained by the arrival of cells or packets.
  • the clock recovery circuit 100 (FIG. 1) can be configured to determine whether clock recovery is operating in either a transient state or steady state. If the clock recovery is in the transient state, thresholds TH,, TH 2 can be decreased or parameters K,, K 2 can be increased. This adjustment can be done in order to move more quickly to a steady state. When the clock recovery is in the steady state, thresholds TH,, TH 2 can be increased or parameters K,, K 2 can be decreased.
  • the steady state can be declared on the basis of observing two consecutive events that satisfy equation (Eq. 1) or equation (Eq. 3). That is, if one event reaches an upper bound, meaning
  • the clock recovery unit 106 includes a conventional direct digital synthesizer (DDS) for generating the clock signals CLKl, CLK2.
  • DDS direct digital synthesizer
  • the DDS adjusts the corresponding value N to reflect a new estimated output clock rate.
  • the amount of adjustment ⁇ N can be computed by
  • K is a constant
  • TH is a threshold
  • ⁇ t 0 is the elapsed time during the transient state
  • ⁇ t is the elapsed time between two clock adjustments due to the buffer level reaching the upper or lower bounds.
  • a higher layer protocol data unit may be segmented into more than one cells or packets.
  • a reassembly function is then necessary in the receiver side to reassemble the cells or packets back into the corresponding PDU.
  • FIG. 4 an embodiment of a circuit 200 is shown in FIG. 4 which includes a reassembly unit 108 coupled between first and second buffers 102, 104, respectively.
  • clock recovery unit 106A generates three clock signals: CLKl 105, CLK2 1 11 and CLK3 115.
  • Clock signals CLKl and CLK2 provide the same clock functions as described above with respect to the first and second buffers shown in FIG. 1.
  • clock signal CLK3 is the byte or bit clock that extracts bytes or bits from reassembly unit 108 into second buffer 104.
  • the ratio of cells or packets to a PDU is usually fixed. Let this ratio be defined as p.
  • the generation and updating of clock signals CLKl and CLK2 in circuit 200 accordingly follows from the foregoing equations (Eq. 1), (Eq. 2), (Eq. 3), (Eq. 4) and (Eq. 5).
  • the buffers 102, 104 can be replaced by one physical buffer.
  • buffers 102, 104 become "virtual buffers".
  • an inter- buffer transfer i.e., any byte output from the first buffer 102 into second buffer 104, does not leave the actual physical buffer. Rather, only the respective buffer levels of buffers 102, 104 are changed.

Abstract

A buffer-level based, nonlinear, second order phase-lock-loop (PLL) approach to synchronizing cells or packets which arrive having bounded but arbitrarily distributed packet transfer delay variation due to asynchronous transfer mode (ATM) or asynchronous multiplexing is disclosed. A recovery circuit for controlling clock timing at a receiver that receives asynchronous data includes a pair of cascaded buffers and a clock recovery unit. The clock recovery unit monitors the buffer level of the first buffer and the buffer level of the second buffer and controls clock timing for the first and second buffers in response to the first and second buffer levels, respectively.

Description

METHOD AND APPARATUS FOR DE-JITTERING ASYNCHRONOUS DATA TRANSFER DELAY
BACKGROUND OF THE INVENTION
Clock and data recovery approaches in communication systems differ depending on whether data is transmitted synchronously or asynchronously. A synchronous multiplexing scheme having N inputs and one output usually divides the output into N time slots. Each input is periodically transmitted in an assigned time slot. With such a scheme, a receiver can predict that the data of a particular channel will arrive every N time slots, and the clock recovery circuitry can be designed accordingly. Variation in the arrival time of the data at the receiver is referred to as jitter. In the synchronous multiplexing scheme the jitter is in general constrained to fractions of a bit interval or at most several bit intervals. The predictable arrival time found in synchronous multiplexing fails to hold true in asynchronous transfer mode (ATM) or asynchronous multiplexing. In ATM or asynchronous multiplexing, the output is also divided into several time slots. The data in each time slot is called a cell or a packet. The assignment of time slots to inputs is no longer fixed. Instead, a header with a label is placed in each cell or packet to associate the cell or packet with a particular channel. The time slots are dynamically assigned to any input that is ready for transmission.
Unfortunately, asynchronous multiplexing also introduces greater jitter than occurs with synchronous multiplexing. Every time an input misses one time slot, it has to wait for at least one additional time slot before it can be transmitted. Since there exists more than one multiplexing before a cell or packet is delivered to the destination receiver, the end-to-end or transfer delay jitter may range from one to many time slots. Because of the variation in such jitter, the corresponding clock recovery circuitry for asynchronous multiplexing is more complex.
One approach to clock recovery in the ATM environment includes a time stamp with the cell or packet. However, processing the time stamps requires fast and complex hardware, especially when the data rate is relatively high (e.g., broadband video).
Other known approaches smooth or filter the jitter by monitoring the level of a receive data buffer each time a packet is removed to control clock recovery circuitry. Such approaches may use a linear phase locked loop (PLL) to adjust frequency offset between a transmitter and the receiver. However, such approaches assume that the maximum variation in the cell or packet transfer delay is no more than TA/2 where TA is the mean arrival time between cells or packets. Unfortunately, the performance of these schemes degrades when delay is greater than TA/2. A robust and high performance clock recovery scheme is desired which can be used with cell or packet transfer delay jitter that is arbitrarily distributed but bounded.
SUMMARY OF THE INVENTION
The present invention uses a buffer-level based, nonlinear, second order phase-lock-loop (PLL) approach to synchronize cells or packets which arrive having bounded but arbitrarily distributed packet transfer delay variation due to asynchronous transfer mode (ATM) or asynchronous multiplexing. The arrival of such cells or packets can be de-jittered to a Constant Bit Rate (CBR) service with very low time jitter.
Accordingly, a circuit for controlling clock timing at a receiver that receives asynchronous data includes a first buffer, a second buffer and a clock recovery unit. The first buffer has an input for receiving asynchronous data and an output. The second buffer has an input coupled to the output of the first buffer and an output. The clock recovery unit monitors the buffer level of the first buffer and the buffer level of the second buffer and controls clock timing for the first and second buffers in response to the first and second buffer levels, respectively. The clock recovery unit includes means for generating a first output clock signal coupled to the first buffer and means for generating a second output clock signal coupled to the second buffer. Clock timing is controlled by adjusting the rate of the first output clock signal if the first buffer level is outside a range defined by a first upper bound and a first lower bound. Likewise, the rate of the second output clock signal can be adjusted if the second buffer level is outside a second range defined by a second upper bound and a second lower bound.
According to an aspect, the clock recovery unit adjusts the first upper and first lower bounds in the same direction as the adjustment of the rate of the first output clock signal. According to another aspect, the circuit operates in a transient state and a steady state. The clock recovery unit declares the steady state if the first or second range is exceeded in opposite directions consecutively.
According to yet another aspect, the circuit further includes a reassembly unit coupled between the first and second buffers for reassembling received packets or cells into higher layer protocol data units. The clock recovery unit further includes means for generating a third output clock signal coupled to the reassembly unit. Clock timing is further controlled by adjusting the rate of the third output clock signal in relation to the first output clock signal.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
FIG. 1 is a schematic block diagram of an embodiment of a clock recovery circuit.
FIG. 2 is a chart illustrating buffer level changes with respect to a time index for the circuit of FIG. 1.
FIG. 3 is a signal timing diagram corresponding to a direct digital synthesizer used to generate clock signals in the circuit of FIG. 1.
FIG. 4 is a schematic block diagram of a second embodiment of a clock recovery circuit.
DETAILED DESCRIPTION OF THE INVENTION
The invention is now described with reference to preferred embodiments. FIG. 1 shows a block diagram of a clock recovery circuit 100 for use in a receiver of a communication system which uses asynchronous multiplexing or ATM. The circuit 100 is a double-buffer, double-PLL (i.e., second order) which has better performance and is more robust than known one buffer, single-PLL designs. The circuit 100 includes first and second buffers 102, 104, respectively, and clock recovery unit 106. The clock recovery unit 106 is used to de-jitter cell or packet transfer delay variation due to ATM or asynchronous multiplexing. The clock recovery unit generates two clocks: CLKl 105 and CLK2 11 1. The clock signal CLKl is the byte or bit clock that extract bytes or bits from first buffer 102. Likewise, the clock signal CLK2 is the byte or bit clock that extracts bytes or bits from second buffer 104.
In operation, an ATM cell or asynchronously multiplexed packet arriving on line 101 is input to first buffer 102. The data in first buffer 102 is cascaded through the second buffer 104 on line 107 and extracted from second buffer 104 on line 113 as a constant bit rate (CBR) flow with low jitter. As described further herein, clock recovery unit generates clock signals CLKl and CLK2 by monitoring the buffer level of first and second buffers 102, 104, respectively, on corresponding lines 103, 109.
A nonlinear operation of the circuit 100 is now described. Let i=0, 1, ... be the time index of the zth cell or packet arrival on line 101. Likewise, let k=0, 1, ... be the time index of the Mi cell or packet on line 107. The clock rates of CLKl and CLK2 are denoted as r,(i) and r2(k), respectively. Suppose the buffer level of first buffer 102 is given as B,(i) and the buffer level of second buffer 104 is given as B2(k). There are several ways in which clock recovery unit 106 can update r,(i) and r2(k) according to B,(i) and B2(k), respectively. In one embodiment, two thresholds TH,, TH2 and two parameters Kb K2 are chosen. If
I B.O - B.O'J ^ TH, (Eq. l)
where i' is the time when the clock signal CLKl was last adjusted, i > i1 and Vj, I B,(i') - B,(j) | < TH, , then clock signal CLKl is updated according to
•B ( i ) " B ( i 1) r ( i ) = r ( i ;) + K ■ — 1 (Eq. 2) l l l i - i ' Similarly, if
| B2(k) - B2(k') | > TH2 (Eq. 3)
where k' is the time when the clock signal CLK2 was last adjusted, k > k' and Vm, | B2(k') - B2(m) | < TH2 , then clock signal CLK2 is updated according to
B2 ( k) - B2 ( k ') Λ r2 ( k) = r2 ( k') + • -? ± (Eq. 4)
2 2 2 k - k1
The foregoing algorithm operates to update or adjust the clock rate when the buffer level hits an upper or lower bound; otherwise, no rate change is required. It can be seen that the adjustment algorithm is nonlinear by referring to the buffer level chart shown in FIG. 2. The chart shows the buffer level B( ) over time index / and can illustrate the behavior of either buffer 102, 104 (FIG. 1 ) in accordance with update equations (Eq. 2) and (Eq. 4).
At time /a, the buffer level is given as B(/a) and there exists an upper bound UBa and a lower bound LBa. The upper and lower bounds form a range equal to twice the threshold TH. Up until time lb, no rate change occurs since the buffer level B(/) remains between the upper and lower bounds UBa. LBa, respectively. At time lb, the upper bound UBa is reached with buffer level B(/b) and the clock rate is adjusted according to the update equation (Eq. 2) or (Eq. 4). When the clock rate is updated, the upper and lower bounds are also adjusted. Thus, the new upper and lower bounds are given as UBb and LBb, respectively. Between times /b and /c, again no rate change occurs since the buffer level B(/) remains between the upper and lower bounds UBb, LBb. However, at time /c, the lower bound LBb is reached and the clock rate is again adjusted. Likewise, the upper and lower bounds are adjusted to new upper and lower bounds UBc. LBc, respectively.
In another embodiment, equations (Eq. 1) and (Eq. 2) can be replaced by ^ i ) = ^ ( 0 ) + ^ - [ 8^ 1 ) - 5, ( 0 ) ] (Eq.5)
where r,(0) is an initial clock rate for clock signal CLKl and B,(0) is the corresponding initial buffer level. In this embodiment, the update of the clock signal CLKl is linear. However, the update of clock signal CLK2 is still according to equations (Eq. 3) and (Eq. 4).
The thresholds TH,, TH2 and parameters K,, K2 can be pre-defined according to the data rate or trained by the arrival of cells or packets. In an embodiment, the clock recovery circuit 100 (FIG. 1) can be configured to determine whether clock recovery is operating in either a transient state or steady state. If the clock recovery is in the transient state, thresholds TH,, TH2 can be decreased or parameters K,, K2 can be increased. This adjustment can be done in order to move more quickly to a steady state. When the clock recovery is in the steady state, thresholds TH,, TH2 can be increased or parameters K,, K2 can be decreased. The steady state can be declared on the basis of observing two consecutive events that satisfy equation (Eq. 1) or equation (Eq. 3). That is, if one event reaches an upper bound, meaning
B1(i) > B,(i') + TH, or B2(k) > B2(k') + TH2 , and the other event reaches the corresponding lower bound, meaning
B,(i) < BI(i') - TH, or B2(k) < B2(k') - TH2 , then a steady state can be declared. On the other hand, if two consecutive events both reach the upper bound or lower bound, the transient state can be declared.
In an embodiment, the clock recovery unit 106 includes a conventional direct digital synthesizer (DDS) for generating the clock signals CLKl, CLK2. The DDS uses an accumulator and two inputs M and N. Initially, M-l is loaded to the accumulator. As shown in the signal timing diagram of FIG. 3, at every clock cycle of an internal clock CLK (e.g., 33 MHZ), the accumulator is subtracted by N modulo M. When the accumulator reaches roll-over an output pulse is generated, shown in FIG. 3 as the signal designated OutputClk. In the diagram the values M=l 1 and N=3 are used for example purposes. In the steady state operation as described above, every time a buffer level
(B,(i) or B2(k)) reaches a corresponding upper or lower bound, the DDS adjusts the corresponding value N to reflect a new estimated output clock rate. The amount of adjustment ΔN can be computed by
K ■ TH • Δ t. AN = ° (Eq. 6)
Δ t
where K is a constant, TH is a threshold, Δt0 is the elapsed time during the transient state and Δt is the elapsed time between two clock adjustments due to the buffer level reaching the upper or lower bounds.
In some applications such as ATM, a higher layer protocol data unit (PDU) may be segmented into more than one cells or packets. A reassembly function is then necessary in the receiver side to reassemble the cells or packets back into the corresponding PDU. To deal with such a case, an embodiment of a circuit 200 is shown in FIG. 4 which includes a reassembly unit 108 coupled between first and second buffers 102, 104, respectively. In this circuit, clock recovery unit 106A generates three clock signals: CLKl 105, CLK2 1 11 and CLK3 115. Clock signals CLKl and CLK2 provide the same clock functions as described above with respect to the first and second buffers shown in FIG. 1. In addition, clock signal CLK3 is the byte or bit clock that extracts bytes or bits from reassembly unit 108 into second buffer 104. The ratio of cells or packets to a PDU is usually fixed. Let this ratio be defined as p. The clock recovery unit 106A generates clock signal CLK3 according to r3(i) = pτ,(i) (Eq. 7) where r3(i) is the clock rate of clock signal CLK3. The generation and updating of clock signals CLKl and CLK2 in circuit 200 accordingly follows from the foregoing equations (Eq. 1), (Eq. 2), (Eq. 3), (Eq. 4) and (Eq. 5).
In another embodiment, the buffers 102, 104 can be replaced by one physical buffer. Thus, buffers 102, 104 become "virtual buffers". In such a case, an inter- buffer transfer, i.e., any byte output from the first buffer 102 into second buffer 104, does not leave the actual physical buffer. Rather, only the respective buffer levels of buffers 102, 104 are changed.
While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

JO-CLAIMSWhat is claimed is:
1. A circuit for controlling clock timing at a receiver that receives asynchronous data, the circuit comprising: a first buffer having an input for receiving asynchronous data and an output; a second buffer having an input coupled to the output of the first buffer and an output; and a clock recovery unit for monitoring a first buffer level of the first buffer and a second buffer level of the second buffer and for controlling clock timing for the first and second buffers responsive to the first and second buffer levels, respectively.
2. The circuit of Claim 1 wherein the clock recovery unit includes means for generating a first output clock signal coupled to the first buffer and means for generating a second output clock signal coupled to the second buffer, and wherein the clock recovery unit controls clock timing by adjusting the rate of the first output clock signal if the first buffer level is outside a first range defined by a first upper bound and a first lower bound.
3. The circuit of Claim 2 wherein the clock recovery unit adjusts the rate of the first output clock signal according to the relation:
B, X ) ~ B1 ( i ') r^ i ) = r1 { i ') + K
if I B,(i) - B,(i') i > TH,, where i is a time index, r,(i) is the rate of the first output clock signal at time i, B,(i) is the first buffer level at time i, i' is the time the first output clock signal was last adjusted, K, is a constant and TH, is a first threshold.
4. The circuit of Claim 2 wherein the clock recovery unit further controls clock timing by adjusting the rate of the second output clock signal if the second buffer level is outside a second range defined by a second upper bound and a second lower bound.
5. The circuit of Claim 4 wherein the clock recovery unit adjusts the rate of the second output clock signal according to the relation:
B2 (k) - B2 ( k ') r2 (k) = r2 (k') + K- k - k1
if I B2(k) - B2(k') | > TH2, where k is a time index, r2(k) is the rate of the second output clock signal at time k, B2(k) is the second buffer level at time k, k' is the time the second output clock signal was last adjusted, K2 is a constant and TH2 is a second threshold.
6. The circuit of Claim 5 wherein the circuit operates in a transient state and a steady state and wherein the clock recovery unit declares the steady state if the first or second range is exceeded in opposite directions consecutively.
7. The circuit of Claim 6 wherein upon declaring the steady state, the clock recovery unit increases the value of TH, and TH2.
8. The circuit of Claim 6 wherein upon declaring the steady state, the clock recovery unit decreases the value of K, and K2.
9. The circuit of Claim 2 wherein the received asynchronous data comprises asynchronous packets or cells and wherein the circuit further comprises a reassembly unit coupled between the first and second buffers for reassembling the received packets or cells into protocol data units.
10. The circuit of Claim 9 wherein the clock recovery unit includes means for generating a third output clock signal coupled to the reassembly unit and wherein the clock recovery unit further controls clock timing by adjusting the rate of the third output clock signal in relation to the first output clock signal.
11. The circuit of Claim 2 wherein the clock recovery unit adjusts the first upper and first lower bounds in the same direction as the adjustment of the rate of the first output clock signal.
12. The circuit of Claim 1 wherein the clock recovery unit includes means for generating a first output clock signal coupled to the first buffer and means for generating a second output clock signal coupled to the second buffer, and wherein the clock recovery unit controls clock timing by adjusting the rate of the first output clock signal according to the relation:
rχ ( i ) = r^ O ) + Kχ ■ [B D - 5, ( 0 ) ] where i is a time index, r,(i) is the rate of the first output clock signal at time i, B,(i) is the first buffer level at time i and K, is a constant.
13. The circuit of Claim 12 wherein the clock recovery unit adjusts the rate of the second output clock signal according to the relation:
BA k) - BΛ k') rΛ k) = rΛk1) + k - k if I B2(k) - B2(k') j > TH2, where k is a time index, r2(k) is the rate of the second output clock signal at time k, B2(k) is the second buffer level at time k, k' is the time the second output clock signal was last adjusted, K2 is a constant and TH2 is a second threshold.
14. The circuit of Claim 1 wherein the first buffer comprises a first virtual buffer and the second buffer comprises a second virtual buffer, the first and second virtual buffers being implemented in a single physical buffer.
15. A method of controlling clock timing at a receiver that receives asynchronous data, the method comprising: receiving asynchronous data in a pair of cascaded buffers, the buffer pair including a first buffer and a second buffer; monitoring a level of the first buffer; monitoring a level of the second buffer; and controlling clock timing for the first and second buffers responsive to the first and second buffer levels, respectively.
16. The method of Claim 15 further comprising generating a first output clock signal coupled to the first buffer and generating a second output clock signal coupled to the second buffer, and wherein controlling clock timing includes adjusting the rate of the first output clock signal if the first buffer level is outside a first range defined by a first upper bound and a first lower bound.
17. The method of Claim 16 wherein adjusting includes adjusting the rate of the first output clock signal according to the relation:
Bχ { i ) - B1 ( i ') rχ ( i) = :Λ i ') + K i - i '
if I B,(i) - B,(i') I > TH,, where i is a time index, r,(i) is the rate of the first output clock signal at time i, B,(i) is the first buffer level at time i, i' is the time the first output clock signal was last adjusted, K, is a constant and TH, is a first threshold.
18. The method of Claim 17 wherein controlling clock timing further includes adjusting the rate of the second output clock signal if the second buffer level is outside a second range defined by a second upper bound and a second lower bound.
19. The method of Claim 18 wherein adjusting includes adjusting the rate of the second output clock signal according to the relation:
BΛ k) - B k1)
[ k) = rΛ k ') + k - k'
if I B2(k) - B2(k') | > TH2, where k is a time index, r2(k) is the rate of the second output clock signal at time k, B2(k) is the second buffer level at time k, k' is the time the second output clock signal was last adjusted, K2 is a constant and TH2 is a second threshold.
20. The method of Claim 16 wherein adjusting includes adjusting the first upper and first lower bounds in the same direction as the adjustment of the rate of the first output clock signal.
21. The method of Claim 15 further comprising generating a first output clock signal coupled to the first buffer and generating a second output clock signal coupled to the second buffer, and wherein controlling clock timing includes adjusting the rate of the first output clock signal according to the relation:
r i ) = rχ ( 0 ) + Kλ ■ [B1 ( i ) - 23, ( 0 ) ] where i is a time index, r,(i) is the rate of the first output clock signal at time i, B,(i) is the first buffer level at time i and K, is a constant.
22. The method of Claim 21 wherein adjusting includes adjusting the rate of the second output clock signal according to the relation:
BΛ k) - BΛk1) rΛk) = rΛ 1) + K, k'
if I B2(k) - B2(k') I > TH2, where k is a time index, r2(k) is the rate of the second output clock signal at time k, B2(k) is the second buffer level at time k, k' is the time the second output clock signal was last adjusted, K2 is a constant and TH2 is a second threshold.
PCT/US1999/024277 1998-10-21 1999-10-19 Method and apparatus for de-jittering asynchronous data transfer delay WO2000024144A1 (en)

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