WO2000025559A1 - Method for manufacturing a circuit board - Google Patents

Method for manufacturing a circuit board Download PDF

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Publication number
WO2000025559A1
WO2000025559A1 PCT/SE1999/001936 SE9901936W WO0025559A1 WO 2000025559 A1 WO2000025559 A1 WO 2000025559A1 SE 9901936 W SE9901936 W SE 9901936W WO 0025559 A1 WO0025559 A1 WO 0025559A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
cavity
agent
via holes
layer
Prior art date
Application number
PCT/SE1999/001936
Other languages
French (fr)
Inventor
Mats SÖDERHOLM
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson filed Critical Telefonaktiebolaget Lm Ericsson
Priority to AU14311/00A priority Critical patent/AU1431100A/en
Publication of WO2000025559A1 publication Critical patent/WO2000025559A1/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0094Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/0959Plated through-holes or plated blind vias filled with insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits

Definitions

  • a circuit board and specially a multilayer circuit board includes several vias or plated via holes, for example for insertion of component terminals and for connecting them to conductors arranged inside or on the circuit board, which interconnects the components.

Abstract

The present invention refers to a method when manufacturing a circuit board (10), specially a multilayer circuit board (10). The method is provided to protect a surface coating of a cavity (11) by preventing harmful production material floating into the cavity through one or more via holes (13, 13') arranged in said cavity (11), said cavity being arranged for receiving an electric component. The via holes during the production of at least each layer of said circuit board are filled with an agent, resistant to said harmful material and also resistant to subsequent soldering.

Description

TITLE
METHOD FOR MANUFACTURING A CIRCUIT BOARD
TECHNICAL FIELD
The present invention relates to a method for manufacturing a circuit board, in particular a multilayer circuit board including at least one cavity for receiving a component and one or more vias holes. The method aims to protect a surface coating of the cavity by preventing harmful production material floating into the cavity through one or more via holes arranged in said cavity.
BACKGROUND OF THE INVENTION
A circuit board and specially a multilayer circuit board includes several vias or plated via holes, for example for insertion of component terminals and for connecting them to conductors arranged inside or on the circuit board, which interconnects the components.
A new type of circuit board provided with cavities for receiving components and some via holes placed inside the cavities is known through the parallel pending Swedish Patent Application No. 9803671-8. Arranging the components in the cavities allows more space for necessary electronic components and better electrical performance can be obtained. These needs are however not reconcilable with the known manufacturing processes and the choice of material that can be obtained.
The cavities on the circuit board are coated at least partly through surface treatment with a conductive material, e.g. of copper, silver, gold or the like. To prevent the damages from the surface treatment, a cavity is usually milled in the layer structure, but a "cover" and a "bottom" are left intact.
A problem that arises is that in certain cases the bottom of the cavity must be perforated with via holes, which results in that sealing is not possible and harmful material, specially chemicals can under the manufacturing, assembling and soldering float via the via holes into the cavities. Specially the chemicals damage the coatings that can occur in the cavity. However, when no cavities are provided, one can use a "prepreg" for protection, but the problem is that the prepreg does not enter into the cavities and fills the via holes. The prepreg is a partly tempered laminate that has good filler characteristics and can fill the via holes (vias). When the cavities are provided a prepreg, which does not have the same filler characteristics is used, because presence of prepreg inside the cavities is not allowed. Since the later prepreg does not fill the holes, it cannot be used to fill the holes in the cavities.
Through US 5,436,279, a coating is known, which can be cross-linked through radiation. The agent is intended to be used as filler during the soldering of the circuit board and it is applied in the via holes on the circuit board, which should not be filled with solder. The agent is manufactured by LACKSERE PETERS Gmbh & CO. KG, and is marketed under the label SD2361.
Another material that is used to prevent solder to float into the vias on the circuit board during the soldering is soled by ELECTRA POLYMERS & CHEMICALS LTD. and marketed under the trademark NIPRA®.
Additionally, US 5,591,353 discloses a method of fabricating a printed wiring board and a printed wiring board module by providing a first board having a pair of major opposing surfaces, a via having walls extending between the surfaces and a layer of copper disposed on at least one surface and extending along the walls of the via. The copper disposed in the via is protected against a subsequent etching of the copper on the surface by filling the remaining portion of the via with an epoxy and then reducing the thickness of the layer of copper on the surface. The layer of copper and the epoxy are then planarized. A core layer and a second board are then provided and the first and second boards are secured to opposing sides of the core layer. A second via having walls and extending through the first and second boards and the core layer is then formed and a layer of copper is disposed on the walls of the second via and the surface. The electrically conductive material on the surface is then patterned and etched to form an electrically conductive pattern. European Patent Application No. 800 336 (Al) proposes a resin filler suitable for filling in the concave portion created on the surface of a wiring substrate or a through-hole formed in the substrate and a construction of a build-up multilayer printed circuit board obtained by smoothening the surface of the substrate filled with the resin filler. Furthermore, a solvent-free resin filler is proposed filled in the concave portion created on the surface of the wiring substrate or in the through-holes formed in the substrate, which comprises a bisphenol type epoxy resin as a resin component and an imidazole curing agent as a curing agent, and if necessary, inorganic particles as an additive component, and a build-up multilayer printed circuit board using this resin filler.
None of above mentioned documents strive to solve the problem with the damages which can arise when material, specially chemicals used for the production of the circuit board can penetrate into the cavities through via-holes and damage the conductive layer inside the cavities.
SUMMARY OF THE INVENTION
The main object of the present invention is to provide a simple, less time consuming and cost-effective procedure during manufacturing circuit boards that solves above-mentioned problem, i.e. preventing harmful material to float into the cavity through the via holes.
Yet another object of the invention is to provide for a substantially hermetical sealing of the cavities, by leaving the agent used to fill the via holes for stopping harmful material to float into the cavities during the manufacturing process.
Surprisingly, a possibility has been obtained to prevent chemicals from coming inside the cavities and via holes provided on a circuit board through application of above described fillers during the manufacturing.
The objective has been achieved by filling said via holes during the production of at least each layer of said circuit board with an agent, resistant to said harmful material and also resistant to subsequent soldering materials. Preferably the agent is applied in the via holes through screen printing and it is hardened thermally or through radiation. Said agent can also be applied after making the conductor patterns in the cavity.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following, the invention will be described with reference to embodiments shown on the attached drawings, in which:
Fig. 1 is a schematic view from above of a circuit board produced according to the present invention, and Fig. 2 is a schematic cross-section along line II -II through the board shown in fig. 1.
DESCRIPTION OF ONE EMBODIMENT
When manufacturing the circuit board or printed board including via holes and cavities having surface treatments, surprisingly a possibility has been revealed to prevent harmful materials from floating into the cavities or via holes and damaging the surface treatments by using material (VIPRA, SD2361) which actually are intended to be used as fillers during the process of soldering to prevent solder to float into and through the via holes.
Figs. 1 and 2 show a multilayer circuit board 10, which includes cavities 11 as well as a space 12 for receiving circuits and components.
On the board and in the cavities, holes 13 are provided primarily for receiving components or component terminals. Certain holes 13 are through holes, but also holes 13' which terminate at a certain layer in the circuit board can occur. Holes can also be used as vias to obtain connection between the faces of the board, e.g. through surface mounting of circuits and conductors of signals through the different layer of the board.
The cavities 11 are provided to accommodate special circuits, e.g. naked circuits and other components. Conductor patterns 14 for these are shown in the figure. Circles represent holes 13/13'.
According to fig. 2, a first layer 15 consists of a conductive material, such as copper, constituting a ground plane or the like. The ground plane is plated on a laminate 16 of an insulating material. A layer of prepreg 17 is applied between the laminate layer 15 and a third conducting layer 18 provided on another laminate layer 19. Between the laminate layer 19 and a conductive layer 21 is another layer 20 applied with prepreg. The conducting layer 21 is provided on a laminate layer 22, which also on the underside is provided with a conductive layer 23. A prepreg layer 24 is provided between the layer 23 and a second conducting layer 25, which is provided on a laminate 26. The conductive layers are, among others, intended to be used as connections, ground plane and so on. Between the different layers, in particular between the prepreg-laminate, or prepreg-conductor a coating or adhesive additive can be applied.
It should be noted that the embodiment according to the drawings is given only as a non- limiting example and configurations including other layouts and layer structures can occur.
The cavities 11 are recesses that are obtained during the fabrication, e.g. through using layers with recessed sections corresponding to the form of the cavity. The conductive pattern 14 in the cavities are applied during the fabrication, e.g. through plating. Through use of laminates provided with base copper, patterns are generated through etching and plating by means of an appropriate surface treatment. Obviously, other methods may occur. To prevent damages on this coating, normally a "lid" 27 in the end layer and a "bottom" for the cavity inside the layer structure are left intact. The lid is removed through milling when the board is completed.
To prevent chemicals to enter into the via holes 13 and through them into the cavities 11 and damage the surface coating during the manufacturing process, under the manufacturing process, preferably during manufacturing of each laminate layer/conductive layer, above described substance resistant to solder is applied. The substance is applied very quickly, e.g. through screen printing or other known application methods, in the via holes and the manufacturing process does not suffer from any appreciable delay. Moreover, also 35 - 43 T polyester or a similar steel screen have been proven to be suitable. According to one advantageous embodiment the substance is applied before or after providing the conductive pattern on the layer that forms the bottom layer of the cavities 11, i.e. after production of layer 20. Preferably, the substance is applied after that the holes have been plated and the conductive layers have been etched. However, this depends on which process that is used, e.g. pattern plating or panel plating process.
For screen printing a silk screen film is produced from a photo mask with the hole patterns (preferably, the ones that are through holes) and the agent is applied afterwards in the holes and hardened by means of ultra violet light, heat or the like. The process can be repeated several times for different cavities.
Following non-limiting example describes some important steps when manufacturing a circuit board, in accordance with the invention:
- a laminate layer 26 is produced according to prior art; - then the laminate layer 26 is provided with via holes 13 ;
- the desired via holes are plated;
- subsequently the holes are filled with a filler;
- then a new laminate layer 22 is produced;
- if required the laminate layer is provided with a conductive layer or pattern; - then the laminate layers 22 and 26 are attached together by means of prepreg 24; via holes 13 (13') are then drilled and plated; the holes are filled with the filler through screen printing from a front and/or rear face and hardened subsequently;
- then a laminate layer 19 provided with the layer for cavity(ies) 11 ( milled off cavity) is produced;
- then all laminate layers are joint together ( laminated together);
- conductor patterns are created;
- afterwards the via holes are drilled and plated;
- finally the laminate layer 16 is produced; and - a possible part of the laminate functioning as the "lid" is milled off.
Clearly, one or several of above described stages can be performed in parallel, at same time that the order of the steps can be changed.
Preferably, the filler is left in the holes since the plating that allows conduction in the via holes is interesting for the function of the board. Besides when covering the cavities, an essentially hermetical sealing of cavities is achieved as a protection against the outer environment. However, the filler can be removed in an appropriate way.
A material (SD2361) which appears to be very suitable according to the present invention includes an olefinic unsaturated ester of an epoxy novolac resin, a binder produced by reaction of an epoxy compound having more than one epoxied group per molecule with at least one carboxylic acid in a molar ratio of epoxy groups per carboxyl group of 1: 0.5 to 0.9 and subsequent reaction of the resulting reaction product with at least one unsaturated isocyanate ester formed by reaction of a compound with at least two isocyanate groups with a member of the group consisting of hydroxyl. The hydroxyl containing acrylic acid, methacrylic acid and cyanacrylic acid esters, at least one latent hardener, at least one photoinitiator, fillers selected from the group consisting of colloidal or hydrophobized silicon dioxide, microtalc, micromica, kaolin, aluminum oxides, magnesium silicate, aluminum hydroxide, calcium silicate, aluminum silicate, magnesium carbonate, calcium carbonate, zirconium silicate, ground porcelain, antimony trioxide, titanium dioxide, barium titanate and barium sulfate, and mixtures of said fillers, wherein the filler content is 80-120% by weight of the binder mixture of components and the mean particle size of the fillers is in the range of 0.01 to 10 μm and the coating agent further includes other binding agents additives, adjuvants and solvents. The agent can be cured through thermal or ultra violet radiation.
While we have illustrated and described a preferred embodiment of the invention, it is apparent that several variations and modifications within the scope of the attached claims can occur.

Claims

1. When manufacturing a circuit board (10), specially a multilayer circuit board (10), a method of protecting a surface coating of a cavity (11) by preventing harmful production material floating into the cavity through one or more via holes (13, 13') arranged in said cavity (11), said cavity being arranged for receiving an electric component, characterised by filling said via holes during the production of at least each layer of said circuit board with an agent, resistant to said harmful material and also resistant to subsequent soldering materials.
2. The method according to claim 1, characterised in, that said one or more via holes are plated.
3. The method according to claim 1 or 2, characterised in, that said agent is applied in the via hole through screen printing.
4. The method according to any of the claims 1 - 3, characterised in, that said agent is tempered thermally or through radiation.
5. The method according to claim 2, characterised in, that said agent is applied after fabrication of that plated via holes.
6. The method according to any of preceding claims, characterised in, that said agent is applied after making of a conductor pattern (14) in the cavity (11).
7. The method according to claim 1, characterised in, that the agent includes an olefinic unsaturated ester of an epoxy novolac resin, at least one latent hardener, at least one photoinitiator, fillers selected from the group consisting of colloidal or hydrophobized silicon dioxide, microtalc, micromica, kaolin, aluminum oxides, magnesium silicate, aluminum hydroxide, calcium silicate, aluminum silicate, magnesium carbonate, calcium carbonate, zirconium silicate, ground porcelain, antimony trioxide, titanium dioxide, barium titanate and barium sulfate, and mixtures of said fillers, wherein the filler content is 80- 120% by weight of the binder mixture of components and the mean particle size of the fillers is in the range of 0.01 to 10 μm and the coating agent further includes other binding agents additives, adjuvants and solvents.
8. The method according to claim 7, characterised in, that agent further includes a binder produced by reaction of an epoxy compound having more than one epoxide group per molecule with at least one carboxylic acid in a molar ratio of epoxy groups per carboxyl group of 1 : 0.5 to 0.9 and subsequent reaction of the resulting reaction product with at least one unsaturated isocyanate ester formed by reaction of a compound with at least two isocyanate groups with a member of the group consisting of hydroxyl. The hydroxyl containing acrylic acid, methacrylic acid and cyanacrylic acid esters.
9. The method according to any of preceding claims, characterised in, that said agent is left in the via holes for providing a substantially hermetical cavity.
10. A circuit board, specially a multi-layer circuit board including one or more cavities (11) essentially intended for receiving components and one or more via holes (13) provided in and/or outside the cavity, which circuit board is produced according to any of claims 1-9.
PCT/SE1999/001936 1998-10-26 1999-10-26 Method for manufacturing a circuit board WO2000025559A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU14311/00A AU1431100A (en) 1998-10-26 1999-10-26 Method for manufacturing a circuit board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9803670A SE9803670L (en) 1998-10-26 1998-10-26 Procedure for making circuit boards
SE9803670-0 1998-10-26

Publications (1)

Publication Number Publication Date
WO2000025559A1 true WO2000025559A1 (en) 2000-05-04

Family

ID=20413091

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1999/001936 WO2000025559A1 (en) 1998-10-26 1999-10-26 Method for manufacturing a circuit board

Country Status (3)

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AU (1) AU1431100A (en)
SE (1) SE9803670L (en)
WO (1) WO2000025559A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449168B1 (en) 1998-10-26 2002-09-10 Telefonaktiebolaget Lm Ericcson (Publ) Circuit board and a method for manufacturing the same
CN106793515A (en) * 2016-12-28 2017-05-31 上海展华电子有限公司 A kind of buried via hole lamination process method of printed circuit board (PCB)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436279A (en) * 1991-05-24 1995-07-25 Rutgerswerke Aktingesellschaft Coating materials containing a reaction product of an epoxy novolak resin and an olefinically unsaturated carboxylic acid crosslinkable by radiation
US5591353A (en) * 1994-08-18 1997-01-07 Texas Instruments Incorporated Reduction of surface copper thickness on surface mount printed wire boards with copper plated through holes by the chemical planarization method
EP0800336A1 (en) * 1995-10-23 1997-10-08 Ibiden Co., Ltd. Resin filler and multilayer printed wiring board
US5712767A (en) * 1994-11-16 1998-01-27 Nec Corporation Circuit elements mounting

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436279A (en) * 1991-05-24 1995-07-25 Rutgerswerke Aktingesellschaft Coating materials containing a reaction product of an epoxy novolak resin and an olefinically unsaturated carboxylic acid crosslinkable by radiation
US5591353A (en) * 1994-08-18 1997-01-07 Texas Instruments Incorporated Reduction of surface copper thickness on surface mount printed wire boards with copper plated through holes by the chemical planarization method
US5712767A (en) * 1994-11-16 1998-01-27 Nec Corporation Circuit elements mounting
EP0800336A1 (en) * 1995-10-23 1997-10-08 Ibiden Co., Ltd. Resin filler and multilayer printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449168B1 (en) 1998-10-26 2002-09-10 Telefonaktiebolaget Lm Ericcson (Publ) Circuit board and a method for manufacturing the same
CN106793515A (en) * 2016-12-28 2017-05-31 上海展华电子有限公司 A kind of buried via hole lamination process method of printed circuit board (PCB)
CN106793515B (en) * 2016-12-28 2019-05-14 上海展华电子有限公司 A kind of buried via hole lamination process method of printed circuit board

Also Published As

Publication number Publication date
AU1431100A (en) 2000-05-15
SE9803670D0 (en) 1998-10-26
SE9803670L (en) 2000-04-27

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