WO2000036641A1 - Wiring, thin-film transistor substrate with the wiring, method of manufacture thereof, and liquid crystal display device - Google Patents

Wiring, thin-film transistor substrate with the wiring, method of manufacture thereof, and liquid crystal display device Download PDF

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Publication number
WO2000036641A1
WO2000036641A1 PCT/JP1999/006877 JP9906877W WO0036641A1 WO 2000036641 A1 WO2000036641 A1 WO 2000036641A1 JP 9906877 W JP9906877 W JP 9906877W WO 0036641 A1 WO0036641 A1 WO 0036641A1
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WO
WIPO (PCT)
Prior art keywords
film
wiring
titanium
copper
substrate
Prior art date
Application number
PCT/JP1999/006877
Other languages
French (fr)
Japanese (ja)
Inventor
Makoto Sasaki
Gee Sung Chae
Original Assignee
Frontec Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Frontec Incorporated filed Critical Frontec Incorporated
Priority to US09/555,625 priority Critical patent/US6956236B1/en
Priority to JP2000588799A priority patent/JP4247772B2/en
Priority to KR1020007008531A priority patent/KR100399556B1/en
Priority to EP99959702.4A priority patent/EP1063693B1/en
Publication of WO2000036641A1 publication Critical patent/WO2000036641A1/en
Priority to US11/100,432 priority patent/US7804174B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a wiring, a thin film transistor substrate using the same, a method of manufacturing the same, and a liquid crystal display.
  • the present invention relates to a wiring using low-resistance copper as an electrode or wiring material, a thin film transistor (TFT) substrate using the same, a method of manufacturing the same, and a liquid crystal display device.
  • TFT thin film transistor
  • a thin film transistor (TFT) substrate is known as a substrate provided in a liquid crystal display device.
  • FIG. 33 and FIG. 34 show an example of the structure of a general thin film transistor substrate provided with portions such as a gate wiring G and a source wiring S on a substrate 86.
  • a gate wiring G and a source wiring S are wired in a matrix on a transparent substrate 86 such as glass.
  • a region surrounded by the gate wiring G and the source wiring S is defined as a pixel portion 81, and a thin film transistor 83 is provided in each pixel portion 81.
  • the thin film transistor 83 has a general structure of an etch stop type.
  • the thin film transistor 83 has a gate wiring G made of a conductive material such as A 1 or an A 1 alloy, and a gate electrode 88 pulled out from the gate wiring G.
  • An insulating film 89 is provided, a semiconductor active film 90 made of amorphous silicon (a-Si) is provided on the gate insulating film 89 so as to face the gate electrode 88, and further on the semiconductor active film 90.
  • the drain electrode 91 and the source electrode 92 made of a conductive material such as A1 or A1 alloy are provided to face each other.
  • ohmic contact films 90a and 90a such as amorphous silicon doped with a high concentration of a dopant such as phosphorus.
  • An etching stopper 93 is formed in a state sandwiched by the formed drain electrode 91, source electrode 92, and semiconductor active film 90.
  • a transparent layer of indium tin oxide (hereinafter abbreviated as ITO) extends from above the drain electrode 91 to the side of the drain electrode 91.
  • ITO indium tin oxide
  • a passivation film 96 is provided so as to cover the gate insulating film 89, the transparent pixel electrode 95, the drain electrode 91, the source electrode 92, and the like.
  • An alignment film (not shown) is formed on the passivation film 96, and a liquid crystal is provided above the alignment film to constitute an active matrix liquid crystal display device. When an electric field is applied, the alignment of liquid crystal molecules can be controlled.
  • the thin film transistor substrate shown in FIGS. 33 and 34 As a method of manufacturing the thin film transistor substrate shown in FIGS. 33 and 34, an aluminum or aluminum alloy sunset is used, and a thin film such as a normal sputtering method in which DC power is applied to the sunset is used. After forming the A1 or A1 alloy layer on the glass substrate 86 by the forming means, the gate electrode 88 is removed by removing the A1 or A1 alloy layer at a place other than the gate formation position by a photolithography method.
  • S I_ ⁇ 2 and S i N gate insulating film 8 9 consisting of x, semiconductors active film 9 0, the etching stopper 9 3 is formed by a thin film formation means such as a CVD method, and then above the top of these An ohmic contact film 90a, a drain electrode 91 and a source electrode 92 are formed by a sputtering method or a photolithography method, and the formed drain electrode 91 and source electrode 92 are masked. After splitting the O over Mick contactee Bokumaku 9 0 a to divided portions of the ohmic contact layer 9 0 a, by forming a passive Beshiyon film 9 6 by a CVD method, a thin film transistor substrate is obtained.
  • an electrode material such as a gate electrode 88 and a wiring material such as a gate wiring G (hereinafter abbreviated as a wiring material).
  • a wiring material such as a gate wiring G
  • the copper film may be damaged by etching when the oxidizing acid-based etching agent used to etch other layers in the subsequent process infiltrates the copper film.
  • the damage may be peeled off from the substrate 86 as a base film or a disconnection failure may occur, so that there is a problem that an etching agent to be used is limited.
  • the resist stripping solution when used as a wiring material, when a resist stripping solution used in a photolithography process permeates the copper film, the resist stripping solution may corrode the copper film.
  • the etching mechanism of the copper film is such that the surface of the copper film is oxidized to perform etching. Before the etching, moisture or oxygen in the air causes the surface of the copper film to have an oxide layer such as CuO or Cu u. If the etching is not completed, there is a problem that even an etching agent having no oxidizing power is etched and damaged, and furthermore, a disconnection failure occurs. Therefore, as the C u based wiring material capable of preventing the occurrence of the oxide layer, such as C U_ ⁇ and C u 2 ⁇ on the surface, but C u alloys are considered, C u alloy wire ratio than the C u The resistance increases, and the effect of using a low resistance material cannot be expected much.
  • the gate electrode 88 is made of a copper film, Cu diffuses into the gate insulating film 89, which causes a problem of poor withstand voltage.
  • the substrate 86 is a glass substrate, the gate electrode 8 Si in the substrate 86 enters the gate electrode 88 into the gate electrode 8, and the resistance of the gate electrode 88 increases.
  • the drain electrode 91 and the source electrode 92 are made of a copper film, mutual diffusion of elements occurs between the electrodes 91 and 92 and the semiconductor active film 90, and the characteristics of the semiconductor active film deteriorate. There was a problem of doing it. Disclosure of the invention
  • the present invention has been made in view of the above circumstances, and when low-resistance copper is used as a wiring material, it is possible to improve the oxidation resistance to moisture and oxygen, and furthermore, the corrosion resistance to an etching agent, a resist stripping solution, and the like.
  • Wiring, a thin film transistor substrate using the same, a method of manufacturing the same, and a thin-film transistor using the same It is an object to provide a liquid crystal display device provided with a substrate.
  • the wiring of the present invention is characterized by having a coating made of titanium or titanium oxide around a copper layer. Specific examples of the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2, and more specifically, a titanium coating, And a titanium oxide film.
  • the wiring of the present invention may be characterized by having a coating made of molybdenum or molybdenum oxide around a copper layer.
  • the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of molybdenum atoms is 1: 0 to 1: 3. More specifically, a molybdenum coating, molybdenum oxide Coatings and the like.
  • the wiring of the present invention may be characterized by having a coating made of chromium or chromium oxide around a copper layer.
  • the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 0 to 1: 2, and more specifically, a chromium film, chromium oxide Coatings and the like.
  • the wiring according to the present invention may have a structure in which a copper layer is provided around the copper layer, and the coating is made of oxide or oxide.
  • the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of tantalum atoms is 1: 0 to 1: 2.5, and more specifically, a tantalum coating. And a tantalum oxide film.
  • the thickness of the film formed around the copper layer is preferably about 5 to 30 nm, more preferably about 5 to 20 nm. If the thickness of the film is less than 5 nm, the film is too thin to improve the oxidation resistance to moisture and oxygen and the corrosion resistance to an etching agent or a resist stripping solution, etc. Interdiffusion of elements may occur. Further, even if the thickness exceeds 3 Onm, the intended effect is saturated, but the film formation time increases, and the wiring specific resistance increases.
  • the film in the case where a film made of titanium or titanium oxide is provided around the copper layer, the film is made of a titanium film and a film made of titanium oxide.
  • Specific examples include a titanium film and a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2. And others.
  • the film in the case where a film made of titanium or titanium oxide is provided around the copper layer, the film includes a titanium film formed around the copper layer and a surface of the titanium film. A titanium film formed around the copper layer and a titanium film formed on the surface of the titanium film. And a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2.
  • the film in the wiring having a film made of titanium or titanium oxide around the copper layer, is formed of a copper film formed on a part of the periphery of the copper layer. And a film made of titanium oxide formed on the rest of the periphery of the copper layer.
  • a titanium film formed on a part of the periphery of the copper layer And a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed in the remainder around the copper layer is 1: 1 to 1: 2.
  • the film in which the copper film has a film made of chromium or chromium oxide around the copper layer, the film has a chromium film and a film made of chromium oxide.
  • the film includes a chromium film and a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 1 to 1: 2.
  • the film in the case where a film made of chromium or chromium oxide is provided around the copper layer, the film includes a chromium film formed around the copper layer and a surface of the chromium film. A chromium film formed on the surface of the chromium film and a chromium film formed around the copper layer. And a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 1 to 1: 2.
  • a thin film transistor substrate according to the present invention includes the wiring of the present invention having any one of the above structures.
  • the thin film transistor substrate of the present invention is characterized in that the wiring of the present invention having any one of the above structures is provided on a base via a TiN film.
  • the thin film transistor substrate of the present invention may be characterized in that a wiring having a coating made of titanium or titanium oxide is provided around a copper layer on a base via a TiN film.
  • the coating made of titanium or titanium oxide include a coating having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2.
  • the thin film transistor substrate of the present invention may have a structure in which a wiring film having a film made of titanium or titanium oxide is provided on a surface of a copper layer via a TiN film on a substrate.
  • the wiring film here may be a film having a titanium film formed on the surface of the copper layer and a film made of titanium oxide formed on the surface of the titanium film.
  • Specific examples of the titanium oxide film include a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2.
  • the thickness of the TiN is preferably about 10 to 50 nm. If the thickness of the TiN is less than 10 nm, the film acting as the barrier layer is not formed between the copper layer of the wiring and the substrate, or the thickness of the film is not sufficient. when, the base and, S I_ ⁇ , S i oN, the effect of prevention of the elements that have diffused from the adjacent layer from entering the wiring, such as S I_ ⁇ x is insufficient. Further, if the thickness exceeds 50 nm, the intended effect is saturated, but the deposition time increases.
  • the thin film transistor substrate of the present invention having such wirings, even if an oxidizing acid-based etching agent used in etching another layer in a later step penetrates into the copper wirings, the copper layer is not removed. Since the above-mentioned film acting as a protective layer is formed on the periphery or on the surface, the wiring is hardly damaged by the etching agent, the wiring can be prevented from peeling off from the ground, and the occurrence of disconnection failure can be prevented. The degree of freedom of the etching agent used is large.
  • the wiring used in the present invention has the above-mentioned film acting as a protective layer formed around or on the surface of the copper layer. Therefore, it is possible to prevent corrosion of the wiring due to the resist stripping solution.
  • the wiring according to the present invention has the above-mentioned film formed around or on the copper layer, an oxide layer is not formed on the surface of the wiring due to the presence of moisture before etching, and has no oxidizing power. It is hardly damaged by the etching agent, and the occurrence of disconnection failure can be prevented.
  • the above-mentioned film acting as a barrier layer is formed around the copper layer, even if the element diffuses from the adjacent film, the diffusion of atoms into the wiring is inhibited by the above-mentioned film, and the diffusion of the element from the adjacent film is prevented.
  • the above-mentioned coating can prevent the increase in the wiring resistance due to the diffusion of Cu atoms in the copper layer to the adjacent film, so that the withstand voltage due to the diffusion of Cu atoms from the copper layer can be prevented. Failures can be prevented, and deterioration of the characteristics of the semiconductor active film can be prevented.
  • the element is diffused from an adjacent film above or on the side of the wiring (above or above the above-mentioned film).
  • the diffusion of atoms into the wiring is hindered by the above-mentioned coating, and an increase in wiring resistance due to the diffusion of elements from the adjacent film can be prevented.
  • Copper because it is prevented from diffusing into the In addition to preventing dielectric breakdown failure caused by diffusion of Cu atoms from the layer, deterioration of the characteristics of the semiconductor active film can be prevented.
  • the periphery or the surface of the copper layer is covered with the above-described film, when forming an insulating film or a passivation film made of silicon oxide on the wiring by a CVD method or the like, Cu and the Cu constituting the copper layer are used. It is possible to prevent the reaction between S i H 4 gas forming material such as an insulating film, without needle projections are generated on the surface of the copper layer due to the reaction, the insulation resistance defect occurs due acicular projections Can be prevented.
  • the barrier as described above is provided between the lower surface of the copper layer constituting the wiring and the base. Even if a coating acting as a single layer is not provided, or the thickness of the coating between the lower surface of the copper layer and the substrate is small, a TiN film is formed between the wiring and the substrate. Is provided, even if an element diffuses into the wiring from the substrate or the adjacent film, the diffusion of atoms into the wiring is inhibited by the TiN film, resulting from the diffusion of the element from the substrate or the adjacent film. The effect of preventing an increase in wiring resistance is excellent. Further, the adhesion of the wiring is improved by the TiN film.
  • the oxidation resistance to moisture and oxygen can be improved without impairing the characteristics of using low-resistance copper as a wiring material, and the resistance to an etching agent and a resist stripping solution can be improved. It can improve the adhesion to the underlying film, prevent disconnection defects and corrosion, and have a large degree of freedom in the etchant used, so that the process after copper wiring formation is less restricted, and furthermore, Since the interdiffusion of elements can be prevented, a thin film transistor substrate having a good withstand voltage and a good characteristic of a semiconductor active film can be provided.
  • a method for manufacturing a thin film transistor substrate according to the present invention includes the steps of: forming a metal film selected from titanium, molybdenum, chromium, and tantalum; The target is used to form a copper film. Patterning the copper film and the metal film into a desired wiring shape; and annealing the substrate to form a film of a metal selected from titanium, molybdenum, chromium, and evening on the patterned copper film. Is formed.
  • the annealing condition is about 400 ° C. to 1200 ° C., and is about 30 minutes to 1 hour. If the annealing temperature is lower than 400 ° C., the temperature is too low, and the elements in the metal film cannot be sufficiently drawn into the copper film for forming the wiring. If the temperature exceeds 1200 ° C., the temperature becomes too high, and the copper film melts, and copper wiring with low resistance cannot be formed.
  • a thin film transistor substrate having the wiring of the present invention having any one of the above structures can be manufactured. It consists of a two-frequency excitation type sputtering device using a target made of copper, for example, on a metal film of a substrate on which a metal film selected from titanium, molybdenum, chromium, and tantalum is formed.
  • the element in the metal film can be drawn into the copper film by a film forming step of forming a copper film in a non-oxidizing atmosphere by using the method. Thereafter, a patterning step of patterning the copper film and the metal film into a desired wiring shape is performed to form a copper layer.
  • the metal element drawn into the copper film becomes Since the metal is diffused to the surface of the copper layer, a film of a metal selected from titanium, molybdenum, chromium, and tungsten can be formed around the copper layer.
  • the elements of the metal film thus formed on the substrate are drawn into the copper film when the copper film is formed, and further subjected to an annealing treatment to diffuse the elements of the metal film to the surface of the copper layer, thereby forming a protective layer and a barrier layer.
  • the thickness of the wiring can be reduced as compared with the case where the above-described film is laminated on the copper layer by a sputtering method or the like. Resistance to acid and resist stripper and acid resistance to etching agents and the like can be sufficiently improved.
  • the method for manufacturing a thin film transistor according to the present invention forms a TiN film on a substrate, and then forms a film made of titanium or a titanium oxide on the TiN film.
  • a copper film is formed on the titanium or titanium oxide film by using a copper gate to form a laminated film, and the laminated film is patterned into a desired wiring shape. Is annealed and patterned as described above.
  • the method may be characterized in that a film made of titanium or titanium oxide is formed on the formed copper film.
  • a titanium-based film having a ratio of the number of oxygen atoms to the number of titanium atoms of 1: 0 to 1: 2 can be given.
  • Specific examples of the coating made of titanium or titanium oxide include a titanium coating in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2.
  • the annealing condition is about 30 CTC to about 1200 ° C., and is about 30 minutes to about 1 hour. If the annealing temperature is lower than 300 ° C., the temperature is too low, and the elements in the metal film cannot be sufficiently drawn into the copper film for forming the wiring. A film composed of titanium oxide cannot be formed. When the temperature exceeds 1200 ° C., the temperature becomes too high, so that the copper film is melted and copper wiring having low resistance cannot be formed.
  • the method for manufacturing a thin film transistor substrate having such a configuration it is possible to manufacture a thin film transistor substrate in which the wiring having any one of the above structures is provided via a TiN film.
  • non-oxidation is performed by using a dual frequency excitation type sputtering device using a target made of copper, for example, on a titanium or titanium oxide film formed of a titanium-based film via a TiN film.
  • the film formation step of forming a copper film in an atmosphere the titanium element in the film made of titanium or titanium oxide can be drawn into the copper film.
  • a copper layer is formed by performing a patterning step of patterning a laminated film made of the film made of titanium or titanium oxide and the copper film into a desired wiring shape, and then annealing the substrate with the copper film. Since the titanium element drawn in is diffused to the surface of the copper layer, a coating made of titanium or titanium oxide acting as a protective layer or a barrier layer can be formed around or on the copper layer.
  • the film of the wiring of the thin film transistor substrate manufactured in this manner may be formed around the copper layer or on the surface of the copper layer, and may be formed of titanium or titanium oxide. It can be controlled by controlling annealing conditions such as the thickness of the film made of and the annealing temperature when the substrate is annealed.
  • the film thickness of the titanium or titanium oxide film formed on the TiN film is 10 nm to 20 nm. Is preferred. By setting the thickness of the film made of titanium or titanium oxide to 20 nm or less, the resistance rise is small and the effect of using Cu as a wiring material is remarkably exhibited. On the other hand, even if the thickness of the film made of titanium or titanium oxide exceeds 30 nm, the resistance increases to about the same level as when A1 was used as the wiring material. There is no point in using u.
  • the thickness of the film made of titanium or titanium oxide is less than 1 O nm, a small amount of titanium element diffuses into the surface of the Cu layer by the annealing treatment, and the number of titanium atoms formed around or around the copper layer is reduced.
  • the thickness of the coating made of titanium or titanium oxide having a ratio of the number of oxygen atoms of 1: 0 to 1: 2 is small, and the effect of the protective layer and the barrier layer cannot be sufficiently obtained.
  • the substrate is annealed by removing the oxide layer of titanium formed on the surface of the film made of titanium or titanium oxide by plasma etching before forming the copper film.
  • the annealing temperature for diffusing the titanium element drawn into the copper film to the surface of the copper layer can be reduced.
  • the film formed of the titanium or the titanium oxide is formed on the substrate on which the metal film is formed or via the TiN film.
  • the wiring according to the present invention on the substrate by a film forming step of forming a copper film on the substrate by the two-frequency excitation sputtering method, a step of polishing the copper film, and an annealing step of the substrate. Since it can be easily formed, the manufacturing process is not complicated.
  • the method for manufacturing a thin film transistor substrate of the present invention having any one of the above structures can form the wiring of the present invention on a substrate in a low-temperature step. It can also be applied when used as a substrate.
  • the coating may contain oxygen.
  • a film having a content of oxygen atoms of 0 atomic% can be obtained.
  • the film in the film can be obtained.
  • the content ratio of oxygen atoms can be sequentially increased.
  • the liquid crystal display device is arranged to face each other. Liquid crystal is sandwiched between a pair of substrates, and one of the pair of substrates is the thin film transistor substrate of the present invention having any one of the above structures.
  • the liquid crystal display device of the present invention since the thin film transistor substrate of the present invention using the copper wiring as the low resistance wiring is provided, a signal voltage drop and a wiring delay due to the wiring resistance hardly occur, and the wiring is reduced. There is an advantage that it is possible to easily realize a display device or the like that is optimal for a display with a large area that is long and a high-definition display with thin wiring. Further, the thin film transistor substrate of the present invention is provided, which does not peel off the wiring from the ground, does not cause disconnection failure or corrosion, and can prevent mutual diffusion of elements between the wiring and an adjacent film. Therefore, a liquid crystal display device having good characteristics can be provided. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a diagram showing a cross section of a liquid crystal display device and a thin film transistor substrate according to a first embodiment of the present invention.
  • FIG. 2 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
  • FIG. 3 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
  • FIG. 4 is a configuration diagram illustrating a film forming chamber of a thin film manufacturing apparatus suitably used in the method for manufacturing a thin film transistor substrate according to the embodiment of the present invention.
  • FIG. 5 is a plan view showing the overall configuration of a thin-film manufacturing apparatus suitably used in the method for manufacturing a thin-film transistor substrate according to the embodiment of the present invention.
  • FIG. 6 is an enlarged side view of a part of the thin film manufacturing apparatus shown in FIG.
  • FIG. 7A is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
  • FIG. 7B is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
  • FIG. 7C is a view illustrating one step of a method for manufacturing a thin film transistor substrate of the first embodiment according to the present invention.
  • FIG. 7D shows a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention. It is a figure showing one process.
  • FIG. 8A is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
  • FIG. 8B is a view showing one step of the method for manufacturing the thin film transistor substrate of the first embodiment according to the present invention.
  • FIG. 8C is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
  • FIG. 9 is a diagram showing a cross section of a liquid crystal display device and a thin film transistor substrate according to a second embodiment of the present invention.
  • FIG. 1OA is a view showing one step of the method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
  • FIG. 10B is a view showing one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
  • FIG. 10C is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the second embodiment of the present invention.
  • FIG. 10D is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the second embodiment of the present invention.
  • FIG. 11A is a view illustrating one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
  • FIG. 11B is a view illustrating one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
  • FIG. 11C is a view illustrating one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
  • FIG. 12 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
  • FIG. 13 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
  • FIG. 14 is a diagram showing a cross section of a thin film transistor substrate according to a third embodiment of the present invention.
  • FIG. 15 is a photograph showing the metallographic structure of the surface of the wiring of Example 1 after immersion in the etching solution.
  • FIG. 16 is a photograph showing the metal structure of the surface of the wiring of Example 2 after immersion in the etching solution.
  • FIG. 17 is a photograph showing the metal structure of the surface of the wiring of Comparative Example 1 after immersion in the etching solution.
  • FIG. 18 is a diagram illustrating a result of examining a wiring structure of the wiring according to the first embodiment before the annealing process by the Auger analysis method.
  • FIG. 19 is a diagram showing a result of examining a wiring structure after annealing treatment of the wiring according to Example 1 by Auger analysis.
  • FIG. 20 is a photograph showing the metallographic structure of the surface of the wiring of Example 3 after immersion in the etching liquid.
  • FIG. 21 is a photograph showing the metal structure of the surface of the wiring of Example 4 after immersion in the etching solution.
  • FIG. 22 is a photograph showing the metal structure of the surface of the wiring of Comparative Example 4 after immersion in the etching solution.
  • FIG. 23 is a diagram showing a result of examining a wiring structure of the wiring according to the third embodiment before the annealing treatment by an Auger analysis method.
  • FIG. 24 is a diagram illustrating a result of examining a wiring structure after annealing treatment of the wiring according to the third embodiment by Auger analysis.
  • FIG. 25 is a diagram showing the results of the structure of the test piece 1 examined by the Auger analysis method.
  • FIG. 26 is a diagram showing the results of the structure of the test piece 2 examined by the Auger analysis method.
  • FIG. 28 shows the result of examining the structure of the test piece 3 by Auger analysis.
  • FIG. 28 shows the result of examining the sheet resistance of the laminated films of the test pieces 4 to 8.
  • Figure 29 shows the barrier of the metal film between the a-Si: n + layer and the Cu film of test pieces 4 to 7. It is a figure showing the result of having examined sex.
  • Figure 30 shows the structure of test piece 9 before annealing and the structure of test piece 9 when the annealing temperature was changed from 25 (TC to 500 ° C) by Auger analysis. The results are shown.
  • Figure 31 shows the structure of the test piece 10 before annealing and the structure of the test piece 10 when the annealing temperature was changed from 300 ° C to 500: C by the Auger analysis method.
  • FIG. 9 is a diagram showing the result of an examination by the method shown in FIG.
  • FIG. 32 is a diagram showing the results of examining the sheet resistance of the laminated films of the test pieces 11 to 14.
  • FIG. 33 is a schematic plan view showing a pixel portion of an example of a thin film transistor substrate provided in a conventional liquid crystal display device.
  • FIG. 34 is a cross-sectional view showing the thin film transistor substrate of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a main part of a first embodiment of the liquid crystal display device of the present invention.
  • the liquid crystal display device 30 of the first embodiment is a bottom gate type of the thin film transistor substrate of the present invention.
  • a liquid crystal layer 33 is provided. Similar to the conventional structure shown in FIG. 33, the thin film transistor substrate 31 has a large number of source wirings in a column and a large number of gate wirings in a horizontal row when viewed from the top side of the counter substrate 32 when viewed in plan.
  • a large number of regions arranged in a matrix form and surrounded by a source line and a gate line are each a pixel portion, and a region corresponding to each pixel portion is formed of ITO (indium tin oxide).
  • a pixel electrode 35 made of a transparent conductive material such as that described above is formed, and a bottom gate type thin film transistor is provided near each pixel electrode 35.
  • Figure 1 shows an enlarged view of the thin-film transistor area and its surrounding area provided in the area corresponding to one pixel section surrounded by the source wiring and the gate wiring.
  • a display screen as the liquid crystal display device 30 is formed by arranging a large number of pixel portions in alignment.
  • a gate electrode 40 is provided on a substrate (substrate) 36 having at least an insulating surface in each pixel portion, and the gate electrode 40 and the substrate A gate insulating film 41 is provided to cover 36, and a semiconductor active film 42 smaller than the gate electrode (wiring) 40 is laminated on the gate insulating film 41 on the gate electrode 40.
  • Ohmic contact films 43, 44 consisting of nt layers, etc. on both ends of film 42.Align with the ends of semiconductor active film 42, leaving a gap at the center of semiconductor active film 42.
  • the layers are separated from each other.
  • the substrate 36 a glass substrate or a substrate on the surface of which a SiN x film 36a is formed can be used.
  • the gate electrode 40 has a coating 40b around a copper layer 40a.
  • the coating 40b is any one of a coating made of titanium or titanium oxide, a coating made of molybdenum or molybdenum oxide, chromium or chromium oxide, and a coating made of tantalum or tan oxide.
  • a film made of titanium or titanium oxide a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2 is exemplified.
  • a film made of molybdenum or molybdenum oxide a film having a composition in which the ratio of the number of oxygen atoms to the number of molybdenum atoms is 1: 0 to 1: 3 can be given.
  • a coating made of chromium or chromium oxide a coating having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 0 to 1: 1.5 is mentioned.
  • the coating 4 Ob may include a titanium film and a film made of titanium oxide.
  • the ratio of the number of oxygen atoms to the number of titanium atoms is 1 And a film having a composition of 1 to 1 to 2, More specifically, as shown in FIG. 2, the titanium film 40 f formed around the copper layer 40 a and the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the titanium film 40 f are A film having a composition of titanium oxide, such as a film having a composition of 1: 1 or 1: 2, or a portion formed around a copper layer 40a as shown in FIG.
  • a titanium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed around the copper layer 40a is 1: 1 to 1: 2.
  • the film 40 may be a film having a chromium film and a film made of chromium oxide. Specific examples include a chromium film, and oxygen with respect to the number of chromium atoms. And a film having a composition in which the ratio of the number of atoms is 1: 1 to 1: 2, and more specifically, around the copper layer 40a.
  • a chromium film formed, and a film made of chromium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms formed on the surface of the chromium film is 1: 1 to 1: 2.
  • the ratio of the number of oxygen atoms to the number of chromium atoms formed on a part of the periphery of the copper layer 40a and the chromium film formed on the rest of the periphery of the copper layer 40a is 1: 1.
  • a film made of chromium oxide such as a film having a composition of 1 to 1: 2.
  • a source electrode 46 is formed so as to cover a part of the upper surface of the gate insulating film 41, that is, to cover an overlapping portion (overlapping portion) of the semiconductor active film 42 and the ohmic contact film 43.
  • the source electrode 46 here has a coating 46b around the copper layer 46a.
  • the coating 46 b is made of the same coating as the coating 40 b of the gate electrode 40.
  • the coating 46 b is made of a titanium film, a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2, or the like. And a film made of titanium oxide.
  • a drain electrode 48 is formed so as to cover the overlapping portion of the contact layer 43.
  • the drain electrode 48 here has a coating 48b around a copper layer 48a.
  • the coating 48 b is made of the same coating as the coating 40 b of the gate electrode 40.
  • the coating 48 b is, like the coating 40 b of the gate electrode 40, a titanium film and a composition film in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2. And a film made of titanium oxide.
  • a passivation film 49 is provided on each of these films to cover them, and a pixel electrode 35 is formed on the passivation film 49 on the right end of the drain electrode 48.
  • the pixel electrode 35 is connected to a drain electrode via a connection conductor 51 provided in a contact hole (conduction hole) 50 formed in the passivation film 49.
  • a color filter 52 and a common electrode film 53 are laminated in order from the opposing substrate 32 side.
  • the color filter 52 is composed of a black matrix for covering the thin film transistor part that does not contribute to the display and the gate wiring and source wiring.
  • the pixel region 35 is made up mainly of a color pixel portion 55 for transmitting light passing through a portion contributing to display and for performing color display.
  • These color pixel portions 55 are required when the liquid crystal display device has a color display structure, and are provided for each pixel portion.
  • R for example, R ( The three primary colors of red), G (green) and B (blue) are arranged regularly or randomly so that there is no color bias.
  • the alignment film provided on the liquid crystal side of 32 is omitted, and the polarizing plates provided on the outside of the thin film transistor substrate 31 and the outside of the counter substrate 32 are omitted.
  • an oxidizing acid-based etching agent used for etching another layer in a later process is used for the gate electrode 40 and the like.
  • each electrode is damaged by the etching agent. It is less susceptible to damage, prevents each electrode from peeling off from the base, and prevents the occurrence of disconnection failure. Also, the degree of freedom of the etching agent used is large.
  • the gate electrode 40, the source electrode 46, and the drain electrode 48 have the above-mentioned coatings 40b, 46b, 48b on the outer peripheral surface of the copper layer 40a, 46a, 48a, respectively. Since it is formed, an oxide layer is not formed on the surface of each electrode due to the presence of moisture before etching, and the electrode is less likely to be damaged by an etching agent having no oxidizing power, thereby preventing the occurrence of disconnection failure.
  • the gate electrode 40, the source electrode 46, and the train electrode 48 have the coatings 4Ob, 46b, and 48b, respectively, the insulating film 41
  • the reaction between Cu constituting the electrodes 40, 46, and 48 and the Si gas of the forming material such as the insulating film can be prevented. Needle-like projections do not occur on the surface of the copper layer, and the needle-like protrusions can prevent insulation failure from occurring.
  • the gate electrode 40, the source electrode 46, and the drain electrode 48 are formed on the outer surfaces of the copper layers 40a, 46a, and 48a, respectively, as the coatings 40b, 46b acting as barrier layers. , 48b are formed, so that even if Si diffuses from the substrate 36, diffusion of atoms to the gate electrode 40 is inhibited by the coating 40b, and the resistance of the gate electrode 40 increases. In addition, even if Cu atoms diffuse from the copper layer 40a into the gate insulating film 41, the coating 40b inhibits the diffusion of the Cu atoms into the gate insulating film 41.
  • the oxidation resistance to moisture and oxygen can be improved without impairing the characteristics of using low-resistance copper as a wiring material, and the resistance to an etching agent, a resist stripping solution, and the like can be improved.
  • the liquid crystal display device 30 of the first embodiment since the thin film transistor substrate 31 as described above is provided, a signal voltage drop or a wiring delay due to wiring resistance is unlikely to occur, and the wiring becomes longer. There is an advantage that a display device optimal for large-area display and high-definition display in which wiring is narrow can be easily realized.
  • the thin film transistor substrate 31 is provided, which does not peel off the wiring from the base, does not cause disconnection failure or corrosion, and prevents mutual diffusion of elements between the wiring and the adjacent film. A good liquid crystal display device can be provided.
  • FIG. 4 is a schematic configuration diagram illustrating a film forming chamber of a thin film manufacturing apparatus suitably used in the thin film transistor substrate manufacturing method according to the first embodiment.
  • FIG. 5 is a plan view illustrating an overall configuration of the thin film manufacturing apparatus.
  • FIG. 6 is a side view in which a part of the thin film manufacturing apparatus shown in FIG. 5 is enlarged.
  • FIG. 4 shows a film forming chamber capable of maintaining a reduced pressure.
  • the film forming chamber 60 is connected to the side of the transfer chamber 61 via a gate valve 62 as shown in FIG.
  • a single chamber 63, an unloading chamber 64, and a stocker chamber 65 are connected so as to surround the transfer chamber 61, respectively.
  • Gate valves 66, 67, 68 are provided between the transfer chamber 61 and each of the surrounding rooms.
  • the film forming chamber 60, the transfer chamber 61, and the low chamber, the “chamber 63 and the low chamber”, one chamber 64, and the stocker chamber 65 constitute the thin film manufacturing apparatus A ′. I have.
  • a first electrode 70 is provided above the film forming chamber 60.
  • a target 71 is removably mounted on the bottom surface of the first electrode 70, and a second electrode 72 is provided at the bottom of the film forming chamber 60.
  • a substrate 36 having at least an instable surface is detachably mounted on the upper surface.
  • the target 71 is made of a metal selected from titanium, molybdenum, chromium, tantalum, and copper.
  • a metal selected from titanium, molybdenum, chromium, tantalum, and copper.
  • P-doped Si for n-type a—Si: n + generation is used.
  • a glass substrate can be suitably used as the substrate 36 when a thin film transistor substrate is manufactured.
  • the target 71 can be mounted using a generally known evening target mounting mechanism such as an electrostatic chuck.
  • the first electrode 70 includes a base 70a made of a conductive material and a protective layer 70b formed of an oxide film, a nitride film, a fluoride film, or the like formed on the surface of the base 70a. It is configured.
  • a first AC power supply 75 is connected to the first electrode 70, and a matching circuit 75a is incorporated between the first electrode 70 and the first AC power supply 75.
  • the matching circuit 75a has an effect of reducing the reflected wave of the high-frequency power to zero.
  • a DC power supply 78 is connected to the first electrode 70 via a band-pass filter 7 such as a low-pass filter for impedance adjustment. This bandpass filter 77 adjusts the impedance of the circuit to infinity so that high frequency does not get on the DC power supply 78.
  • a second AC power supply 80 is also connected to the second electrode 72, and the same as the matching circuit 75a between the second electrode 72 and the second AC power supply 80.
  • a matching circuit 80a having the function of (1) is incorporated.
  • the film forming chamber 60 includes an exhaust unit 60a for evacuation and gas exhaust, a reaction gas supply mechanism 60b into the film forming chamber 60, etc. These are simplified and described for simplification.
  • a link-type transfer mechanism (magic hand) 69 is provided in the transfer chamber 61, and the transfer mechanism 69 is provided with a support shaft 74 erected at the center of the transfer chamber 61.
  • a cassette 7 rotatably provided as a fulcrum and disposed in the stocker chamber 65
  • the evening getter 71 is taken out from the container 9 and transported to the film forming chamber 60 as necessary, so that the evening getter 71 can be mounted on the first electrode 70 of the film forming chamber 60.
  • the cassette 79 also contains a dummy target 71a, so that the dummy target 71a can be transported to the film forming chamber 60 as necessary.
  • the thin film manufacturing apparatus shown in FIGS. 4 to 6 includes one or more thin films (for example, a metal film and a copper film for forming the gate electrode 40, a gate insulating film 41) in one deposition chamber 60. , A semiconductor active film 42, an ohmic contact film 43, 44, a metal film and a copper film for forming a source electrode 46, and a metal film and a copper for forming a drain electrode 48. This is an apparatus capable of continuously forming a film and a passivation film 49).
  • a CVD film formation film formation of a gate insulating film, a semiconductor active film, a passivation film 49
  • a sputtering film formation an ohmic contact film, a gate electrode
  • Metal film and copper film for forming a metal film and a copper film for forming a source electrode, and forming a metal film and a copper film for forming a drain electrode).
  • the gate valves 62 and 68 are opened, and the glass substrate 36 is transferred to the second electrode by the transfer mechanism 69. 7 Attach to 2.
  • the gate valve 62 is closed from this state, thin films such as the gate electrode 40 are sequentially formed on the substrate 36 according to the following procedure.
  • the film forming chamber 60 is set to an Ar gas atmosphere, and a target 71 made of a metal selected from titanium, molybdenum, chromium, and tantalum is mounted on the first electrode 70, and the second electrode 70 While a glass substrate 36 is attached to 72, a high frequency of about 13.6 MHz is supplied to the first AC power supply 75 to the first electrode 70, and a direct current power supply 7 Sputtering is performed with the load potential applied from 8 set to 120 V, and a metal film 40 e having a thickness of about 50 nm is formed on the substrate 36 as shown in FIG. 7A.
  • a metal oxide layer may be formed on the surface of the metal film 40 e by a reaction between a metal element constituting the metal film 40 and residual oxygen in the film formation chamber 60.
  • the film forming chamber 60 was set to an Ar gas atmosphere, With the dummy target 71 a attached to the first electrode 70 and the glass substrate 36 on which the metal film 40 e is formed attached to the second electrode 72, the first AC power supply 75 A high frequency is supplied to the first power source 70, a load potential is floated to generate plasma, and a high frequency power is supplied to the second electrode 72 to supply about 200 W AC power to the substrate 36. This is performed by applying for about 2 minutes.
  • the film forming chamber 60 is a non-oxidizing atmosphere and an Ar gas atmosphere, and the first electrode 70 is equipped with a copper gate 71 and the second electrode is kept with the glass substrate 36 attached. Then, the DC power supply 78 is operated to apply DC power to the evening getter 71, and the second AC power supply 80 is operated to apply AC power to the glass substrate 36. Then, a copper film is formed by sputtering, and a copper film 40c having a thickness of about 150 nm is formed on the metal film 40e formed on the substrate 36 as shown in FIG. 7B. In this step, the AC power applied to the substrate 36 is about 0.1 to 5 WZ cm 2 . By doing so, the grain size of the Cu crystal constituting the copper film 40c can be reduced, so that the grain boundary of the Cu crystal increases, and the elements in the metal film 40e It is drawn into 0 c, and the diffusion of the drawn element is promoted.
  • a resist was applied to the surface of the copper film 40c and subjected to pattern exposure. After removing unnecessary portions of the copper film 40c and the metal film 40e by etching, patterning was performed to remove the resist. A laminated film of a copper layer (copper wiring) 40a and a metal film 40e having a desired line width as shown in C is formed.
  • the substrate 36 on which the laminated film of the copper layer 40a and the metal film 40e is formed is subjected to an annealing treatment in an Ar gas atmosphere, and the metal element of the metal film 40e drawn into the copper layer 40a. Is diffused to the surface of the copper layer 40a, and a metal film 40 selected from titanium, molybdenum, chromium, and tantalum is formed around the copper layer 40a as shown in FIG. 7D. Obtained gate electrode 40 is obtained.
  • the thickness of the coating 40b formed here is about 5 nm to 20 nm.
  • the annealing treatment conditions here are about 400 ° C. for about 2 hours.
  • a film 40b having an oxygen atom content of 0 atomic% is obtained.
  • the content ratio of oxygen atoms in the coating 40b can be sequentially increased.
  • a coating 40 b made of titanium or titanium oxide is formed, and more specifically, the number of oxygen atoms with respect to the number of titanium atoms
  • a coating 40b made of molybdenum or molybdenum oxide is formed.
  • a coating 40b having a composition in which the ratio of the number of oxygen atoms to the number of molybdenum atoms is 1: 0 to 1: 3 is formed, and the metal film 40e made of chromium is formed
  • a coating 40b made of chromium or chromium oxide is formed, and more specifically, a coating 40b having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 0 to 1: 2 is formed
  • a metal film made of tantalum 40 e is formed, tantalum Or a film 40b made of tantalum oxide, and more specifically, a film 40b having a composition in which the ratio of the number of oxygen atoms to the number of tantalum atoms is 1: 0 to 1: 2.5.
  • FIG. 2 by changing the thickness of the metal film 40e made of titanium and the anneal temperature in the range of 400 ° C. to 1200 ° C. and the anneal time in the range of 30 minutes to 1 hour, FIG. As shown in FIG. 2, the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the titanium film 40f formed on the periphery of the copper layer 40a and the titanium film 40f is 1: 1-1.
  • a film 40 g comprising a film of titanium oxide, such as a film having a composition of 1 to 2, having a thickness of 40 g, which is formed on a part of the periphery of the copper layer 40 a as shown in FIG.
  • Titanium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed in the remainder around the copper layer 40a is 1: 1 to 1: 2.
  • the film 40b having the film 40i and the film 40b can be formed.
  • the film forming chamber 60 is set to a mixed gas atmosphere of SiH + NH + N2, a dummy electrode 1a is attached to the first electrode 70, and the first electrode power supply 75 to the first electrode 70
  • a high frequency of 20 OMHz is supplied to the substrate, and a load potential is floated to generate plasma to deposit a silicon nitride film on the substrate 36.
  • a gate insulating film 41 as shown is formed.
  • the frequency supplied to the dummy electrode 71a mounted on the first electrode 70 so as not to spatter is set to a large value, and the ion energy applied to the first electrode 70 is reduced.
  • high-frequency power is supplied to the second electrode 72 to control ion energy applied to the substrate 36.
  • the film formation chamber 60 is set to a mixed gas atmosphere of Si +, and the first AC power supply 75 is supplied to the first electrode 70 while the dummy electrode 71 1a is attached to the first electrode 70.
  • a high frequency of about MH z is supplied, and a high frequency power is supplied from the second AC power supply 80 to the second electrode 72 to control the ion energy applied to the glass substrate 36 to form the a-Si layer. Then, a semiconductor active film 42 is formed.
  • Ohmic contact film (a- S i: n + layer) 43 a sputter deposition process
  • the film forming chamber 60 is set to an Ar gas atmosphere, and a first electrode 70 made of P-doped Si for a—Si: n + layer formation is mounted on the first electrode 70.
  • a high frequency having a frequency of about 13.6 MHz is supplied to the first electrode 70, and a sputtering is performed by setting the load potential applied from the DC power supply 78 to 1200 V, and the ohmic contact film 43 is formed on the semiconductor active film 42.
  • the film is formed so as to cover the upper surface and both side surfaces of the ohmic contact film 43a, the both side surfaces of the semiconductor active film 42 therebelow, and a part of the upper surface of the gate insulating film 41 continuous therewith.
  • the metal film 46 e having a thickness of about 50 nm is used as the metal film for the gate electrode described above.
  • the film is formed in the same manner as the film forming process.
  • a metal oxide layer is formed on the surface of the metal film 46 e. In this case, the metal oxide layer is subjected to plasma etching of the metal film 40 e described above. It is preferable to remove them in the same manner as in the method.
  • the upper portion of the central portion of the semiconductor active film 42 is removed by etching, and the ohmic contact film 43 a, the metal film 43 a, and the copper film 46 e on the central portion of the semiconductor active film 42 are removed.
  • ohmic contact films 43, 44 spaced apart from each other on both ends of the semiconductor active film 42, a metal film 46 e for forming a source electrode 46, and a copper layer 46. a, the drain electrode 48 forming metal film 46 e and the copper layer 48 a can be formed.
  • Substrate 36 on which metal film 46 e for forming source electrode 46 and copper layer 46 a and metal film 46 e for forming drain electrode 48 and copper layer 48 a are formed first The metal element of the metal film 46 e drawn into the copper layers 46 a and 48 a is subjected to an annealing treatment in the same manner as in the first annealing step of FIG. Around the copper layers 46a and 48a, as shown in Fig. 8C, forming a film 46b and 48b of a metal selected from titanium, molybdenum, chromium, and tungsten. The source electrode 46 and the drain electrode 48 thus obtained are obtained.
  • the coatings 46 b and 48 b formed here may contain oxygen in the above-described ratio, similarly to the coating 40 b of the gate electrode 40. Also, by changing the thickness of the metal film 46 e and the annealing conditions as in the case of forming the coating 40 b of the gate electrode 40, the titanium film formed around the copper layer and the titanium film are removed.
  • a film comprising a film of titanium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the film is 1: 1 to 1: 1 2 4 6 b, 48b, and the ratio of the number of oxygen atoms to the number of titanium atoms formed on the titanium film formed on a part of the periphery of the copper layer and the remainder on the periphery of the copper layer is 1: 1 to 1: 2.
  • Coatings 46 b and 48 b comprising titanium oxide film 40 i such as a film of a certain composition can be formed.
  • a passivation film 49 made of silicon nitride is formed so as to cover the semiconductor active film 42, the source electrode 46, and the drain electrode 48 in substantially the same manner as the CVD film forming process of the gate insulating film 41.
  • the passivation film 49 is etched by a dry method or a combination of a dry method and a wet method to form a contact hole 50, and then, an ITO layer is formed on the nomination film 49 and patterned.
  • a pixel electrode 35 is formed, and as shown in FIG. 1, a connection conductor 51 is formed over the bottom and inner wall surfaces of the contact hole 50 and the upper surface of the passivation film 49, and this connection conductor 51 is formed.
  • the drain electrode 48 and the pixel electrode 35 are connected through the same, a thin film transistor substrate 31 similar to that of FIG. 1 is obtained.
  • the above-mentioned CVD of the gate insulating film 41 is performed before forming the metal film 40 e on the substrate 36.
  • a SiNx film is formed in the same manner as in the film process.
  • the source wiring may be formed at the same time as film formation, annealing, and etching when forming the source electrode 46 on the gate insulating film 41.
  • a film forming step of forming a copper film by a two-frequency excitation sputtering method on the substrate 36 on which the metal film is formed By the evening process and the annealing process of the substrate, the oxidation resistance to moisture and oxygen can be improved, and the corrosion resistance to an etching agent and a resist stripping solution can be improved, and the adhesion to the base can be improved. Further, since the gate electrode 40, the source electrode 46, and the drain electrode 48, which can prevent mutual diffusion of elements between adjacent films, can be easily formed on the substrate 36, the manufacturing process does not become complicated.
  • the gate electrode 40, the source electrode 46, and the drain electrode 48 having the above-described characteristics can be formed on the substrate 36 in a low-temperature process.
  • the present invention can be applied to a case where a glass substrate or the like that cannot withstand heating of C or more is used as a base.
  • FIG. 9 shows a main part of a liquid crystal display device according to a second embodiment of the present invention.
  • the liquid crystal display device 30a of the second embodiment differs from the liquid crystal display device 3 of the first embodiment shown in FIG.
  • the difference from 0 is that a bottom-gate thin film transistor substrate 31a having a configuration as shown in FIG. 9 is provided as a thin film transistor substrate.
  • the thin film transistor substrate 31 a is different from the thin film transistor substrate 31 shown in FIG. 1 in that a TiN layer 45 a is provided on the surface of the gate electrode 40 on the glass substrate 36 side, and the source electrode 46
  • the TiN layer 47a is provided on the surface on the side of the ohmic contact film 43
  • the TiN layer 47b is provided on the surface on the side of the ohmic contact film 44 of the drain electrode 48. Is a point.
  • the source electrode 46 is electrically connected to the atomic contact film 43 and the semiconductor active film 42 via the TiN layer 47a.
  • the drain electrode 48 is electrically connected to the ohmic contact film 44 and the semiconductor active film 42 via the TiN layer 47b.
  • the thin film transistor substrate 31a according to the second embodiment has the same configuration and effect as the thin film transistor 31 according to the first embodiment due to the above configuration. Furthermore, in the second embodiment, the TIN layers 45a, 47a, and 47b are provided between the electrodes 40, 46, and 48 and the substrate 36, so that Even if elements are diffused from the substrate 36-gate insulating film 41, which is an adjacent film below each electrode, the electrodes 40, 46 are formed by the TiN layers 45a, 47a, and 47b. The diffusion of atoms into the substrate 48 and 48 is inhibited, and the effect of preventing an increase in wiring resistance due to the diffusion of elements from the substrate 36 or an adjacent film is excellent. In addition, the denseness of the electrodes 40, 46, and 48 is achieved by the TIN layers 45a, 47a, and 47b. The wearability is improved.
  • This thin film transistor substrate 31 can also be manufactured by using the thin film manufacturing apparatus shown in FIGS.
  • the film forming chamber 60 is set to a gas atmosphere containing N, and a first electrode 71 made of titanium is mounted on the first electrode 70, a glass substrate 36 is mounted on the second electrode 72, and a first AC power supply 75 A high frequency having a frequency of about 13.6 MHz is supplied to the first electrode 70 from above, and the load potential applied from the DC power supply 78 is further set to 1200 V, and sputtering is performed. As shown in FIG. Then, a TiN film 45 having a thickness of about 50 nm is formed.
  • a mixed gas of a gas such as, ⁇ , ⁇ , NO ′ and an Ar gas is used.
  • the film formation chamber 60 is changed from a gas atmosphere containing N to an Ar gas atmosphere, and the target 71 to be mounted on the first electrode 70 is selected from titanium, molybdenum, chromium, and tantalum, and any one of the metals is selected. 10B, the film thickness is formed on the TiN film 45 formed on the substrate 36 as shown in FIG. A metal film 40e of about 50 nm is formed.
  • a copper film 40c having a thickness of about 150 nm is formed on the metal film 40e as shown in FIG. 10B by a method similar to the dual frequency excitation sputtering film formation step (1-2) described above.
  • a laminated film 57 including the TiN film 45, the metal film 40e, and the copper film 40c is formed. By doing so, the elements in the metal film 40e are drawn into the copper film 40c.
  • TiN layer 45a remains interposed between the gate electrode 40 and the substrate 36.
  • a CVD film forming process is performed to deposit a silicon nitride film on the substrate 36 to form a gate insulating film 41 as shown in FIG. 11A. I do.
  • An a-Si layer is formed on the gate insulating film 41 to form the semiconductor active film 42 in the same manner as in the above-mentioned CVD film forming step of the semiconductor active film (1-16).
  • An ohmic contact film 43a is formed on the semiconductor active film 42 in the same manner as the above (1-7), the ohmic contact film sputtering step.
  • the film formation chamber 60 is set to a gas atmosphere containing N in the same manner as in the above step (2-1), a titanium electrode 71 is attached to the first electrode 70, and a glass substrate is attached to the second electrode 72.
  • a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70, and the load potential applied from the DC power supply 78 is further reduced.
  • Sputtering was performed at -200 V, and as shown in Fig. 11A, the upper surface and both side surfaces of the omnidirectional contact film 43a, the both side surfaces of the semiconductor active film 42 therebelow, and gates continuous to them.
  • a TiN film 47 having a thickness of about 50 nm is formed so as to cover a part of the upper surface of the insulating film 41.
  • a metal film 46e having a thickness of about 50 nm is formed on the TiN film 47 in the same manner as the above-described step of forming the gate electrode metal film.
  • (2-1 2) Dual frequency excitation sputtering film formation process of copper film for source electrode and drain electrode As shown in Fig. 11A, a copper film 46c with a thickness of about 150 nm is formed on the metal film 46e.
  • a copper film for a gate electrode is formed in the same manner as in the two-frequency excitation sputtering film forming process to obtain a laminated film 58 including a TiN film 47, a metal film 46e, and a copper film 46c. By doing so, the elements in the metal film 46e are drawn into the copper film 46c.
  • 36 is annealed in the same manner as in the first annealing step of the substrate, and the metal element of the metal film 46e drawn into the copper layers 46a and 48a is removed from the copper layers 46a and 48a.
  • a passivation film 49 made of silicon nitride is formed so as to cover the semiconductor active film 42, the source electrode 46, and the drain electrode 48 in substantially the same manner as the CVD film forming process of the gate insulating film 41.
  • an ITO layer is formed on the passivation film 49 and patterned.
  • a connection electrode 51 over the bottom and inner wall of the contact hole 50 and the upper surface of the passivation film 49, as shown in FIG.
  • a thin film transistor substrate 31a having a structure as shown in FIG. 9 can be manufactured.
  • a copper layer 40 a has a coating 40 b having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1 to 0 to 1 to 2 on the surface of the copper layer 40 a.
  • a coating 40 b having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1 to 0 to 1 to 2 on the surface of the copper layer 40 a.
  • the gate electrode 40 and the titanium film 4 O m formed on the surface of the copper layer 40 a and the oxygen atoms with respect to the number of titanium atoms formed on the surface of the titanium film 4 O m A gate electrode 40 having a film 40n having a composition in which the number ratio is 1: 1 to 1: 2 is obtained.
  • the source electrode 46 and the drain electrode 48 also include a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2 on the surface of the copper layer, A film having a titanium film formed on the surface of the layer and a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the titanium film is 1: 1 to 1: 2 is obtained. .
  • the electrodes 40, 46, 48 obtained in this way are provided with coatings 40b, 46b, 48b on the lower surface side of the copper layers 40a, 46a, 48a. Not force electrode 4 0, 4 Since the TiN layers 45a, 47a, and 47b are provided between 6, 48 and the substrate 36, the substrate 36, which is the adjacent film below each electrode, and the gate insulation Even if the element diffuses from the film 41 etc., the diffusion of atoms to the electrodes 40, 46, 48 is inhibited by the TiN layers 45 a, 47 a, 47 b, and the substrate 36 or adjacent It has an excellent effect of preventing an increase in wiring resistance due to diffusion of elements from the film.
  • the thin film transistor substrate 3 lb of the third embodiment is provided with a top gate type TFT, and as shown in FIG. 14, for example, a semiconductor layer 1 made of polycrystalline silicon is formed on a transparent substrate 102 such as glass. 0 3 is formed, and a gate insulating film 104 made of SiN x or the like is formed on the central portion thereof.
  • the gate electrode 1 is formed on the gate insulating film 104 via the TiN layer 101 a. 0 5 is formed.
  • the gate electrode 105 has a film 105b made of the same material as the film 40b of the second embodiment on the surface of the copper layer 105a. Note that the gate electrode 105 is formed integrally with a gate wiring (not shown).
  • the n-semiconductor layer forming the source region 107 and the drain region 108 is formed so as to penetrate below the end of the gate insulating film 104.
  • silicide films 110 such as tungsten silicide and molybdenum silicide are formed on the surfaces of the source region 107 and the drain region 108, respectively.
  • the source wiring 1 1 1 and the source electrode 1 1 2 are formed via the T i N layer 1 2 5 a, and the drain electrode 1 via the T i N layer 1 2 5 b is formed on the other silicide film 110. 13 are formed.
  • the source wiring 111 and the source electrode 112 have a coating 112 b made of the same material as the coating 46 b of the second embodiment on the surface of the copper layer 112 a. It becomes.
  • Drain electrode 1 1 3 is copper layer 1 On the surface of 13a, a film 113b made of the same material as the film 48 of the second embodiment is provided.
  • a passivation film 114 is formed so as to cover the entire surface, and a contact hole 111 through the passivation film 114 to reach the drain electrode 113 is formed.
  • the passivation film 114 covering the gate wiring and the source wiring is opened at the gate terminal at the gate wiring end and at the source terminal at the source wiring end, similarly to the contact hole 115 described above.
  • a pad composed of an ITO is provided to be connected to the gate wiring and the source wiring, respectively.
  • a film 105b, 112b, 111 is formed on the surface of the copper layers 105a, 112a, 113a constituting electrodes and wiring. Since 3b is formed, the oxidation resistance to moisture and oxygen can be improved, and the corrosion resistance to an etching agent / resist stripper can be improved. Between the gate electrode 105, the source wiring 1 1 1 and the source electrode 1 1 2 and the drain electrode 1 1 3 and the substrate 102 are provided TiN layers 101a, 125a and 125b, respectively.
  • the TiN layer 101 a, 125 a, 125 b Accordingly, diffusion of atoms is hindered, and the effect of preventing an increase in wiring resistance due to diffusion of elements from the substrate 102, the gate insulating film 104, and the like is excellent. Further, the adhesion of the gate electrode 105, the source wiring 111, the source electrode 112, and the drain electrode 113 is improved by the TiN layers 101a, 125a, and 125b.
  • the film forming chamber 60 was set to an Ar gas atmosphere, and an evening getter 71 made of titanium was attached to the first electrode 70, and the second electrode 7 was made.
  • a 2 inch 6-inch square glass substrate is attached to 2
  • a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70, and a load is further applied from the DC power supply 78.
  • Sputtering was performed at a potential of -200 V to form a 50-nm-thick titanium film on a glass substrate.
  • the film formation chamber 60 was set to an Ar gas atmosphere, an evening get 71 made of copper was attached to the first electrode 70, and a DC voltage was applied while the glass substrate was attached to the second electrode 72.
  • the titanium A 150 nm thick Cu film was formed on the film.
  • the AC power applied to the glass substrate here was 200 W.
  • a resist is applied to the surface of the Cu film, pattern exposure is performed, an unnecessary portion of the Cu film and the titanium film is removed with an etching agent, and then the photosensitive resist is removed.
  • a layer stack was formed.
  • the substrate on which the above-mentioned laminated film was formed was subjected to annealing treatment at 400 ° C. for 2 hours in a nitrogen gas atmosphere, thereby producing a wiring.
  • annealing treatment at 400 ° C. for 2 hours in a nitrogen gas atmosphere.
  • the thickness was 10 nm.
  • specific resistance of the wiring of Example 1 was measured, it was 0.27 ⁇
  • Wiring was produced in the same manner as in Example 1 except that the AC power applied to the glass substrate was set to 100 W.
  • the structure of the wiring obtained in Example 2 was examined by Auger analysis, it was found that the film containing Ti was formed around the copper layer. The thickness was 8 nm. Further, the specific resistance of the wiring layer of Example 2 was measured and found to be 0.23 ⁇ / port.
  • Wiring was fabricated in the same manner as in Example 1 except that the AC power applied to the glass substrate was set to 0 W.
  • the structure of the wiring obtained in Comparative Example 1 was examined by Auger analysis, it was found to be a structure in which a film containing Ti was formed around the copper layer, and the thickness of the film on the copper layer was 4 nm.
  • the specific resistance of the wiring of Comparative Example 1 was measured and found to be 0.23 ⁇ square.
  • the film forming chamber 60 was set to an Ar gas atmosphere, and a first electrode 71 made of copper was mounted on the first electrode 70, and the second electrode was A glass substrate is mounted on 72, and a DC power supply 78 is operated to apply DC power to the evening target 71, and a second AC power supply 80 is operated to apply AC power to the glass substrate.
  • a 150 nm-thick Cu film was formed by the dual frequency excitation sputtering method.
  • the AC power applied to the glass substrate here was 200 W.
  • Wiring was produced in the same manner as in Comparative Example 2 except that the AC power applied to the glass substrate was set to 100 W.
  • the specific resistance of the wiring obtained in Comparative Example 3 was measured, it was 0.18 ⁇ / port.
  • FIGS. 15 to 17 The chemical resistance of the wirings obtained in Examples 1 and 2 and Comparative Examples 1 to 3 was examined.
  • the chemical resistance here is as follows. Each wiring is immersed in an ammonium persulfate etching solution for 60 seconds, these are removed from the stripping solution, rinsed, and dried. The condition was evaluated by observing it with an atomic force microscope (AFM). The results are shown in FIGS. 15 to 17.
  • FIG. 15 is a photograph showing the metal structure of the wiring surface of Example 1 after immersion in an ammonium persulfate etching solution.
  • FIG. 16 is a photograph showing the metallographic structure of the wiring surface of Example 2 after immersion in an ammonium persulfate etching solution.
  • FIG. 17 is a photograph showing the metal structure of the wiring surface of Comparative Example 1 after immersion in an ammonium persulfate etching solution.
  • the wiring of Example 1 before annealing was equivalent to 132 nmZ, and the wiring of Example 1 after annealing was compared with the wiring before annealing after a holding time of about 3 minutes.
  • 132 nm / min the wiring of Example 2 before annealing is 12.6 nm mZ, and the wiring of Example 2 after annealing is 1 minute or more after holding time and before annealing.
  • the wiring of Comparative Example 1 before annealing is 128 nm / min, the wiring of Comparative Example 1 after annealing is less than 1 minute, and the wiring before annealing is thereafter
  • the amount of 1 282 n mZ, the wiring of Comparative Example 2 was 1 279 nm mZ, the wiring of Comparative Example 3 was 1 278 n mZ, and even after the same annealing as in Example 1 was performed. Etching Great did not change.
  • the AC power applied to the substrate was 0 W, and the wirings and the copper layers of Comparative Example 1 of Comparative Example 1 were formed.
  • the wiring has a large etching rate with the etchant immediately after the start of the etching, and the wiring of Comparative Example 1 has the copper film etched over almost the entire surface (surface protection rate is 7%), and the wiring is greatly damaged by the etching liquid.
  • Examples 1 and 2 have a holding time in which the etching does not proceed for about 1 minute or more, and the surface protection ratio of the wiring of Example 1 where the AC power applied to the substrate is 200 W is 9 W
  • the surface protection ratio of the wiring in Example 2 where the AC power applied to the substrate was 0% and the AC power applied to the substrate was 100 W was 60%, and the state of the wiring surface before and after immersion in the etching solution was not significantly changed.
  • the drug solution resistance is superior to that of Comparative Example 1.
  • the surface protection ratio is the ratio of the total area of the surface portion remaining after the immersion in the etching solution to the surface area (100%) of the wiring before the immersion in the etching solution. Further, in the wiring of Example 2, the specific resistance before and after annealing does not change much.
  • FIGS. 18 to 19 show the results of the wiring analysis of the wiring of Example 1 before and after the annealing process, using the age analysis method.
  • FIG. 18 shows a depth profile of the wiring of the first embodiment before the annealing process
  • FIG. 19 shows a depth profile of the wiring of the first embodiment after the annealing process.
  • the Ti content between the glass substrate and the Cu layer is large, and the Ti layer contains a small amount of Ti. Further, it can be seen that Ti is hardly contained on the surface of the Cu layer.
  • the reason why Ti is included in the Cu layer is that AC power was applied to the substrate when Cu was deposited by sputtering.
  • the Ti content between the glass substrate and the Cu layer becomes smaller than before the annealing treatment, and the Ti and the Ti layer on the surface side of the Cu layer become less. An O peak was observed, indicating that Ti and O on the surface of the Cu layer were larger than before the annealing treatment. From these facts, it can be seen that Ti was diffused to the surface of the Cu layer by performing the annealing treatment.
  • a wiring was produced in the same manner as in Example 1 except that a chromium film was formed on a glass substrate using a chromium target 71 instead of the titanium target 71.
  • the specific resistance of the wiring layer of Example 3 was 0.14 ⁇ / cm.
  • Wiring was manufactured in the same manner as in Example 3 except that the AC power applied to the glass substrate was set to 100 W.
  • the specific resistance of the wiring layer of Example 4 was measured and found to be 0.14 ⁇ .
  • Wiring was fabricated in the same manner as in Example 3 except that the AC power applied to the glass substrate was set to 0 W. The specific resistance of the wiring of Comparative Example 1 was measured.
  • FIG. 20 is a photograph showing the metallographic structure of the wiring surface of Example 3 after immersion in an ammonium persulfate etching solution.
  • FIG. 21 is a photograph showing the metallographic structure of the wiring surface of Example 4 after immersion in an ammonium persulfate etching solution.
  • FIG. 22 is a photograph showing the metallographic structure of the wiring surface of Comparative Example 4 after immersion in an ammonium persulfate etching solution.
  • the wiring of Example 3 before annealing was 128 nmZ, and the wiring of Example 3 after annealing was the same as the wiring before annealing after a holding time of about 2 minutes.
  • the wiring of Example 4 before anneal is 1 2 8 nmZ, the wiring of Example 4 after anneal is the same as that before anneal after the retention time of 1 minute or more.
  • the wiring of Comparative Example 4 was 127 nmZ, the retention time of the wiring of Comparative Example 4 after annealing was less than 1 minute, and the same as the wiring before annealing. It was 127 nmZ minutes.
  • Comparative Examples 2 and 3 in which only the wiring and the copper layer of Comparative Example 4 in which the AC power applied to the substrate was 0 W were formed.
  • the wiring of Example 4 has a large etching rate with the etchant immediately after the start of the etching, and the wiring of Comparative Example 4 has the copper film etched over almost the entire surface (a surface protection rate of 15%). You can see that it is taking great damage.
  • Examples 3 and 4 have a holding time in which etching does not proceed for about 1 minute or more, and the surface protection ratio of the wiring of Example 3 where the AC power applied to the substrate is 200 W is In Example 4 where the AC power applied to the substrate was 100% and the AC power applied to the substrate was 100 W, the wiring surface protection ratio was 50%, and the state of the wiring surface before and after immersion in the etching solution did not change much. It can be seen that the drug solution resistance is superior to that of Comparative Example 4.
  • FIGS. 23 to 24 show the results of a wiring analysis of the wiring structure of the third embodiment before and after the annealing treatment, by a page analysis method.
  • FIG. 23 shows a depth profile of the wiring of the third embodiment before the annealing process
  • FIG. 24 shows a depth profile of the wiring of the first embodiment after the annealing process.
  • the Cr content between the glass substrate and the Cu layer was smaller than before the annealing treatment, and the peaks of Cr and 0 were observed on the surface of the Cu layer. It can be seen that Cr and ⁇ on the surface of the Cu layer are larger than before the annealing treatment. From these facts, it can be understood that Cr was diffused to the surface of the Cu layer by performing the annealing treatment.
  • Example 3 Instead of the titanium target 71, a molybdenum target 71 was used.Also, the AC power applied to the glass substrate was changed in the range of 0 to 200 W, and the molybdenum was set on the glass substrate. The relationship between the film formed on the Cu layer and the AC power applied to the glass substrate was examined when a wiring was produced in the same manner as in Example 1 except that the film was formed. As a result, the film obtained when the AC power applied to the glass substrate was 200 W was 7 nm, the film obtained at 100 W was 6 nm, and the film obtained at 0 W was 2 nm. nm
  • the film formation chamber 60 was set to a mixed atmosphere of and Ar gas, the titanium electrode 71 was mounted on the first electrode 70, and the The second electrode 72 is equipped with a square glass substrate having a side of 6 inches, and a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70. Further, a TiN film having a thickness of 50 nm was formed by performing sputtering by setting the load potential applied from the DC power supply 78 to ⁇ 200 V.
  • the film forming chamber 60 was set to an Ar gas atmosphere, an evening get 71 made of titanium was attached to the first electrode 70, and the above-mentioned square glass having a side of 6 inches was attached to the second electrode 72.
  • a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70, and the load potential applied from the DC power supply 78 is reduced by one.
  • Sputtering was performed at 00 V to form a 20-nm-thick titanium film on a glass substrate.
  • the film formation chamber 60 was set to an Ar gas atmosphere, an evening gate 71 made of copper was attached to the first electrode 70, and a glass substrate was attached to the second electrode 72,
  • the two-frequency excitation sputtering method in which the DC power source 78 is operated to apply DC power to the target 71 and the second AC power source 80 is operated to apply AC power to the glass substrate,
  • a Cu film having a thickness of 140 nm was formed on the titanium film, and a laminated film including a TiN film, a titanium film, and a Cu film was formed.
  • the AC power applied to the glass substrate here was 200 W.
  • the substrate on which the above-mentioned laminated film was formed was annealed at 400 ° C. for 2 hours in a nitrogen gas atmosphere to prepare a test piece 1.
  • a test piece 2 was prepared in the same manner as described above, except that the thickness of the Cu film was set at 150 nm and the temperature during the annealing treatment was set at 500 ° C.
  • the film forming chamber 60 was set to a mixed gas atmosphere of SiH 4 + H 2 , and the dummy electrode 71 a was mounted on the first electrode 70. Then, a glass substrate 36 is mounted on the second electrode 72, and a high frequency of about 200 MHz is supplied from the first AC power supply 75 to the first electrode 70, and the second RF power is supplied from the AC power supply 80 to the second electrode 72 to control the ion energy applied to the glass substrate 36 to form an a-Si layer (i-Si) having a thickness of 10 ° nm. A film was formed.
  • the film forming chamber 60 was set to an Ar gas atmosphere, and an evening gate 71 made of P-doped Si for a-Si: n monolayer formation was mounted on the first electrode 70.
  • a high frequency of about 13.6 MHz is supplied from the AC power supply 75 to the first electrode 70, and the load potential applied from the DC power supply 78 is set to ⁇ 200 V to perform sputtering.
  • nnna S i nnna S i
  • a 50 nm-thick TiN film was formed on the a-Si: n + layer in the same manner as in the above-mentioned test piece 1, and a 150 nm-thick film was further formed on the TiN film.
  • the Cu film was formed in the same manner as in Test Piece 1 above.
  • this substrate was annealed in a nitrogen gas atmosphere at 500 ° (:, 2 hours) to prepare a test piece 3.
  • FIGS. 25 to 27 show the results of examining the structures of the test pieces 1 to 3 by Auger analysis.
  • Fig. 25 shows the depth profile of test piece 1 subjected to annealing at 400 ° C for 2 hours
  • Fig. 26 shows the depth profile of test piece 2 subjected to annealing at 500 ° C for 2 hours.
  • FIG. 27 shows the depth profile of the test piece 3 subjected to annealing at 500 ° C. for 2 hours.
  • the test piece 3 in which the Ti film was not provided between the TiN film and the Cu film showed a peak of Ti on the surface side of the Cu film. It can be seen that Ti is not diffused to the surface of the Cu film even after annealing at 50 ( ⁇ C.
  • the Cu peak and the Si peak there is a peak of N and a peak of T i indicated by 1101, and the peak of N is larger than the peak of T i, but it is determined by Auger analysis that the peak of T i is near the peak of N Since peaks are also detected, the peaks of N indicated by a line include Ti in addition to N, and therefore the content ratio of N and T i is estimated to be approximately 1: 1. Therefore, it can be seen that the TiN film remains between the Cu film and the a—Si: n + layer.
  • the peak of Ti was observed on the surface side of the Cu film, and 40 (the Cu film was treated by annealing with TC). It can be seen that T i is diffused on the surface of Cu. Also, between the peak of Cu and the peak of ⁇ in the glass substrate, the peak of N indicated by the letter T is indicated by the symbol T Although it is larger than the peak of i, it can be seen that the TiN film remains for the same reason as described above, and a peak of ⁇ is observed on the surface side of the Cu film. This is because O reacted with T i to form a titanium oxide film.
  • test piece 3 had a larger Ti peak on the surface side of the Cu film than the test piece 2, and also had a peak between the Cu peak and the black peak in the glass substrate. It is considered that most of the Ti constituting the Ti film was diffused to the surface of the Cu film by performing annealing at 500 ° C. because the peak of the indicated Ti was small. (Experimental example 5)
  • Specimen 4 was prepared in the same manner as in the preparation of Specimen 3 except that the annealing conditions were changed.
  • Specimens 5 to 8 were prepared in the same manner as for Specimen 3 except that a 50 nm thick TiN film and a 20 nm thick Ti film were formed, and the annealing conditions were changed. Produced.
  • Figure 28 shows the results.
  • the horizontal axis represents the anneal temperature (° C.)
  • the vertical axis represents the ratio of the sheet resistance value of the laminated film to the sheet resistance value of the RZR (i n).
  • the sheet resistance at an annealing temperature of 400 ° C is about 1.5 times the sheet resistance of the Cu film, and the sheet resistance is the highest at 500 ° C.
  • the sheet resistance increases with an increase in the annealing temperature because the Cu that forms the Cu film and the element of the underlying metal film interdiffuse with Cu as a result of the rise in temperature, forming a solid solution in Cu. To do so.
  • the sheet resistance almost changed even when the annealing temperature was changed.
  • the film has a resistance as low as that of the Cu film.
  • a- S i: n ⁇ layer and C u film intended C r specimen 6 having a film between is about 1.1 times the sheet resistance of the resistance of the Cu film in the 400 ° C, Also, it can be seen that the sheet resistance hardly changed even when the annealing temperature was changed.
  • the specimen 8 having a TiN film and a Ti film between the a—Si: n + layer and the Cu film has a sheet resistance of (400 ° C). : About 1.3 times that of the 11 film, but it can be seen that when the temperature exceeds 500 ° C, the resistance becomes as low as the Cu film.
  • the metal film TiN film, Ti film, Cr film, Mo film, TiN film and T
  • the diffusion state of the i-film was investigated by Auger analysis. The results are described below.
  • test pieces 5 and 6 it was found that a film consisting of a titanium oxide film and a Kumumu oxide film with a thickness of about 10 nm was formed on the surface of the Cu film. . It was also found that the test piece 8 had a film of titanium oxide having a thickness of about 10 nm formed on the surface of the Cu film.
  • the test pieces 4 to 7 were evaluated for barrier property of the metal film formed between the a—S i: n + layer and the Cu film.
  • the barrier property here was evaluated by measuring the sheet resistance when a voltage was applied to the Cu film. The results are shown in FIG. From the results shown in Fig. 29, a Ti film or a Cr film was provided between the a-Si: n + layer and the Cu film. It can be seen that the test pieces 5 and 6 showed a sharp rise in sheet resistance when the anneal temperature exceeded 400 ° C. In the test piece 7 in which the Mo film was provided between the a—Si: n + layer and the Cu film, the sheet resistance hardly changed up to 500 ° C., and suddenly exceeded 500 ° C. It can be seen that it has risen.
  • the sheet resistance sharply rises because of the increase in the annealing temperature, the metal silicide reaction causes the barrier property of the metal film between the a—Si: n— layer and the Cu film to decrease, and S i: This is because S i in the n + layer diffuses and enters the Cu film.
  • the sheet resistance hardly changes until the annealing temperature reaches 500 ° C. It can be seen that even when the temperature exceeds 500 ° C., the temperature rises more slowly than that of the test piece 7.
  • the TiN film has better heat resistance than Ti, Cr, and Mo, and is effective in preventing the diffusion of elements from the adjacent film.
  • Specimen 9 was produced in the same manner as in Specimen 1 except that it was removed and the annealing conditions were changed.
  • the film formation chamber 60 was set to an Ar gas atmosphere, a dummy electrode 71 a was mounted on the first electrode 70, and a Ti film was formed on the second electrode 70. While the glass substrate is still mounted, high frequency is supplied from the first AC power supply 75 to the first power supply 70 to generate a plasma by floating the load potential, and to the second electrode 72. It is performed by supplying high frequency power and applying AC power of about 200 W to the glass substrate for about 2 minutes.
  • test pieces were prepared in the same manner as the above-described test piece 10 except that the AC power applied to the glass substrate was set to 50 W for 1 minute. To 13 were produced.
  • Fig. 30 shows the structure of test piece 9 before annealing and the structure of test piece 9 when the annealing temperature was changed in the range of 250 ° C to 500 ° C by Auger analysis. The results are shown below.
  • Fig. 31 shows the structure of test piece 10 before annealing and the structure of test piece 10 when the annealing temperature was changed in the range of 300 ° C to 500 ° C by Auger analysis. The result of the examination is shown.
  • the test piece 10 before the annealing treatment showed a peak near the boundary between the Cu film and the Ti film, and a titanium oxide film was formed on the surface of the Ti film. You can see that it has been done.
  • the temperature at which Ti begins to diffuse to the surface of the Cu film is 350 ° C., and as the annealing temperature increases, the amount of Ti diffused to the surface of the Cu film increases. I understand.
  • the test piece 9 before the annealing treatment no peak of ⁇ was observed near the boundary between the Cu film and the Ti film, indicating that the titanium oxide film was removed by the plasma etching treatment.
  • Test pieces 11 to 14 were prepared in substantially the same manner as test piece 3 of Experimental Example 4 except that the thickness was changed in the range of nm and the annealing conditions were further changed.
  • Figure 32 shows the results.
  • the horizontal axis is the anneal temperature (° C.)
  • the vertical axis is RZR (in), which is the ratio of the sheet resistance of the laminated film to the sheet resistance of the Cu film.
  • the test piece 13 in which a 50 nm thick TiN film and a 20 nm thick Ti film were provided between the Si and Cu films It can be seen that the change in sheet resistance is smaller than that in the case of 2.
  • a 50 nm thick It can be seen that the sheet resistance of the test piece 14 provided with a Ti film and a Ti film having a thickness of 10 nm hardly changed even when the annealing temperature was changed.
  • oxidation resistance to moisture and oxygen can be improved, and corrosion resistance to an etching agent, a resist stripping solution, and the like can be improved.
  • a wiring capable of improving adhesion to a base and preventing interdiffusion of elements between adjacent films, a thin film transistor substrate using the same, a method of manufacturing the same, and a liquid crystal display device having such a thin film transistor substrate Can be provided.

Abstract

The invention provides a gate electrode (40) (wiring) characterized by comprising titanium or titanium oxide film (40b) that surrounds a copper layer (40a); a thin-film transistor substrate (31) characterized by comprising the gate electrode (40) (wiring); and a liquid crystal display device characterized in that liquid crystal is interposed between a pair of substrates opposed to each other, one of the substrates being the thin-film transistor substrate (31).

Description

明細書 配線とこれを用いた薄膜卜ランジス夕基板およびその製造方法と液晶表示装置 技術分野  TECHNICAL FIELD The present invention relates to a wiring, a thin film transistor substrate using the same, a method of manufacturing the same, and a liquid crystal display.
本発明は、 低抵抗の銅を電極や配線材料に用いた配線とこれを用いた薄膜トラ ンジス夕 （T F T ) 基板及びその製造方法と液晶表示装置に関する。 背景技術  The present invention relates to a wiring using low-resistance copper as an electrode or wiring material, a thin film transistor (TFT) substrate using the same, a method of manufacturing the same, and a liquid crystal display device. Background art
一般に、 液晶表示装置に備えられる基板としては、 薄膜トランジスタ （T F T ) 基板が知られている。  Generally, a thin film transistor (TFT) substrate is known as a substrate provided in a liquid crystal display device.
図 3 3と図 3 4は、 ゲート配線 Gとソース配線 Sなどの部分を基板 8 6上に備 えた一般的な薄膜トランジスタ基板の一構造例を示すものである。 図 3 3と図 3 4に示す薄膜トランジスタ基板において、 ガラスなどの透明の基板 8 6上に、 ゲ 一卜配線 Gとソース配線 Sとがマトリクス状に配線されている。 また、 ゲート配 線 Gとソース配線 Sとで囲まれた領域が画素部 8 1とされ、 各画素部 8 1には薄 膜トランジスタ 8 3が設けられている。  FIG. 33 and FIG. 34 show an example of the structure of a general thin film transistor substrate provided with portions such as a gate wiring G and a source wiring S on a substrate 86. In the thin film transistor substrate shown in FIGS. 33 and 34, a gate wiring G and a source wiring S are wired in a matrix on a transparent substrate 86 such as glass. Further, a region surrounded by the gate wiring G and the source wiring S is defined as a pixel portion 81, and a thin film transistor 83 is provided in each pixel portion 81.
薄膜トランジスタ 8 3はエッチストツパ型の一般的な構成のものであり、 A 1 又は A 1合金などの導電材料からなるゲート配線 Gとこのゲート配線 Gから引き 出して設けたゲート電極 8 8上に、 ゲート絶縁膜 8 9を設け、 このゲート絶縁膜 8 9上にアモルファスシリコン （a - S i ) からなる半導体能動膜 9 0をゲート 電極 8 8に対向させて設け、 更にこの半導体能動膜 9 0上に A 1又は A 1合金な どの導電材料からなるドレイン電極 9 1とソース電極 9 2とを相互に対向させて 設けて構成されている。 なお、 半導体能動膜 9 0の両側の上部側にはリンなどの ドナ一となる不純物を高濃度にドープしたアモルファスシリコンなどのォーミツ クコンタクト膜 9 0 a、 9 0 aが形成され、 それら上に形成されたドレイン電極 9 1とソース電極 9 2と、 半導体能動膜 9 0とで挟まれた状態でエッチングス卜 ッパー 9 3が形成されている。 また、 ドレイン電極 9 1の上からドレイン電極 9 1の側方側にかけてインジウム酸化錫 （以下、 I T Oと略記する。 ） からなる透 明画素電極 9 5が接続されている。 The thin film transistor 83 has a general structure of an etch stop type. The thin film transistor 83 has a gate wiring G made of a conductive material such as A 1 or an A 1 alloy, and a gate electrode 88 pulled out from the gate wiring G. An insulating film 89 is provided, a semiconductor active film 90 made of amorphous silicon (a-Si) is provided on the gate insulating film 89 so as to face the gate electrode 88, and further on the semiconductor active film 90. The drain electrode 91 and the source electrode 92 made of a conductive material such as A1 or A1 alloy are provided to face each other. On the upper side of both sides of the semiconductor active film 90, there are formed ohmic contact films 90a and 90a such as amorphous silicon doped with a high concentration of a dopant such as phosphorus. An etching stopper 93 is formed in a state sandwiched by the formed drain electrode 91, source electrode 92, and semiconductor active film 90. In addition, a transparent layer of indium tin oxide (hereinafter abbreviated as ITO) extends from above the drain electrode 91 to the side of the drain electrode 91. The bright pixel electrode 95 is connected.
そして、 ゲー卜絶縁膜 8 9と透明画素電極 9 5とドレイン電極 9 1とソース電 極 9 2などの上を覆ってこれらの上にパッシべ一ション膜 9 6が設けられている 。 このパッシベーシヨン膜 9 6上には図示略の配向膜が形成され、 この配向膜の 上方に液晶が設けられてァクティブマトリクス液晶表示装置が構成されていて、 透明画素電極 9 5によって液晶の分子に電界を印加すると液晶分子の配向制御が できるようになつている。  Then, a passivation film 96 is provided so as to cover the gate insulating film 89, the transparent pixel electrode 95, the drain electrode 91, the source electrode 92, and the like. An alignment film (not shown) is formed on the passivation film 96, and a liquid crystal is provided above the alignment film to constitute an active matrix liquid crystal display device. When an electric field is applied, the alignment of liquid crystal molecules can be controlled.
図 3 3と図 3 4に示した薄膜トランジスタ基板を製造する方法としては、 アル ミニゥムまたはアルミニウム合金からなる夕ーゲットを用い、 該夕ーゲッ 卜に直 流電力を印加する通常のスパッ夕法などの薄膜形成手段によりガラス基板 8 6上 に A 1又は A 1合金層を形成後、 フォトリソグラフィ一法によりゲ一ト形成位置 以外の場所の A 1又は A 1合金層を除去してゲート電極 8 8を形成した後、 C V D法などの薄膜形成手段により S i〇2や S i N xからなるゲート絶縁膜 8 9、 半 導体能動膜 9 0、 エッチングストッパー 9 3を形成し、 ついでこれらの上に上述 のスパッ夕法、 フォトリソグラフィ一法によりォーミックコンタクト膜 9 0 a 、 ドレイン電極 9 1及びソース電極 9 2を形成し、 ついで形成したドレイン電極 9 1及びソース電極 9 2をマスクして、 ォーミックコンタクト膜 9 0 aの一部を除 去してォーミックコンタク卜膜 9 0 aを分割した後、 C V D法などによりパッシ ベーシヨン膜 9 6を形成することにより、 薄膜トランジスタ基板が得られる。 ところで、 近年、 液晶表示装置の高速化等に伴い、 ゲート電極、 ゲート配線、 ソース配線、 ドレイン配線などの電極や配線の抵抗による信号伝達の遅延の問題 が顕在化されており、 このような問題を解決するために電極や配線を構成する材 料として A 1または A 1合金より低抵抗の銅の使用が検討されている。 この銅配 線は、 A 1または A 1合金から配線を構成する場合と同様に通常のスパッ夕法に より C u層を形成後、 フォトリソグラフィ一法により配線形成位置以外の場所の C u層を除去することにより形成できる。 As a method of manufacturing the thin film transistor substrate shown in FIGS. 33 and 34, an aluminum or aluminum alloy sunset is used, and a thin film such as a normal sputtering method in which DC power is applied to the sunset is used. After forming the A1 or A1 alloy layer on the glass substrate 86 by the forming means, the gate electrode 88 is removed by removing the A1 or A1 alloy layer at a place other than the gate formation position by a photolithography method. after forming, S I_〇 2 and S i N gate insulating film 8 9 consisting of x, semiconductors active film 9 0, the etching stopper 9 3 is formed by a thin film formation means such as a CVD method, and then above the top of these An ohmic contact film 90a, a drain electrode 91 and a source electrode 92 are formed by a sputtering method or a photolithography method, and the formed drain electrode 91 and source electrode 92 are masked. After splitting the O over Mick contactee Bokumaku 9 0 a to divided portions of the ohmic contact layer 9 0 a, by forming a passive Beshiyon film 9 6 by a CVD method, a thin film transistor substrate is obtained. In recent years, with the speeding up of liquid crystal display devices, the problem of signal transmission delay due to the resistance of electrodes and wiring such as gate electrodes, gate wirings, source wirings, and drain wirings has become apparent. In order to solve this problem, the use of copper having lower resistance than A1 or A1 alloy as a material for forming electrodes and wiring is being studied. This copper wiring is formed by forming a Cu layer by the usual sputtering method as in the case of forming the wiring from A1 or A1 alloy, and then by photolithography to form a Cu layer at a location other than the wiring formation position. Can be formed.
しかしながら図 3 3と図 3 4に示したような構造の薄膜トランジスタ基板が備 えられた液晶表示装置において、 ゲート電極 8 8などの電極やゲート配線 Gなど の配線の材料 （以下、 配線材料と略記する。 ） として銅を用いると、 銅が薬液に 弱いため、 後工程で他の層をエッチングする際に使用される酸化力のある酸系ェ ッチング剤が銅膜にしみ込んで来たときにこの銅膜がェッチングされて損傷を受 けることがあり、 さらに損傷が進行すると下地膜としての基板 8 6から剥離した り、 断線不良が生じることがあるため、 用いるエッチング剤が制限されてしまう という問題があった。 However, in a liquid crystal display device provided with a thin film transistor substrate having a structure as shown in FIGS. 33 and 34, an electrode material such as a gate electrode 88 and a wiring material such as a gate wiring G (hereinafter abbreviated as a wiring material). If copper is used as), copper becomes Due to its weakness, the copper film may be damaged by etching when the oxidizing acid-based etching agent used to etch other layers in the subsequent process infiltrates the copper film. However, if the damage further progresses, it may be peeled off from the substrate 86 as a base film or a disconnection failure may occur, so that there is a problem that an etching agent to be used is limited.
また、 配線材料として銅を用いると、 フォトリソグラフィー工程で使用される レジスト剥離液が銅膜にしみ込んで来たときにこのレジスト剥離液により銅膜が 腐食することがあった。  Further, when copper is used as a wiring material, when a resist stripping solution used in a photolithography process permeates the copper film, the resist stripping solution may corrode the copper film.
また、 銅膜のエッチングメカニズムは、 銅膜表面を酸化してエッチングを行う ものであるが、 エッチング前に空気中の水分や酸素により銅膜の表面に C u Oや C u 〇などの酸化層ができてしまうと、 酸化力のないエッチング剤でもエッチ ングされて損傷を受け、 さらには断線不良が生じるという問題があった。 そこで 、 表面に C u〇や C u 2〇などの酸化層の発生を防止できる C u系配線材料とし て、 C u合金が考えられているが、 C u合金は C uに比べて配線比抵抗が大きく なってしまい、 低抵抗の材料を用いる効果があまり期待できなくなってしまう。 また、 ゲート電極 8 8を銅膜から構成すると、 C uがゲート絶緣膜 8 9に拡散 し、 絶縁耐圧不良が生じるという問題があり、 さらに、 基板 8 6がガラス基板で あると、 ゲート電極 8 8に基板 8 6中の S iがゲート電極 8 8に入り込み、 ゲ一 卜電極 8 8の抵抗が上昇してしまう。 また、 ドレイン電極 9 1やソース電極 9 2 を銅膜から構成すると、 各電極 9 1 , 9 2と半導体能動膜 9 0との間で元素の相 互拡散が生じ、 半導体能動膜の特性が劣化してしまうという問題があつた。 発明の開示 The etching mechanism of the copper film is such that the surface of the copper film is oxidized to perform etching. Before the etching, moisture or oxygen in the air causes the surface of the copper film to have an oxide layer such as CuO or Cu u. If the etching is not completed, there is a problem that even an etching agent having no oxidizing power is etched and damaged, and furthermore, a disconnection failure occurs. Therefore, as the C u based wiring material capable of preventing the occurrence of the oxide layer, such as C U_〇 and C u 2 〇 on the surface, but C u alloys are considered, C u alloy wire ratio than the C u The resistance increases, and the effect of using a low resistance material cannot be expected much. In addition, if the gate electrode 88 is made of a copper film, Cu diffuses into the gate insulating film 89, which causes a problem of poor withstand voltage. Further, if the substrate 86 is a glass substrate, the gate electrode 8 Si in the substrate 86 enters the gate electrode 88 into the gate electrode 8, and the resistance of the gate electrode 88 increases. Also, when the drain electrode 91 and the source electrode 92 are made of a copper film, mutual diffusion of elements occurs between the electrodes 91 and 92 and the semiconductor active film 90, and the characteristics of the semiconductor active film deteriorate. There was a problem of doing it. Disclosure of the invention
本発明は上記事情に鑑みてなされたもので、 低抵抗の銅を配線材料として用い る場合に、 水分や酸素に対する耐酸化性を向上でき、 しかもエッチング剤やレジ スト剥離液などに対する耐腐食性を向上でき、 下地との密着性を向上でき、 さら に隣接膜との間での元素の相互拡散を防止できる配線とこれを用いた薄膜トラン ジス夕基板およびその製造方法と、 そのような薄膜トランジスタ基板を備えた液 晶表示装置を提供することを課題とする。 本発明の配線は、 上記課題を解決するために、 銅層の周囲に、 チタンまたはチ 夕ン酸化物からなる被膜を有することを特徴とする。 ここでの被膜の具体例とし ては、 チタン原子数に対する酸素原子数の比が 1対 0乃至 1対 2である組成の皮 膜などを挙げることができ、 より具体的には、 チタン被膜、 酸化チタン被膜など が挙げられる。 The present invention has been made in view of the above circumstances, and when low-resistance copper is used as a wiring material, it is possible to improve the oxidation resistance to moisture and oxygen, and furthermore, the corrosion resistance to an etching agent, a resist stripping solution, and the like. Wiring, a thin film transistor substrate using the same, a method of manufacturing the same, and a thin-film transistor using the same It is an object to provide a liquid crystal display device provided with a substrate. In order to solve the above-mentioned problems, the wiring of the present invention is characterized by having a coating made of titanium or titanium oxide around a copper layer. Specific examples of the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2, and more specifically, a titanium coating, And a titanium oxide film.
また、 本発明の配線は、 上記課題を解決するために、 銅層の周囲に、 モリブデ ンまたはモリブデン酸化物からなる被膜を有することを特徴とするものであって もよい。 ここでの被膜の具体例としては、 モリブデン原子数に対する酸素原子数 の比が 1対 0乃至 1対 3である組成の被膜などを挙げることができ、 より具体的 には、 モリブデン被膜、 酸化モリブデン被膜などが挙げられる。  Further, in order to solve the above-mentioned problems, the wiring of the present invention may be characterized by having a coating made of molybdenum or molybdenum oxide around a copper layer. Specific examples of the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of molybdenum atoms is 1: 0 to 1: 3. More specifically, a molybdenum coating, molybdenum oxide Coatings and the like.
また、 本発明の配線は、 上記課題を解決するために、 銅層の周囲に、 クロムま たはクロム酸化物からなる被膜を有することを特徴とするものであってもよい。 ここでの被膜の具体例としては、 クロム原子数に対する酸素原子数の比が 1対 0 乃至 1対 2である組成の被膜などを挙げることができ、 より具体的にはクロム被 膜、 酸化クロム被膜などが挙げられる。  Further, in order to solve the above-mentioned problems, the wiring of the present invention may be characterized by having a coating made of chromium or chromium oxide around a copper layer. Specific examples of the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 0 to 1: 2, and more specifically, a chromium film, chromium oxide Coatings and the like.
さらにまた、 本発明の配線は、 上記課題を解決するために、 銅層の周囲に、 夕 ン夕ルまたは夕ン夕ル酸化物からなる被膜を有することを特徴とするものであつ てもよい。 ここでの被膜の具体例としては、 タンタル原子数に対する酸素原子数 の比が 1対 0乃至 1対 2 . 5である組成の被膜などを挙げることができ、 より具 体的には、 タンタル被膜、 酸化タンタル被膜などが挙げられる。  Still further, in order to solve the above-mentioned problem, the wiring according to the present invention may have a structure in which a copper layer is provided around the copper layer, and the coating is made of oxide or oxide. . Specific examples of the coating here include a coating having a composition in which the ratio of the number of oxygen atoms to the number of tantalum atoms is 1: 0 to 1: 2.5, and more specifically, a tantalum coating. And a tantalum oxide film.
上記の銅層の周囲に形成される上記被膜の厚みは、 5乃至 3 O n m程度とする ことが好ましく、 より好ましくは 5乃至 2 0 n mストローム程度である。 上記被 膜の厚みが 5 n m未満であると、 薄すぎて水分や酸素に対する耐酸化性ならびに エッチング剤やレジス卜剥離液などに対する耐腐食性をあまり向上できず、 また 、 隣接膜との間の元素の相互拡散が生じる場合がある。 また、 3 O n mを超えて 厚くしても目的とする効果が飽和する一方で成膜時間が増加し、 また、 配線比抵 抗が上昇してしまう。  The thickness of the film formed around the copper layer is preferably about 5 to 30 nm, more preferably about 5 to 20 nm. If the thickness of the film is less than 5 nm, the film is too thin to improve the oxidation resistance to moisture and oxygen and the corrosion resistance to an etching agent or a resist stripping solution, etc. Interdiffusion of elements may occur. Further, even if the thickness exceeds 3 Onm, the intended effect is saturated, but the film formation time increases, and the wiring specific resistance increases.
また、 本発明の配線で、 銅層の周囲に、 チタンまたはチタン酸化物からなる被 膜を有するものにおいては、 上記被膜は、 チタン膜と、 チタン酸化物からなる膜 とを有してなるものであってもよく、 具体例としては、 チタン膜と、 チタン原子 数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜とを有してなるも のなどが挙げられる。 In the wiring according to the present invention, in the case where a film made of titanium or titanium oxide is provided around the copper layer, the film is made of a titanium film and a film made of titanium oxide. Specific examples include a titanium film and a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2. And others.
また、 本発明の配線で、 銅層の周囲に、 チタンまたはチタン酸化物からなる被 膜を有するものにおいては、 上記被膜は、 上記銅層の周囲に形成されたチタン膜 と該チタン膜の表面に形成されたチタン酸化物からなる膜とを有してなるもので あってもよく、 具体例としては、 上記銅層の周囲に形成されたチタン膜と該チ夕 ン膜の表面に形成されたチタン原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜とを有してなるものなどが挙げられる。  Further, in the wiring according to the present invention, in the case where a film made of titanium or titanium oxide is provided around the copper layer, the film includes a titanium film formed around the copper layer and a surface of the titanium film. A titanium film formed around the copper layer and a titanium film formed on the surface of the titanium film. And a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2.
また、 本発明の配線で、 銅層の周囲に、 チタンまたはチタン酸化物からなる被 膜を有するものにおいては、 上記被膜は、 上記銅層の周囲の一部に形成されたチ 夕ン膜と、 上記銅層の周囲の残部に形成されたチタン酸化物からなる膜とを有し てなるものであってもよく、 具体例としては、 上記銅層の周囲の一部に形成され たチタン膜と、 上記銅層の周囲の残部に形成されたチタン原子数に対する酸素原 子数の比が 1対 1乃至 1対 2である組成の膜とを有してなるものなどが挙げられ る。  Further, in the wiring according to the present invention, in the wiring having a film made of titanium or titanium oxide around the copper layer, the film is formed of a copper film formed on a part of the periphery of the copper layer. And a film made of titanium oxide formed on the rest of the periphery of the copper layer. As a specific example, a titanium film formed on a part of the periphery of the copper layer And a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed in the remainder around the copper layer is 1: 1 to 1: 2.
また、 本発明の配線で、 銅層の周囲に、 クロムまたはクロム酸化物からなる被 膜を有するものにおいては、 上記被膜は、 クロム膜と、 クロム酸化物からなる膜 とを有してなるものであってもよく、 具体例としては、 クロム膜と、 クロム原子 数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜とを有してなるも のなどが挙げられる。  Further, in the wiring according to the present invention, in which the copper film has a film made of chromium or chromium oxide around the copper layer, the film has a chromium film and a film made of chromium oxide. Specific examples thereof include a chromium film and a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 1 to 1: 2.
また、 本発明の配線で、 銅層の周囲に、 クロムまたはクロム酸化物からなる被 膜を有するものにおいては、 上記被膜は、 上記銅層の周囲に形成されたクロム膜 と該クロム膜の表面に形成されたクロム酸化物からなる膜とを有してなるもので あってもよく、 具体例としては、 上記銅層の周囲に形成されたクロム膜と該クロ ム膜の表面に形成されたクロム原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜とを有してなるものなどが挙げられる。  Further, in the wiring according to the present invention, in the case where a film made of chromium or chromium oxide is provided around the copper layer, the film includes a chromium film formed around the copper layer and a surface of the chromium film. A chromium film formed on the surface of the chromium film and a chromium film formed around the copper layer. And a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 1 to 1: 2.
また、 本発明の配線で、 銅層の周囲に、 クロム又はクロム酸化物からなる被膜 を有するものにおいては、 上記被膜は、 上記銅層の周囲の一部に形成されたクロ ム膜と、 上記銅層の周囲の残部に形成されたクロム酸化物からなる膜とを有して なるものであってもよく、 具体例としては、 上記銅層の周囲の一部に形成された クロム膜と、 上記銅層の周囲の残部に形成されたクロム原子数に対する酸素原子 数の比が 1対 1乃至 1対 2である組成の膜とを有してなるものなどが挙げられる 本発明の薄膜トランジスタ基板は、 上記課題を解決するために、 上記のいずれ かの構成の本発明の配線を有することを特徴とする。 Further, in the wiring according to the present invention, in the case where a coating made of chromium or chromium oxide is provided around the copper layer, the coating is formed on a part of the periphery of the copper layer. And a film made of chromium oxide formed on the rest of the periphery of the copper layer. As a specific example, the film may be formed on a part of the periphery of the copper layer. And a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms formed on the periphery of the copper layer is 1: 1 to 1: 2. In order to achieve the above object, a thin film transistor substrate according to the present invention includes the wiring of the present invention having any one of the above structures.
また、 本発明の薄膜トランジスタ基板は、 上記課題を解決するために、 基体上 に T i N膜を介して上記のいずれかの構成の本発明の配線を設けたことを特徴と する。  Further, in order to solve the above problems, the thin film transistor substrate of the present invention is characterized in that the wiring of the present invention having any one of the above structures is provided on a base via a TiN film.
また、 本発明の薄膜トランジスタ基板は、 銅層の周囲に、 チタンまたはチタン 酸化物からなる被膜を有する配線を基体上に T i N膜を介して設けたことを特徴 とするものであってもよい。 チタンまたはチタン酸化物からなる被膜の具体例と しては、 チタン原子数に対する酸素原子数の比が 1対 0乃至 1対 2である組成の 被膜などが挙げられる。  Further, the thin film transistor substrate of the present invention may be characterized in that a wiring having a coating made of titanium or titanium oxide is provided around a copper layer on a base via a TiN film. . Specific examples of the coating made of titanium or titanium oxide include a coating having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2.
また、 本発明の薄膜トランジスタ基板は、 銅層の表面に、 チタンまたはチタン 酸化物からなる被膜を有する配線の被膜が、 基体上に T i N膜を介して設けられ たものであってもよい。 ここでの配線の被膜は、 上記銅層の表面に形成されたチ タン膜と該チ夕ン膜の表面に形成されたチタン酸化物からなる膜とを有するもの .- であってもよい。 ここでのチタン酸化物からなる膜の具体例としては、 チタン原 子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜とを有するもの などが挙げられる。  Further, the thin film transistor substrate of the present invention may have a structure in which a wiring film having a film made of titanium or titanium oxide is provided on a surface of a copper layer via a TiN film on a substrate. The wiring film here may be a film having a titanium film formed on the surface of the copper layer and a film made of titanium oxide formed on the surface of the titanium film. Specific examples of the titanium oxide film include a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2.
上記 T i Nの厚みは、 1 0乃至 5 0 n m程度とすることが好ましい。 上記 T i Nの厚みが 1 0 n m未満であると、 上記配線の銅層と基体の間に、 上記のバリヤ 一層として作用する被膜が形成されていない場合、 あるいは、 上記被膜の厚みが 十分でない場合に、 上記基体や、 S i〇 、 S i O N、 S i〇xなどの隣接膜から 拡散してきた元素が配線内に入り込むのを防 止する効果が不十分である。 また、 5 0 n mを超えて厚くしても目的とする効果が飽和する一方で成膜時間が増加し てしまう。 本発明に係わる配線にあっては、 上述のような構成とすることにより、 レジス ト剥離液やエッチング液などの薬液や水分に強い保護層や隣接膜との間での元素 の相互拡散を防止するバリヤ一層としての被膜が銅層の周囲に形成されたことと なり、 あるいはレジスト剥離液やエッチング液などの薬液や水分に強い保護層と しての被膜が銅層の表面に形成されたこととなる。 The thickness of the TiN is preferably about 10 to 50 nm. If the thickness of the TiN is less than 10 nm, the film acting as the barrier layer is not formed between the copper layer of the wiring and the substrate, or the thickness of the film is not sufficient. when, the base and, S I_〇, S i oN, the effect of prevention of the elements that have diffused from the adjacent layer from entering the wiring, such as S I_〇 x is insufficient. Further, if the thickness exceeds 50 nm, the intended effect is saturated, but the deposition time increases. In the wiring according to the present invention, by adopting the above-described configuration, mutual diffusion of elements between a protective layer resistant to a chemical solution such as a resist stripping solution or an etching solution or moisture and an adjacent film is prevented. This means that a film as a barrier layer to be formed is formed around the copper layer, or a film as a protective layer resistant to chemicals such as a resist stripping solution and an etching solution and moisture is formed on the surface of the copper layer. Becomes
このような配線を有する本発明の薄膜トランジスタ基板によれば、 後工程で他 の層をエッチングする際に使用される酸化力のある酸系エッチング剤が銅配線に までしみ込んで来ても銅層の周囲あるいは表面に保護層として作用する上記被膜 が形成されているので、 配線がエッチング剤により損傷を受けにくく、 配線が下 地から剥離するのを防止できるうえ断線不良の発生を防止でき、 また、 用いるェ ツチング剤の自由度が大きい。  According to the thin film transistor substrate of the present invention having such wirings, even if an oxidizing acid-based etching agent used in etching another layer in a later step penetrates into the copper wirings, the copper layer is not removed. Since the above-mentioned film acting as a protective layer is formed on the periphery or on the surface, the wiring is hardly damaged by the etching agent, the wiring can be prevented from peeling off from the ground, and the occurrence of disconnection failure can be prevented. The degree of freedom of the etching agent used is large.
また、 フォ卜リソグラフィー工程で使用されるレジスト剥離液が配線にまでし み込んで来ても本発明に用いられる配線は銅層の周囲あるいは表面に保護層とし て作用する上記被膜が形成されているので、 レジス卜剥離液による配線の腐食を 防止できる。  Also, even if the resist stripping solution used in the photolithography process penetrates into the wiring, the wiring used in the present invention has the above-mentioned film acting as a protective layer formed around or on the surface of the copper layer. Therefore, it is possible to prevent corrosion of the wiring due to the resist stripping solution.
また、 本発明に係わる配線は、 銅層の周囲あるいは表面に上記被膜が形成され ているので、 エッチング前に水分の存在により配線の表面に酸化層が形成される ことがなくなり、 酸化力のないエッチング剤により損傷を受けにくく、 断線不良 の発生を防止できる。 また、 銅層の周囲にバリヤ一層として作用する上記被膜が 形成されているので、 隣接膜から元素が拡散してきても上記被膜により配線への 原子の拡散が阻害され、 隣接膜からの元素の拡散に起因する配線抵抗の上昇を防 止でき、 また、 銅層の C u原子が隣接膜に拡散するのを上記被膜により阻害でき るので、 銅層からの C u原子の拡散に起因する絶縁耐圧不良を防止できるうえ、 半導体能動膜の特性の劣化を防止できる。  Further, since the wiring according to the present invention has the above-mentioned film formed around or on the copper layer, an oxide layer is not formed on the surface of the wiring due to the presence of moisture before etching, and has no oxidizing power. It is hardly damaged by the etching agent, and the occurrence of disconnection failure can be prevented. In addition, since the above-mentioned film acting as a barrier layer is formed around the copper layer, even if the element diffuses from the adjacent film, the diffusion of atoms into the wiring is inhibited by the above-mentioned film, and the diffusion of the element from the adjacent film is prevented. In addition, the above-mentioned coating can prevent the increase in the wiring resistance due to the diffusion of Cu atoms in the copper layer to the adjacent film, so that the withstand voltage due to the diffusion of Cu atoms from the copper layer can be prevented. Failures can be prevented, and deterioration of the characteristics of the semiconductor active film can be prevented.
また、 銅層の表面にバリヤ一層として作用する上記被膜を形成した配線にあつ ては、 この配線の上側や側方の隣接膜 （上記被膜の上側や側方の隣接膜） から元 素が拡散してきても上記被膜により配線への原子の拡散が阻害され、 隣接膜から の元素の拡散に起因する配線抵抗の上昇を防止でき、 また、 上記被膜により銅層 の C u原子がこの配線の上側や側方の隣接膜に拡散するのを阻害されるので、 銅 層からの C u原子の拡散に起因する絶縁耐圧不良を防止できるうえ、 半導体能動 膜の特性の劣化を防止できる。 In the case of a wiring in which the above-mentioned film acting as a barrier layer is formed on the surface of the copper layer, the element is diffused from an adjacent film above or on the side of the wiring (above or above the above-mentioned film). In this case, the diffusion of atoms into the wiring is hindered by the above-mentioned coating, and an increase in wiring resistance due to the diffusion of elements from the adjacent film can be prevented. Copper because it is prevented from diffusing into the In addition to preventing dielectric breakdown failure caused by diffusion of Cu atoms from the layer, deterioration of the characteristics of the semiconductor active film can be prevented.
また、 銅層の周囲あるいは表面が上記被膜により覆われているので、 この配線 上に C V D法等により酸化珪素からなる絶縁膜やパッシベーシヨン膜を形成する 際に、 上記銅層を構成する C uと絶縁膜等の形成材料の S i H 4ガスとの反応を 防止できるので、 上記反応に起因して銅層の表面に針状突起が生じることがなく 、 該針状突起により絶縁抵抗不良が起こるのを防止できる。 Further, since the periphery or the surface of the copper layer is covered with the above-described film, when forming an insulating film or a passivation film made of silicon oxide on the wiring by a CVD method or the like, Cu and the Cu constituting the copper layer are used. it is possible to prevent the reaction between S i H 4 gas forming material such as an insulating film, without needle projections are generated on the surface of the copper layer due to the reaction, the insulation resistance defect occurs due acicular projections Can be prevented.
また、 本発明に係わる配線は、 I T Oや I Z〇などの透明導電膜からなる画素 電極と直接接触させても、 配線材料としてアルミニウムを用いる場合のように I T Oや I Z O中の酸素が配線を酸化することがなく、 I T〇や I Ζ Οとのコン夕 クト抵抗が低い。  Further, even when the wiring according to the present invention is brought into direct contact with a pixel electrode made of a transparent conductive film such as ITO or IZ 、, oxygen in ITO or IZO oxidizes the wiring as in the case of using aluminum as a wiring material. No contact resistance with IT〇 and IΖΖ.
さらに、 本発明の薄膜トランジスタ基板において、 上記配線と上記基体との間 に T i N膜を設けたものにあっては、 上記配線を構成する銅層の下面と基体の間 に上記のようなバリヤ一層として作用する被膜が設けられていなくても、 あるい は、 上記銅層の下面と基体の間の上記被膜の厚みが薄くても、 上記配線と上記基 体との間に T i N膜が設けられているので、 上記基体や隣接膜から配線に元素が 拡散してきても上記 T i N膜により配線への原子の拡散が阻害され、 上記基体や 隣接膜からの元素の拡散に起因する配線抵抗の上昇の防止効果が優れる。 また、 上記 T i N膜によって、 上記配線の密着性が向上する。  Further, in the thin film transistor substrate of the present invention, wherein a TiN film is provided between the wiring and the base, the barrier as described above is provided between the lower surface of the copper layer constituting the wiring and the base. Even if a coating acting as a single layer is not provided, or the thickness of the coating between the lower surface of the copper layer and the substrate is small, a TiN film is formed between the wiring and the substrate. Is provided, even if an element diffuses into the wiring from the substrate or the adjacent film, the diffusion of atoms into the wiring is inhibited by the TiN film, resulting from the diffusion of the element from the substrate or the adjacent film. The effect of preventing an increase in wiring resistance is excellent. Further, the adhesion of the wiring is improved by the TiN film.
従って、 本発明の薄膜トランジスタ基板によれば、 低抵抗の銅を配線材料とし て用いる特性を損なうことなく、 水分や酸素に対する耐酸化性を向上でき、 しか もエッチング剤やレジスト剥離液などに対する耐性を向上できるので、 下地膜と の密着性を向上でき、 断線不良や腐食を防止でき、 また、 用いるエッチング剤の 自由度が大きいので、 銅配線形成後の工程が制約されにくく、 さらに、 隣接膜と の間での元素の相互拡散を防止できるので、 絶縁耐圧が良好で半導体能動膜の特 性が良好な薄膜トランジスタ基板を提供できる。  Therefore, according to the thin film transistor substrate of the present invention, the oxidation resistance to moisture and oxygen can be improved without impairing the characteristics of using low-resistance copper as a wiring material, and the resistance to an etching agent and a resist stripping solution can be improved. It can improve the adhesion to the underlying film, prevent disconnection defects and corrosion, and have a large degree of freedom in the etchant used, so that the process after copper wiring formation is less restricted, and furthermore, Since the interdiffusion of elements can be prevented, a thin film transistor substrate having a good withstand voltage and a good characteristic of a semiconductor active film can be provided.
本発明の薄膜トランジスタ基板の製造方法は、 上記課題を解決するために、 チ タン、 モリブデン、 クロム、 タンタルのうちから選択されたいずれかの金属膜を 形成した基体の上記金属膜上に、 銅からなるターゲッ 卜を使用して銅膜を成膜し 、 該銅膜と上記金属膜とを所望配線形状にパターニングし、 ついで前記基体をァ ニール処理して前記パターニングした銅膜上にチタン、 モリブデン、 クロム、 夕 ンタルのうちから選択された金属の被膜を形成することを特徴とする。 In order to solve the above-mentioned problems, a method for manufacturing a thin film transistor substrate according to the present invention includes the steps of: forming a metal film selected from titanium, molybdenum, chromium, and tantalum; The target is used to form a copper film. Patterning the copper film and the metal film into a desired wiring shape; and annealing the substrate to form a film of a metal selected from titanium, molybdenum, chromium, and evening on the patterned copper film. Is formed.
上記の構成の本発明の薄膜トランジスタの製造方法において、 上記ァニール条 件は、 4 0 0 ° C乃至 1 2 0 0 °C程度で、 3 0分間乃至 1時間程度である。 ァニ ール温度が 4 0 0 °C未満であると低温すぎて、 配線形成用の銅膜中に金属膜中の 元素を十分引き込むことができない。 1 2 0 0 °Cを越えると、 温度が高くなりす ぎて、 銅膜が融解し抵抗の低い銅配線が形成できない。  In the method for manufacturing a thin film transistor according to the present invention having the above configuration, the annealing condition is about 400 ° C. to 1200 ° C., and is about 30 minutes to 1 hour. If the annealing temperature is lower than 400 ° C., the temperature is too low, and the elements in the metal film cannot be sufficiently drawn into the copper film for forming the wiring. If the temperature exceeds 1200 ° C., the temperature becomes too high, and the copper film melts, and copper wiring with low resistance cannot be formed.
本発明の薄膜トランジスタ基板の製造方法によれば、 上記のいずれかの構成の 本発明の配線を有する薄膜卜ランジス夕基板を製造できる。 それは、 チタン、 モ リブデン、 クロム、 タンタルのうちから選択されたいずれかの金属膜を形成した 基体の金属膜上に、 例えば、 銅からなるターゲッ トを使用した 2周波励起型スパ ッ夕装置を用いて非酸化雰囲気下で銅膜を成膜する成膜工程により、 上記金属膜 中の元素を銅膜中に引き込むことができる。 この後、 該銅膜と上記金属膜とを所 望配線形状にパターニングするパターニング工程を行つて銅層を形成し、 ついで 前記基体をァニール処理すると、 上記銅膜中に引き込まれた金属元素が上記銅層 の表面に拡散するので、 上記銅層の周囲にチタン、 モリブデン、 クロム、 タン夕 ルのうちから選択された金属の被膜を形成することができる。 このように基体上 に形成した金属膜の元素を銅膜形成時に銅膜中に引き込み、 さらにァニール処理 することにより上記金属膜の元素を銅層の表面に拡散させることにより保護層や バリヤ一層として作用する被膜を形成すると、 銅層上にスパッ夕法等により上記 被膜を積層する場合と比べて、 配線の厚みを薄くでき、 しかもこの配線の被膜は 、 厚みが薄くても上述のように水分やレジス卜剥離液に対する耐酸化性やエッチ ング剤などに対する耐酸性を十分向上できる。  According to the method for manufacturing a thin film transistor substrate of the present invention, a thin film transistor substrate having the wiring of the present invention having any one of the above structures can be manufactured. It consists of a two-frequency excitation type sputtering device using a target made of copper, for example, on a metal film of a substrate on which a metal film selected from titanium, molybdenum, chromium, and tantalum is formed. The element in the metal film can be drawn into the copper film by a film forming step of forming a copper film in a non-oxidizing atmosphere by using the method. Thereafter, a patterning step of patterning the copper film and the metal film into a desired wiring shape is performed to form a copper layer. Then, when the base is annealed, the metal element drawn into the copper film becomes Since the metal is diffused to the surface of the copper layer, a film of a metal selected from titanium, molybdenum, chromium, and tungsten can be formed around the copper layer. The elements of the metal film thus formed on the substrate are drawn into the copper film when the copper film is formed, and further subjected to an annealing treatment to diffuse the elements of the metal film to the surface of the copper layer, thereby forming a protective layer and a barrier layer. By forming a film that acts, the thickness of the wiring can be reduced as compared with the case where the above-described film is laminated on the copper layer by a sputtering method or the like. Resistance to acid and resist stripper and acid resistance to etching agents and the like can be sufficiently improved.
また、 本発明の薄膜トランジスタの製造方法は、 上記の課題を解決するために 、 基体上に T i N膜を成膜し、 ついで上記 T i N膜上にチタンまたはチタン酸化 物からなる膜を成膜し、 ついで上記チタンまたはチタン酸化物からなる膜上に銅 からなる夕ーゲッ 卜を使用して銅膜を成膜して積層膜とし、 該積層膜を所望配線 形状にパターニングし、 ついで上記基体をァニール処理して上記パターニングし た銅膜上にチタンまたはチタン酸化物からなる被膜を形成することを特徴とする 方法であってもよい。 ここでのチタンまたはチタン酸化物からなる膜の具体例と しては、 チタン原子数に対する酸素原子数の比が 1対 0乃至 1対 2であるチタン 系膜などを挙げることができる。 また、 チタンまたはチタン酸化物からなる被膜 の具体例としては、 チタン原子数に対する酸素原子数の比が 1対 0乃至 1対 2で あるチタン被膜などを挙げることができる。 Further, in order to solve the above problems, the method for manufacturing a thin film transistor according to the present invention forms a TiN film on a substrate, and then forms a film made of titanium or a titanium oxide on the TiN film. A copper film is formed on the titanium or titanium oxide film by using a copper gate to form a laminated film, and the laminated film is patterned into a desired wiring shape. Is annealed and patterned as described above. The method may be characterized in that a film made of titanium or titanium oxide is formed on the formed copper film. As a specific example of the film made of titanium or titanium oxide, a titanium-based film having a ratio of the number of oxygen atoms to the number of titanium atoms of 1: 0 to 1: 2 can be given. Specific examples of the coating made of titanium or titanium oxide include a titanium coating in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2.
上記の構成の本発明の薄膜トランジスタの製造方法において、 上記ァニ一ル条 件は、 3 0 CT C乃至 1 2 0 0 °C程度で、 3 0分間乃至 1時間程度である。 ァニ ール温度が 3 0 0 °C未満であると低温すぎて、 配線形成用の銅膜中に金属膜中の 元素を十分引き込むことができず、 銅層の表面に良好なチタンまたたチタン酸化 物からなる被膜を形成できない。 1 2 0 0 °Cを越えると、 温度が高くなりすぎて 、 銅膜が融解し抵抗の低レ 銅配線が形成できない。  In the method for manufacturing a thin film transistor according to the present invention having the above-described structure, the annealing condition is about 30 CTC to about 1200 ° C., and is about 30 minutes to about 1 hour. If the annealing temperature is lower than 300 ° C., the temperature is too low, and the elements in the metal film cannot be sufficiently drawn into the copper film for forming the wiring. A film composed of titanium oxide cannot be formed. When the temperature exceeds 1200 ° C., the temperature becomes too high, so that the copper film is melted and copper wiring having low resistance cannot be formed.
かかる構成の薄膜トランジスタ基板の製造方法によれば、 上記のいずれかの構 成の配線が T i N膜を介して設けた薄膜トランジスタ基板を製造できる。 それは 、 チタン系膜を T i N膜を介して形成した基体のチタンまたはチタン酸化物から なる膜上に、 例えば、 銅からなるターゲットを使用した 2周波励起型スパッ夕装 置を用いて非酸化雰囲気下で銅膜を成膜する成膜工程により、 上記チタンまたは チタン酸化物からなる膜中のチタン元素を銅膜中に引き込むことができる。 この 後、 上記チタンまたはチタン酸化物からなる膜と銅膜とからなる積層膜を所望配 線形状にパターニングするパターニング工程を行つて銅層を形成し、 ついで上記 基体をァニール処理すると、 上記銅膜中に引き込まれたチタン元素を上記銅層の 表面に拡散するので、 上記銅層の周囲または表面に保護層やバリヤ一層として作 用するチタンまたはチタン酸化物からなる被膜を形成することができる。 このよ うにして製造される薄膜トランジスタ基板の配線の被膜は、 上記銅層の周囲に形 成される場合と、 上記銅層の表面に形成される場合があるが、 それはチタンまた はチタン酸化物からなる膜の厚みや基体をァニール処理する際のァニール温度等 のァニール条件をコン卜ロールすることにより制御できる。  According to the method for manufacturing a thin film transistor substrate having such a configuration, it is possible to manufacture a thin film transistor substrate in which the wiring having any one of the above structures is provided via a TiN film. For example, non-oxidation is performed by using a dual frequency excitation type sputtering device using a target made of copper, for example, on a titanium or titanium oxide film formed of a titanium-based film via a TiN film. By the film formation step of forming a copper film in an atmosphere, the titanium element in the film made of titanium or titanium oxide can be drawn into the copper film. Thereafter, a copper layer is formed by performing a patterning step of patterning a laminated film made of the film made of titanium or titanium oxide and the copper film into a desired wiring shape, and then annealing the substrate with the copper film. Since the titanium element drawn in is diffused to the surface of the copper layer, a coating made of titanium or titanium oxide acting as a protective layer or a barrier layer can be formed around or on the copper layer. The film of the wiring of the thin film transistor substrate manufactured in this manner may be formed around the copper layer or on the surface of the copper layer, and may be formed of titanium or titanium oxide. It can be controlled by controlling annealing conditions such as the thickness of the film made of and the annealing temperature when the substrate is annealed.
また、 上記の薄膜卜ランジス夕の製造方法においては、 上記 T i N膜上に成膜 するチタンまたはチタン酸化物からなる膜の膜厚を 1 0 n m乃至 2 0 n mとする ことが好ましい。 チタンまたはチタン酸化物からなる膜の膜厚を 2 0 n m以下と することで、 抵抗上昇が少なく、 配線材料として C uを用いる効果が顕著に現れ る。 一方、 チタンまたはチタン酸化物からなる膜の膜厚を 3 0 n mを超えて厚く しても、 配線材料として A 1を用いたときと同じ程度まで抵抗が上昇してしてし まうため、 C uを用いる意義がなくなってしまう。 また、 チタンまたはチタン酸 化物からなる膜の膜厚が 1 O n m未満では、 ァニール処理により C u層の表面に 拡散するチタン元素が少なく、 銅層の周囲または表面に形成されるチタン原子数 に対する酸素原子数の比が 1対 0乃至 1対 2であるチタンまたはチタン酸化物か らなる被膜の厚みが薄く、 保護層ゃバリャ一層としての効果が十分得られない。 また、 上記の薄膜トランジスタの製造方法においては、 上記銅膜の成膜前にチ タンまたはチタン酸化物からなる膜の表面に生成したチタンの酸化層をプラズマ エッチングにより除去することにより、 基体をァニール処理して銅膜中に引き込 まれたチタン元素を上記銅層の表面に拡散させるためのァニール温度を下げるこ とができる。 Further, in the method for producing a thin film transistor described above, the film thickness of the titanium or titanium oxide film formed on the TiN film is 10 nm to 20 nm. Is preferred. By setting the thickness of the film made of titanium or titanium oxide to 20 nm or less, the resistance rise is small and the effect of using Cu as a wiring material is remarkably exhibited. On the other hand, even if the thickness of the film made of titanium or titanium oxide exceeds 30 nm, the resistance increases to about the same level as when A1 was used as the wiring material. There is no point in using u. When the thickness of the film made of titanium or titanium oxide is less than 1 O nm, a small amount of titanium element diffuses into the surface of the Cu layer by the annealing treatment, and the number of titanium atoms formed around or around the copper layer is reduced. The thickness of the coating made of titanium or titanium oxide having a ratio of the number of oxygen atoms of 1: 0 to 1: 2 is small, and the effect of the protective layer and the barrier layer cannot be sufficiently obtained. Further, in the method of manufacturing a thin film transistor, the substrate is annealed by removing the oxide layer of titanium formed on the surface of the film made of titanium or titanium oxide by plasma etching before forming the copper film. Thus, the annealing temperature for diffusing the titanium element drawn into the copper film to the surface of the copper layer can be reduced.
また、 上記のいずれかの構成の本発明の薄膜トランジスタの製造方法によれば 、 上記金属膜が形成された基体上あるいは上記チタンまたはチタン酸化物からな る膜が T i N膜を介して形成された基体上に 2周波励起スパッ夕法により銅膜を 成膜する成膜工程と、 該銅膜のパ夕一ニング工程と、 上記基体のァニール工程に より、 本発明に係わる配線を基体上に容易に形成できるので製造工程が複雑にな ることがない。  Further, according to the method for manufacturing a thin film transistor of the present invention having any one of the above structures, the film formed of the titanium or the titanium oxide is formed on the substrate on which the metal film is formed or via the TiN film. The wiring according to the present invention on the substrate by a film forming step of forming a copper film on the substrate by the two-frequency excitation sputtering method, a step of polishing the copper film, and an annealing step of the substrate. Since it can be easily formed, the manufacturing process is not complicated.
さらに、 上記のいずれかの構成の本発明の薄膜トランジスタ基板の製造方法は 、 低温工程で基体上に本発明の配線を形成できるので、 6 0 0 ° C以上の加熱に 耐えられないガラス基板などを基体として用いる場合にも適用できる。  Further, the method for manufacturing a thin film transistor substrate of the present invention having any one of the above structures can form the wiring of the present invention on a substrate in a low-temperature step. It can also be applied when used as a substrate.
また、 上記のいずれかの構成の本発明の薄膜卜ランジス夕の製造方法において は、 上記被膜に酸素を含有させてもよい。  Further, in the method for producing a thin film transistor of the present invention having any one of the above constitutions, the coating may contain oxygen.
上記ァニール時の雰囲気に酸素を含まないで行うと酸素原子の含有割合が 0原 子％の被膜が得られ、 また、 上記ァニール時の雰囲気の酸素分圧を順次増やすこ とにより、 被膜中の酸素原子の含有割合を順次増加できる。  By performing the above-described annealing without containing oxygen, a film having a content of oxygen atoms of 0 atomic% can be obtained. In addition, by sequentially increasing the oxygen partial pressure of the atmosphere during the annealing, the film in the film can be obtained. The content ratio of oxygen atoms can be sequentially increased.
本発明に係わる液晶表示装置は、 上記課題を解決するために、 対向配置された 一対の基板の間に液晶が挾持され、 前記一対の基板の一方が上記のいずれかの構 成の本発明の薄膜トランジス夕基板であることを特徴とする。 In order to solve the above problems, the liquid crystal display device according to the present invention is arranged to face each other. Liquid crystal is sandwiched between a pair of substrates, and one of the pair of substrates is the thin film transistor substrate of the present invention having any one of the above structures.
本発明の液晶表示装置によれば、 低抵抗配線として銅配線を用いた本発明の薄 膜トランジスタ基板が備えられているので、 配線抵抗に起因する信号電圧降下や 配線遅延が生じにくく、 配線が長くなる大面積の表示や配線が細くなる高精細な 表示に最適な表示装置等を容易に実現できるという利点がある。 また、 配線の下 地からの剥離がなく、 断線不良や腐食の発生がなく、 しかも配線と隣接膜との間 での元素の相互拡散を防止できる本発明の薄膜トランジス夕基板が備えられてい るので、 特性の良好な液晶表示装置を提供できる。 図面の簡単な説明  According to the liquid crystal display device of the present invention, since the thin film transistor substrate of the present invention using the copper wiring as the low resistance wiring is provided, a signal voltage drop and a wiring delay due to the wiring resistance hardly occur, and the wiring is reduced. There is an advantage that it is possible to easily realize a display device or the like that is optimal for a display with a large area that is long and a high-definition display with thin wiring. Further, the thin film transistor substrate of the present invention is provided, which does not peel off the wiring from the ground, does not cause disconnection failure or corrosion, and can prevent mutual diffusion of elements between the wiring and an adjacent film. Therefore, a liquid crystal display device having good characteristics can be provided. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明に係わる第 1実施形態の液晶表示装置と薄膜トランジス夕基板 の断面を示す図である。  FIG. 1 is a diagram showing a cross section of a liquid crystal display device and a thin film transistor substrate according to a first embodiment of the present invention.
図 2は、 図 1の薄膜卜ランジス夕基板に備えられるゲー卜電極のその他の例を 示す拡大断面図である。  FIG. 2 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
図 3は、 図 1の薄膜トランジス夕基板に備えられるゲート電極のその他の例 を示す拡大断面図である。  FIG. 3 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
図 4は、 本発明に係わる実施形態の薄膜卜ランジス夕基板の製造方法に好適に 用いられる薄膜の製造装置の成膜室を示す構成図である。  FIG. 4 is a configuration diagram illustrating a film forming chamber of a thin film manufacturing apparatus suitably used in the method for manufacturing a thin film transistor substrate according to the embodiment of the present invention.
図 5は、 本発明に係わる実施形態の薄膜卜ランジス夕基板の製造方法に好適に 用いられる薄膜の製造装置の全体構成を示す平面図である。  FIG. 5 is a plan view showing the overall configuration of a thin-film manufacturing apparatus suitably used in the method for manufacturing a thin-film transistor substrate according to the embodiment of the present invention.
図 6は、 図 5に示す薄膜の製造装置の一部を拡大した側面図である。  FIG. 6 is an enlarged side view of a part of the thin film manufacturing apparatus shown in FIG.
図 7 Aは、 本発明に係わる第 1実施形態の薄膜卜ランジス夕基板の製造方法の 一工程を示す図である。  FIG. 7A is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
図 7 Bは、 本発明に係わる第 1実施形態の薄膜卜ランジス夕基板の製造方法の 一工程を示す図である。  FIG. 7B is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
図 7 Cは、 本発明に係わる第 1実施形態の薄膜トランジスタ基板の製造方法の 一工程を示す図である。  FIG. 7C is a view illustrating one step of a method for manufacturing a thin film transistor substrate of the first embodiment according to the present invention.
図 7 Dは、 本発明に係わる第 1実施形態の薄膜卜ランジス夕基板の製造方法の 一工程を示す図である。 FIG. 7D shows a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention. It is a figure showing one process.
図 8 Aは、 本発明に係わる第 1実施形態の薄膜トランジス夕基板の製造方法の 一工程を示す図である。  FIG. 8A is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
図 8 Bは、 本発明に係わる第 1実施形態の薄膜トランジスタ基板の製造方法の 一工程を示す図である。  FIG. 8B is a view showing one step of the method for manufacturing the thin film transistor substrate of the first embodiment according to the present invention.
図 8 Cは、 本発明に係わる第 1実施形態の薄膜トランジス夕基板の製造方法の 一工程を示す図である。  FIG. 8C is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the first embodiment of the present invention.
図 9は、 本発明に係わる第 2実施形態の液晶表示装置と薄膜トランジスタ基板 の断面を示す図である  FIG. 9 is a diagram showing a cross section of a liquid crystal display device and a thin film transistor substrate according to a second embodiment of the present invention.
図 1 O Aは、 本発明に係わる第 2実施形態の薄膜トランジスタ基板の製造方法 の一工程を示す図である。  FIG. 1OA is a view showing one step of the method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
図 1 0 Bは、 本発明に係わる第 2実施形態の薄膜トランジスタ基板の製造方法 の一工程を示す図である。  FIG. 10B is a view showing one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
図 1 0 Cは、 本発明に係わる第 2実施形態の薄膜トランジス夕基板の製造方法 の一工程を示す図である。  FIG. 10C is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the second embodiment of the present invention.
図 1 0 Dは、 本発明に係わる第 2実施形態の薄膜トランジスタ基板の製造方法 の一工程を示す図である。  FIG. 10D is a view illustrating one step of a method for manufacturing a thin-film transistor substrate according to the second embodiment of the present invention.
図 1 1 Aは、 本発明に係わる第 2実施形態の薄膜トランジスタ基板の製造方法 の一工程を示す図である。  FIG. 11A is a view illustrating one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
図 1 1 Bは、 本発明に係わる第 2実施形態の薄膜トランジスタ基板の製造方法 の一工程を示す図である。  FIG. 11B is a view illustrating one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
図 1 1 Cは、 本発明に係わる第 2実施形態の薄膜トランジスタ基板の製造方法 の一工程を示す図である。  FIG. 11C is a view illustrating one step of a method for manufacturing a thin film transistor substrate according to the second embodiment of the present invention.
図 1 2は、 図 9の薄膜トランジスタ基板に備えられるゲート電極のその他の例 を示す拡大断面図である。  FIG. 12 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
図 1 3は、 図 9の薄膜卜ランジス夕基板に備えられるゲート電極のその他の例 を示す拡大断面図である。  FIG. 13 is an enlarged sectional view showing another example of the gate electrode provided on the thin film transistor substrate of FIG.
図 1 4は、 本発明の係わる第 3実施形態の薄膜トランジスタ基板の断面を示す 図である。 図 1 5は、 エッチング液浸漬後の実施例 1の配線の表面の金属組織を示す写真 である。 FIG. 14 is a diagram showing a cross section of a thin film transistor substrate according to a third embodiment of the present invention. FIG. 15 is a photograph showing the metallographic structure of the surface of the wiring of Example 1 after immersion in the etching solution.
図 1 6は、 エッチング液浸漬後の実施例 2の配線の表面の金属組織を示す写真 である。  FIG. 16 is a photograph showing the metal structure of the surface of the wiring of Example 2 after immersion in the etching solution.
図 1 7は、 エッチング液浸漬後の比較例 1の配線の表面の金属組織を示す写真 である。  FIG. 17 is a photograph showing the metal structure of the surface of the wiring of Comparative Example 1 after immersion in the etching solution.
図 1 8は、 実施例 1の配線のァニール処理前の配線構造をォージェ分析法によ り調べた結果を示す図である。  FIG. 18 is a diagram illustrating a result of examining a wiring structure of the wiring according to the first embodiment before the annealing process by the Auger analysis method.
図 1 9は、 実施例 1の配線のァニール処理後の配線構造をォージェ分析法によ り調べた結果を示す図である。  FIG. 19 is a diagram showing a result of examining a wiring structure after annealing treatment of the wiring according to Example 1 by Auger analysis.
図 2 0は、 エツチング液浸漬後の実施例 3の配線の表面の金属組織を示す写真 である。  FIG. 20 is a photograph showing the metallographic structure of the surface of the wiring of Example 3 after immersion in the etching liquid.
図 2 1は、 エッチング液浸漬後の実施例 4の配線の表面の金属組織を示す写真 である。  FIG. 21 is a photograph showing the metal structure of the surface of the wiring of Example 4 after immersion in the etching solution.
図 2 2は、 エッチング液浸漬後の比較例 4の配線の表面の金属組織を示す写真 である。  FIG. 22 is a photograph showing the metal structure of the surface of the wiring of Comparative Example 4 after immersion in the etching solution.
図 2 3は、 実施例 3の配線のァニール処理前の配線構造をォージェ分析法によ り調べた結果を示す図である。  FIG. 23 is a diagram showing a result of examining a wiring structure of the wiring according to the third embodiment before the annealing treatment by an Auger analysis method.
図 2 4は、 実施例 3の配線のァニール処理後の配線構造をォージェ分析法によ り調べた結果を示す図である。  FIG. 24 is a diagram illustrating a result of examining a wiring structure after annealing treatment of the wiring according to the third embodiment by Auger analysis.
図 2 5は、 試験片 1の構造をォージェ分析法により調べた結果を示す図である 図 2 6は、 試験片 2の構造をォージェ分析法により調べた結果を示す図である 図 2 7は、 試験片 3の構造をォージェ分析法により調べた結果を示す図である 図 2 8は、 試験片 4乃至試験片 8の積層膜のシー卜抵抗を調べた結果を示す図 である。  FIG. 25 is a diagram showing the results of the structure of the test piece 1 examined by the Auger analysis method. FIG. 26 is a diagram showing the results of the structure of the test piece 2 examined by the Auger analysis method. FIG. 28 shows the result of examining the structure of the test piece 3 by Auger analysis. FIG. 28 shows the result of examining the sheet resistance of the laminated films of the test pieces 4 to 8.
図 2 9は、 試験片 4乃至 7の a - S i ： n +層と C u膜間の金属膜のバリ ャ一 性を調べた結果を示す図である。 Figure 29 shows the barrier of the metal film between the a-Si: n + layer and the Cu film of test pieces 4 to 7. It is a figure showing the result of having examined sex.
図 3 0は、 ァニール処理前の試験片 9の構造と、 ァニール温度を 2 5 (T Cか ら 5 0 0 ° Cの範囲で変更したときの試験片 9の構造をォージェ分析法により調 ベた結果を示す。  Figure 30 shows the structure of test piece 9 before annealing and the structure of test piece 9 when the annealing temperature was changed from 25 (TC to 500 ° C) by Auger analysis. The results are shown.
図 3 1は、 ァニール処理前の試験片 1 0の構造と、 ァニール温度を 3 0 0 ° C から 5 0 0： Cの範囲で変更したときの試験片 1 0の構造をォ一ジェ分析法によ り調べた結果を示す図である。  Figure 31 shows the structure of the test piece 10 before annealing and the structure of the test piece 10 when the annealing temperature was changed from 300 ° C to 500: C by the Auger analysis method. FIG. 9 is a diagram showing the result of an examination by the method shown in FIG.
図 3 2は、 試験片 1 1乃至試験片 1 4の積層膜のシート抵抗を調べた結果を示 す図である。  FIG. 32 is a diagram showing the results of examining the sheet resistance of the laminated films of the test pieces 11 to 14.
図 3 3は、 従来の液晶表示装置に備えられた薄膜トランジスタ基板の一例の画 素部を示す平面略図である。  FIG. 33 is a schematic plan view showing a pixel portion of an example of a thin film transistor substrate provided in a conventional liquid crystal display device.
図 3 4は、 図 3 3の薄膜トランジスタ基板を示す断面図である。 発明を実施するための最良の形態  FIG. 34 is a cross-sectional view showing the thin film transistor substrate of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
以下に本発明の各実施形態を詳細に説明するが、 本発明はこれらの実施形態に 限定されるものではない。  Hereinafter, each embodiment of the present invention will be described in detail, but the present invention is not limited to these embodiments.
(第 1実施形態）  (First Embodiment)
図 1は本発明の液晶表示装置の第 1実施形態の要部を示すもので、 この第 1実 施形態の液晶表示装置 3 0は、 本発明の薄膜トランジス夕基板の実施形態のボト ムゲート型の薄膜卜ランジス夕基板 3 1と、 この薄膜トランジスタ基板 3 1に平 行に隔離して設けられた透明の対向基板 3 2と、 上記薄膜トランジスタ基板 3 1 と対向基板 3 2との間に封入された液晶層 3 3を具備して構成されている。 上記薄膜トランジスタ基板 3 1には、 図 3 3に示した従来の構造と同様に縦列 の多数のソース配線と横列の多数のゲート配線が、 対向基板 3 2の上面側から平 面視した場合にマ卜リクス状になるように配列形成され、 ソース配線とゲー卜配 線とで囲まれた多数の領域のそれぞれが画素部とされ、 各画素部に対応する領域 にそれぞれ I T O (インジウムスズ酸化物） 等の透明導電材料からなる画素電極 3 5が形成されるとともに、 各画素電極 3 5の近傍にボトムゲー卜型の薄膜トラ ンジス夕が設けられている。 図 1はソース配線とゲート配線とで囲まれた 1つの画素部に対応する領域に設 けられた薄膜卜ランジス夕の部分とその周囲部分を拡大して示すもので、 薄膜卜 ランジス夕基板 3 1には画素部が多数整列形成されて液晶表示装置 3 0としての 表示画面が構成されている。 FIG. 1 shows a main part of a first embodiment of the liquid crystal display device of the present invention. The liquid crystal display device 30 of the first embodiment is a bottom gate type of the thin film transistor substrate of the present invention. Thin film transistor substrate 31; a transparent opposing substrate 32 provided in parallel with and separated from the thin film transistor substrate 31; and a thin film transistor enclosed between the thin film transistor substrate 31 and the opposing substrate 32. A liquid crystal layer 33 is provided. Similar to the conventional structure shown in FIG. 33, the thin film transistor substrate 31 has a large number of source wirings in a column and a large number of gate wirings in a horizontal row when viewed from the top side of the counter substrate 32 when viewed in plan. A large number of regions arranged in a matrix form and surrounded by a source line and a gate line are each a pixel portion, and a region corresponding to each pixel portion is formed of ITO (indium tin oxide). A pixel electrode 35 made of a transparent conductive material such as that described above is formed, and a bottom gate type thin film transistor is provided near each pixel electrode 35. Figure 1 shows an enlarged view of the thin-film transistor area and its surrounding area provided in the area corresponding to one pixel section surrounded by the source wiring and the gate wiring. In 1, a display screen as the liquid crystal display device 30 is formed by arranging a large number of pixel portions in alignment.
この形態の薄膜トランジスタ基板 3 1にあっては、 各画素部において少なくと も表面が絶縁性である基板 （基体） 3 6上にゲート電極 4 0が設けられ、 このゲ 一卜電極 4 0と基板 3 6を覆ってゲー卜絶縁膜 4 1が設けられ、 ゲート電極 4 0 上のゲート絶縁膜 4 1上にゲート電極 （配線） 4 0よりも小さな半導体能動膜 4 2が積層され、 この半導体能動膜 4 2の両端部上に n t層などからなるォーミッ クコンタクト膜 4 3、 4 4力 半導体能動膜 4 2の端部と位置を合わせ、 半導体 能動膜 4 2の中央部側に間隙をあけて相互に隔離して積層されている。 ここでの 基板 3 6としては、 ガラス基板や、 表面に S i N x膜 3 6 aが形成された基板を 用いることもできる。  In the thin film transistor substrate 31 of this embodiment, a gate electrode 40 is provided on a substrate (substrate) 36 having at least an insulating surface in each pixel portion, and the gate electrode 40 and the substrate A gate insulating film 41 is provided to cover 36, and a semiconductor active film 42 smaller than the gate electrode (wiring) 40 is laminated on the gate insulating film 41 on the gate electrode 40. Ohmic contact films 43, 44 consisting of nt layers, etc. on both ends of film 42.Align with the ends of semiconductor active film 42, leaving a gap at the center of semiconductor active film 42. The layers are separated from each other. Here, as the substrate 36, a glass substrate or a substrate on the surface of which a SiN x film 36a is formed can be used.
ここでゲー卜電極 4 0は、 銅層 4 0 aの周囲に被膜 4 0 bを有してなるもので ある。 被膜 4 0 bは、 チタンまたはチタン酸化物からなる被膜、 モリブデンまた はモリブデン酸化物、 クロムまたはクロム酸化物からなる被膜、 タンタルまたは タン夕ル酸化物からなる被膜のうちいずれかの被膜である。 上記チタンまたはチ 夕ン酸化物からなる被膜の具体例としては、 チタン原子数に対する酸素原子数の 比が 1対 0乃至 1対 2である組成の被膜が挙げられる。 また、 上記モリブデンま たはモリブデン酸化物からなる被膜の具体例としては、 モリブデン原子数に対す る酸素原子数の比が 1対 0乃至 1対 3である組成の被膜が挙げられる。 また、 上 記クロムまたはクロム酸化物からなる被膜の具体例としては、 クロム原子数に対 する酸素原子数の比が 1対 0乃至 1対 1 . 5である組成の被膜が挙げられる。 ま た、 上記タンタルまたはタンタル酸化物からなる被膜の具体例としては、 タンタ ル原子数に対する酸素原子数の比が 1対 0乃至 1対 2 . 5である組成の被膜のう ちのいずれかの被膜が挙げられる。  Here, the gate electrode 40 has a coating 40b around a copper layer 40a. The coating 40b is any one of a coating made of titanium or titanium oxide, a coating made of molybdenum or molybdenum oxide, chromium or chromium oxide, and a coating made of tantalum or tan oxide. As a specific example of the film made of titanium or titanium oxide, a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2 is exemplified. Further, as a specific example of the film made of molybdenum or molybdenum oxide, a film having a composition in which the ratio of the number of oxygen atoms to the number of molybdenum atoms is 1: 0 to 1: 3 can be given. Further, as a specific example of the coating made of chromium or chromium oxide, a coating having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 0 to 1: 1.5 is mentioned. Further, as a specific example of the above-mentioned film made of tantalum or tantalum oxide, any one of films having a composition in which the ratio of the number of oxygen atoms to the number of tantalum atoms is 1: 0 to 1: 2.5. Is mentioned.
上記被膜 4 O bは、 チタン膜と、 チタン酸化物からなる膜とを有してなるもの であってもよく、 具体例としては、 チタン膜と、 チタン原子数に対する酸素原子 数の比が 1対 1乃至 1対 2である組成の膜とを有してなるものであってもよく、 より具体的には図 2に示すように銅層 4 0 aの周囲に形成されたチタン膜 4 0 f と該チタン膜 4 0 f の表面に形成されたチタン原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜などのチタン酸化物からなる膜 4 0 gとを有し てなるものや、 図 3に示すように銅層 4 0 aの周囲の一部に形成されたチタン膜 4 0 hと、 銅層 4 0 aの周囲の残部に形成されたチタン原子数に対する酸素原子 数の比が 1対 1乃至 1対 2である組成の膜などのチタン酸化物からなる膜 4 0 i また、 上記被膜 4 0は、 クロム膜と、 クロム酸化物からなる膜とを有してなる ものであってもよく、 具体例としては、 クロム膜と、 クロム原子数に対する酸素 原子数の比が 1対 1乃至 1対 2である組成の膜とを有してなるものであってもよ く、 より具体的には、 銅層 4 0 aの周囲に形成されたクロム膜と、 該クロム膜の 表面に形成されたクロム原子数に対する酸素原子数の比が 1対 1乃至 1対 2であ る組成の膜などクロム酸化物からなる膜とを有してなるものや、 銅層 4 0 aの周 囲の一部に形成されたクロム膜と、 銅層 4 0 aの周固の残部に形成されたクロム 原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜などのクロム 酸化物からなる膜とを有してなるものであってもよい。 The coating 4 Ob may include a titanium film and a film made of titanium oxide. As a specific example, the ratio of the number of oxygen atoms to the number of titanium atoms is 1 And a film having a composition of 1 to 1 to 2, More specifically, as shown in FIG. 2, the titanium film 40 f formed around the copper layer 40 a and the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the titanium film 40 f are A film having a composition of titanium oxide, such as a film having a composition of 1: 1 or 1: 2, or a portion formed around a copper layer 40a as shown in FIG. And a titanium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed around the copper layer 40a is 1: 1 to 1: 2. Film 40 i Further, the film 40 may be a film having a chromium film and a film made of chromium oxide. Specific examples include a chromium film, and oxygen with respect to the number of chromium atoms. And a film having a composition in which the ratio of the number of atoms is 1: 1 to 1: 2, and more specifically, around the copper layer 40a. A chromium film formed, and a film made of chromium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms formed on the surface of the chromium film is 1: 1 to 1: 2. The ratio of the number of oxygen atoms to the number of chromium atoms formed on a part of the periphery of the copper layer 40a and the chromium film formed on the rest of the periphery of the copper layer 40a is 1: 1. And a film made of chromium oxide such as a film having a composition of 1 to 1: 2.
次に、 図 1の左側 （図 1に示す画素電極 3 5から離れた側） のォーミックコン タクト膜 4 3の上面と左側面とその下の半導体能動膜 4 2の左側面とそれらに連 続するゲート絶縁膜 4 1の上面の一部分を覆って、 即ち、 半導体能動膜 4 2とォ 一ミックコンタクト膜 4 3の重なり部分 （重畳部分） を覆ってソース電極 4 6が 形成されている。 ここでのソース電極 4 6は、 銅層 4 6 aの周囲に被膜 4 6 bを 有してなるものである。 被膜 4 6 bは、 上記ゲート電極 4 0の被膜 4 0 bと同様 の被膜からなるものである。 また、 この被膜 4 6 bは、 ゲート電極 4 0の被膜 4 O bと同様に、 チタン膜と、 チタン原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成の膜などのチタン酸化物からなる膜とを有してなるものであつ てもよい。  Next, the upper surface and left side surface of the ohmic contact film 43 on the left side of FIG. 1 (the side away from the pixel electrode 35 shown in FIG. 1) and the left side surface of the semiconductor active film 42 therebelow are connected to them. A source electrode 46 is formed so as to cover a part of the upper surface of the gate insulating film 41, that is, to cover an overlapping portion (overlapping portion) of the semiconductor active film 42 and the ohmic contact film 43. The source electrode 46 here has a coating 46b around the copper layer 46a. The coating 46 b is made of the same coating as the coating 40 b of the gate electrode 40. Like the coating 4 Ob of the gate electrode 40, the coating 46 b is made of a titanium film, a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2, or the like. And a film made of titanium oxide.
また、 図 1の右側 （図 1に示す画素電極 3 5に近い側） のォ一ミックコンタク ト膜 4 4の上面と右側面とその下の半導体能動膜 4 2の右側面とそれらに連続す るゲート絶縁膜 4 1の上面の一部分を覆って、 即ち、 半導体能動膜 4 2とォーミ ックコンタクト膜 4 3の重畳部分を覆ってドレイン電極 4 8が形成されている。 ここでのドレイン電極 4 8は、 銅層 4 8 aの周囲に被膜 4 8 bを有してなるもの である。 被膜 4 8 bは、 上記ゲート電極 4 0の被膜 4 0 bと同様の被膜からなる ものである。 また、 この被膜 4 8 bは、 ゲート電極 4 0の被膜 4 0 bと同様に、 チタン膜と、 チタン原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組 成の膜なとのチタン酸化物からなる膜とを有してなるものであってもよい。 また、 これらの各膜の上にはこれらを覆ってパッシベーション膜 4 9が設けら れ、 ドレイン電極 4 8の右側端部上のパッシベーション膜 4 9上には画素電極 3 5が形成されていて、 この画素電極 3 5はパッシベーション膜 4 9に形成された コンタク トホール （導通孔） 5 0に設けた接続導体部 5 1を介してドレイン電極In addition, the upper surface and the right side surface of the contact film 44 on the right side of FIG. 1 (the side closer to the pixel electrode 35 shown in FIG. 1) and the right side surface of the semiconductor active film 42 therebelow are connected to them. Covering a part of the upper surface of the gate insulating film 41, namely, the semiconductor active film 42 and the ohmic contact. A drain electrode 48 is formed so as to cover the overlapping portion of the contact layer 43. The drain electrode 48 here has a coating 48b around a copper layer 48a. The coating 48 b is made of the same coating as the coating 40 b of the gate electrode 40. The coating 48 b is, like the coating 40 b of the gate electrode 40, a titanium film and a composition film in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 1 to 1: 2. And a film made of titanium oxide. A passivation film 49 is provided on each of these films to cover them, and a pixel electrode 35 is formed on the passivation film 49 on the right end of the drain electrode 48. The pixel electrode 35 is connected to a drain electrode via a connection conductor 51 provided in a contact hole (conduction hole) 50 formed in the passivation film 49.
4 8に接続されている。 4 Connected to 8.
一方、 薄膜トランジスタ基板 3 1に対して設けられている対向基板 3 2の液晶 側には、 対向基板 3 2側から順にカラーフィルタ 5 2と共通電極膜 5 3とが積層 されている。 上記カラーフィル夕 5 2は、 表示に寄与しない薄膜トランジスタ部 分ゃゲート配線部分およびソース配線部分を覆い隠すためのブラックマトリクス On the other hand, on the liquid crystal side of the opposing substrate 32 provided for the thin film transistor substrate 31, a color filter 52 and a common electrode film 53 are laminated in order from the opposing substrate 32 side. The color filter 52 is composed of a black matrix for covering the thin film transistor part that does not contribute to the display and the gate wiring and source wiring.
5 4と、 画素電極 3 5を設けた画素領域で表示に寄与する部分を通過する光を透 過させ、 更に、 カラー表示をするためのカラー画素部 5 5を主体として構成され ている。 これらのカラー画素部 5 5は、 液晶表示装置がカラー表示の構造の場合 に必要とされ、 画素部毎に設けられているが、 隣接する画素部において色違いと なるように、 例えば、 R (赤） 、 G (緑） 、 B (青） の 3元色のものが色の偏り がないように規則的にあるいはランダムに配置される。 54 and a pixel region where the pixel electrode 35 is provided. The pixel region 35 is made up mainly of a color pixel portion 55 for transmitting light passing through a portion contributing to display and for performing color display. These color pixel portions 55 are required when the liquid crystal display device has a color display structure, and are provided for each pixel portion. For example, R (for example, R ( The three primary colors of red), G (green) and B (blue) are arranged regularly or randomly so that there is no color bias.
なお、 図 1に示す断面構造では薄膜トランジスタ基板 3 1の液晶側と対向基板 In the cross-sectional structure shown in FIG. 1, the liquid crystal side of the thin film transistor substrate 31 and the opposite substrate
3 2の液晶側に設けられる配向膜は省略してあるとともに、 薄膜トランジスタ基 板 3 1の外側と対向基板 3 2の外側に設けられる偏光板を省略してある。 The alignment film provided on the liquid crystal side of 32 is omitted, and the polarizing plates provided on the outside of the thin film transistor substrate 31 and the outside of the counter substrate 32 are omitted.
図 1に示す液晶表示装置 3 0に備えらた薄膜トランジスタ基板 3 1にあっては 、 後工程で他の層をエッチングする際に使用される酸化力のある酸系エッチング 剤がゲート電極 4 0やソース電極 4 6やドレイン電極 4 8にまでしみ込んで来て も銅層 4 0 a , 4 6 a , 4 8 aの周囲にそれぞれ保護層として作用する上記被膜 In the thin film transistor substrate 31 provided in the liquid crystal display device 30 shown in FIG. 1, an oxidizing acid-based etching agent used for etching another layer in a later process is used for the gate electrode 40 and the like. The above-mentioned coating acting as a protective layer around the copper layers 40a, 46a and 48a even if it penetrates to the source electrode 46 and the drain electrode 48.
4 0 b , 4 6 b , 4 8 bが形成されているので、 各電極がエッチング剤により損 傷を受けにくく、 各電極が下地から剥離するのを防止できるうえ断線不良の発生 を防止でき、 また、 用いるエッチング剤の自由度が大きい。 Since 40b, 46b and 48b are formed, each electrode is damaged by the etching agent. It is less susceptible to damage, prevents each electrode from peeling off from the base, and prevents the occurrence of disconnection failure. Also, the degree of freedom of the etching agent used is large.
また、 フォトリソグラフィ一工程で使用されるレジスト剥離液がゲート電極 4 0やソース電極 4 6やドレイン電極 4 8にまでしみ込んで来ても銅層 4 0 a , 4 6 a , 4 8 aの周囲にそれぞれ上記被膜 4 0 b , 4 6 b , 4 8 bが形成されてい るので、 レジス卜剥離液により各電極の表面の腐食を防止できる。  In addition, even if the resist stripping solution used in one photolithography step penetrates into the gate electrode 40, the source electrode 46, and the drain electrode 48, the periphery of the copper layers 40a, 46a, and 48a Since the coatings 40b, 46b, and 48b are formed on the respective electrodes, the surface of each electrode can be prevented from being corroded by the resist stripping solution.
また、 ゲート電極 4 0やソース電極 4 6やドレイン電極 4 8は、 銅層 4 0 a， 4 6 a , 4 8 aの外周面にそれぞれ上記被膜 4 0 b , 4 6 b , 4 8 bが形成され ているので、 エッチング前に水分の存在により各電極の表面に酸化層が形成され ることがなくなり、 酸化力のないエッチング剤により損傷を受けにくく、 断線不 良の発生を防止できる。 また、 ゲート電極 4 0やソース電極 4 6やトレイン電極 4 8は、 それぞれ被膜 4 O b , 4 6 b , 4 8 bを有しているので、 これら電極上 に C V D法等により絶縁膜 4 1やパッシベーション膜 4 9を形成する際に、 電極 4 0， 4 6， 4 8を構成する C uと絶縁膜等の形成材料の S i ガスとの反応 を防止できるので、 上記反応に起因して銅層の表面に針状突起が生じることがな く、 該針状突起により絶縁抵抗不良が起こるのを防止できる。  The gate electrode 40, the source electrode 46, and the drain electrode 48 have the above-mentioned coatings 40b, 46b, 48b on the outer peripheral surface of the copper layer 40a, 46a, 48a, respectively. Since it is formed, an oxide layer is not formed on the surface of each electrode due to the presence of moisture before etching, and the electrode is less likely to be damaged by an etching agent having no oxidizing power, thereby preventing the occurrence of disconnection failure. Further, since the gate electrode 40, the source electrode 46, and the train electrode 48 have the coatings 4Ob, 46b, and 48b, respectively, the insulating film 41 When forming the passivation film 49 or the passivation film 49, the reaction between Cu constituting the electrodes 40, 46, and 48 and the Si gas of the forming material such as the insulating film can be prevented. Needle-like projections do not occur on the surface of the copper layer, and the needle-like protrusions can prevent insulation failure from occurring.
また、 ゲート電極 4 0やソース電極 4 6やドレイン電極 4 8は、 銅層 4 0 a , 4 6 a , 4 8 aの外周面にそれぞれバリヤ一層として作用する上記被膜 4 0 b， 4 6 b , 4 8 bが形成されているので、 基体 3 6から S iが拡散してきても上記 被膜 4 0 bによりゲー卜電極 4 0への原子の拡散が阻害され、 ゲート電極 4 0の 抵抗の上昇を防止でき、 また、 銅層 4 0 aから C u原子がゲート絶縁膜 4 1に拡 散しょうとしても被膜 4 0 bにより上記 C u原子のゲ一卜絶縁膜 4 1への拡散が 阻害され、 銅層 4 0 aからの C u原子の拡散に起因する絶縁耐圧不良を防止でき 、 銅層 4 6 a , 4 8 aから C u原子が半導体能動膜 4 2に拡散しょうとしても被 膜 4 6 b , 4 8 bにより上記 C u原子の拡散が阻害され、 銅層 4 6 a， 4 8 a力、 らの C u原子の拡散に起因する半導体能動膜 4 2の特性の劣化を防止できる。 また、 電極 4 8は、 I T Oからなる画素電極と直接接触させても、 配線材料と してアルミニウムを用いる場合のように I T O中の酸素が電極 4 8を酸化するこ とがなく、 I T Oとのコンタクト抵抗が低い。 従って、 実施形態の薄膜トランジスタ基板 3 1によれば、 低抵抗の銅を配線材 料として用いる特性を損なうことなく、 水分や酸素に対する耐酸化性を向上でき 、 しかもエッチング剤やレジスト剥離液などに対する耐性を向上できるので、 下 地膜との密着性を向上でき、 断線不良や腐食を防止でき、 また、 用いるエツチン グ剤の自由度が大きいので、 銅配線形成後の工程が制約されにくく、 さらに、 隣 接膜との間での元素の相互拡散を防止できるので、 絶縁耐圧が良好で半導体能動 膜の特性が良好な薄膜卜ランジス夕基板を提供できる。 The gate electrode 40, the source electrode 46, and the drain electrode 48 are formed on the outer surfaces of the copper layers 40a, 46a, and 48a, respectively, as the coatings 40b, 46b acting as barrier layers. , 48b are formed, so that even if Si diffuses from the substrate 36, diffusion of atoms to the gate electrode 40 is inhibited by the coating 40b, and the resistance of the gate electrode 40 increases. In addition, even if Cu atoms diffuse from the copper layer 40a into the gate insulating film 41, the coating 40b inhibits the diffusion of the Cu atoms into the gate insulating film 41. Insufficient dielectric strength due to diffusion of Cu atoms from the copper layer 40a can be prevented, and even if Cu atoms diffuse from the copper layers 46a and 48a to the semiconductor active film 42, the film 4 The diffusion of the Cu atoms is inhibited by 6 b and 48 b, and the deterioration of the characteristics of the semiconductor active film 42 caused by the diffusion of the Cu atoms by the copper layers 46 a and 48 a can be prevented. You. In addition, even if the electrode 48 is brought into direct contact with the pixel electrode made of ITO, oxygen in the ITO does not oxidize the electrode 48 as in the case where aluminum is used as a wiring material, and the electrode 48 is not in contact with ITO. Low contact resistance. Therefore, according to the thin film transistor substrate 31 of the embodiment, the oxidation resistance to moisture and oxygen can be improved without impairing the characteristics of using low-resistance copper as a wiring material, and the resistance to an etching agent, a resist stripping solution, and the like can be improved. Can improve the adhesion to the underlying film, prevent disconnection defects and corrosion, and have a high degree of freedom in the use of an etching agent. Since the interdiffusion of elements with the contact film can be prevented, a thin film transistor substrate having a good withstand voltage and good characteristics of the semiconductor active film can be provided.
第 1実施形態の液晶表示装置 3 0によれば、 上述のような薄膜トランジスタ基 板 3 1が備えられているので、 配線抵抗に起因する信号電圧降下や配線遅延が生 じにくく、 配線が長くなる大面積の表示や配線が細くなる高精細な表示に最適な 表示装置を容易に実現できるという利点がある。 また、 下地からの配線の剥離が なく、 断線不良や腐食の発生がなく、 しかも配線と隣接膜との間での元素の相互 拡散を防止できる薄膜トランジスタ基板 3 1が備えられているので、 特性の良好 な液晶表示装置を提供できる。  According to the liquid crystal display device 30 of the first embodiment, since the thin film transistor substrate 31 as described above is provided, a signal voltage drop or a wiring delay due to wiring resistance is unlikely to occur, and the wiring becomes longer. There is an advantage that a display device optimal for large-area display and high-definition display in which wiring is narrow can be easily realized. In addition, the thin film transistor substrate 31 is provided, which does not peel off the wiring from the base, does not cause disconnection failure or corrosion, and prevents mutual diffusion of elements between the wiring and the adjacent film. A good liquid crystal display device can be provided.
次に、 本発明の薄膜トランジスタ基板の製造方法を図 1に示す構造の薄膜トラ ンジス夕基板を製造する方法に適用した実施形態例について説明する。  Next, an embodiment in which the method for manufacturing a thin film transistor substrate of the present invention is applied to a method for manufacturing a thin film transistor substrate having the structure shown in FIG. 1 will be described.
図 4は、 第 1実施形態の薄膜トランジスタ基板の製造方法に好適に用いられる 薄膜の製造装置の成膜室を示す概略構成図であり、 図 5は、 薄膜の製造装置の全 体構成を示す平面図であり、 図 6は、 図 5に示す薄膜の製造装置の一部を拡大し た側面図である。  FIG. 4 is a schematic configuration diagram illustrating a film forming chamber of a thin film manufacturing apparatus suitably used in the thin film transistor substrate manufacturing method according to the first embodiment. FIG. 5 is a plan view illustrating an overall configuration of the thin film manufacturing apparatus. FIG. 6 is a side view in which a part of the thin film manufacturing apparatus shown in FIG. 5 is enlarged.
図 4は、 減圧状態に保持可能な成膜室を示し、 この成膜室 6 0は、 図 5に示す ように搬送室 6 1の側部にゲートバルブ 6 2を介して接続されている。  FIG. 4 shows a film forming chamber capable of maintaining a reduced pressure. The film forming chamber 60 is connected to the side of the transfer chamber 61 via a gate valve 62 as shown in FIG.
上記搬送室 6 1の周囲には成膜室 6 0の他に、 口一夕" 一室 6 3とアンロー夕 " 一室 6 4とストッカーチャンバ 6 5がそれぞれ搬送室 6 1を囲むように接続さ れ、 搬送室 6 1とその周囲の各室との間にはそれぞれゲートバルブ 6 6、 6 7、 6 8が設けられている。 以上の説明のように、 成膜室 6 0と搬送室 6 1とロー夕 、' 室 6 3とアンロー夕" 一室 6 4とストッカーチャンバ 6 5により薄膜の製造装 置 A ' が構成されている。  Around the transfer chamber 61, in addition to the film forming chamber 60, a single chamber 63, an unloading chamber 64, and a stocker chamber 65 are connected so as to surround the transfer chamber 61, respectively. Gate valves 66, 67, 68 are provided between the transfer chamber 61 and each of the surrounding rooms. As described above, the film forming chamber 60, the transfer chamber 61, and the low chamber, the “chamber 63 and the low chamber”, one chamber 64, and the stocker chamber 65 constitute the thin film manufacturing apparatus A ′. I have.
上記成膜室 6 0は、 図 4に示すように、 その上部に第 1の電極 7 0が設けられ 、 第 1の電極 7 0の底面に夕ーゲット 7 1が着脱自在に装着されているとともに 、 成膜室 6 0の底部には第 2の電極 7 2が設けられ、 第 2の電極 7 2の上面に少 なくとも表面が絶緣性である基板 3 6が着脱自在に装着されている。 As shown in FIG. 4, a first electrode 70 is provided above the film forming chamber 60. A target 71 is removably mounted on the bottom surface of the first electrode 70, and a second electrode 72 is provided at the bottom of the film forming chamber 60. A substrate 36 having at least an instable surface is detachably mounted on the upper surface.
上記ターゲッ ト 7 1をなす材料としては、 ゲート電極 4 0、 ソース電極 4 6、 ドレイン電極 4 8を形成する場合、 チタン、 モリブデン、 クロム、 タンタルのう ちから選択されたいずれかの金属と、 銅が用いられ、 a — S i : n +層を形成す る 場合、 n型 a— S i ： n +生成用の P ドープ S iが用いられる。 上記基板 3 6 と しては、 薄膜トランジスタ基板を製造する場合にはガラス基板を好適に用い ることができる。 なお、 上記ターゲット 7 1の装着には静電チャックなどの通常 知られた夕ーゲッ ト装着機構を用いることができる。 When forming the gate electrode 40, the source electrode 46, and the drain electrode 48, the target 71 is made of a metal selected from titanium, molybdenum, chromium, tantalum, and copper. When an a—Si: n + layer is formed, P-doped Si for n-type a—Si: n + generation is used. A glass substrate can be suitably used as the substrate 36 when a thin film transistor substrate is manufactured. The target 71 can be mounted using a generally known evening target mounting mechanism such as an electrostatic chuck.
上記第 1の電極 7 0は、 導電性材料からなる母体 7 0 aとこの母体 7 0 aの表 面に形成された酸化膜、 窒化膜あるいはフッ化膜などからなる保護層 7 0 bとか ら構成されている。  The first electrode 70 includes a base 70a made of a conductive material and a protective layer 70b formed of an oxide film, a nitride film, a fluoride film, or the like formed on the surface of the base 70a. It is configured.
そして、 上記第 1の電極 7 0には第 1の交流電源 7 5が接続されるとともに、 第 1の電極 7 0と第 1の交流電源 7 5との間には整合回路 7 5 aが組み込まれて いて、 この整合回路 7 5 aは高周波電力の反射波をゼロにする作用を奏する。 ま た、 第 1の電極 7 0には、 インピーダンス調整用のローパスフィル夕などのバン ドパスフィル夕 Ί 7を介して直流電源 7 8が接続されている。 このバンドパスフ ィル夕 7 7は、 直流電源 7 8に高周波が乗らないように回路のインピーダンスを 無限大に調整するものである。  A first AC power supply 75 is connected to the first electrode 70, and a matching circuit 75a is incorporated between the first electrode 70 and the first AC power supply 75. Thus, the matching circuit 75a has an effect of reducing the reflected wave of the high-frequency power to zero. Further, a DC power supply 78 is connected to the first electrode 70 via a band-pass filter 7 such as a low-pass filter for impedance adjustment. This bandpass filter 77 adjusts the impedance of the circuit to infinity so that high frequency does not get on the DC power supply 78.
更に、 上記第 2の電極 7 2にも第 2の交流電源 8 0が接続されるとともに、 第 2の電極 7 2と第 2の交流電源 8 0の間には上記整合回路 7 5 aと同様の作用を 奏する整合回路 8 0 aが組み込まれている。  Further, a second AC power supply 80 is also connected to the second electrode 72, and the same as the matching circuit 75a between the second electrode 72 and the second AC power supply 80. A matching circuit 80a having the function of (1) is incorporated.
なお、 上記成膜室 6 0には、 真空引き用およびガス排気用の排気ユニット 6 0 a、 成膜室 6 0内への反応ガス供給機構 6 0 b等を含んでいるが図 4では説明の 簡略化のためにこれらを簡略化して記載した。  The film forming chamber 60 includes an exhaust unit 60a for evacuation and gas exhaust, a reaction gas supply mechanism 60b into the film forming chamber 60, etc. These are simplified and described for simplification.
次に、 上記搬送室 6 1には、 リンク式の搬送機構 （マジックハンド） 6 9が設 けられ、 この搬送機構 6 9は搬送室 6 1の中心部に立設された支軸 7 4を支点と して回動自在に設けられ、 ストッカーチャンバ 6 5に配置されているカセット 7 9から夕ーゲッ 卜 7 1を取り出して必要に応じて成膜室 6 0に搬送し、 成膜室 6 0の第 1の電極 7 0に夕ーゲッ ト 7 1を装着できるようになつている。 Next, a link-type transfer mechanism (magic hand) 69 is provided in the transfer chamber 61, and the transfer mechanism 69 is provided with a support shaft 74 erected at the center of the transfer chamber 61. A cassette 7 rotatably provided as a fulcrum and disposed in the stocker chamber 65 The evening getter 71 is taken out from the container 9 and transported to the film forming chamber 60 as necessary, so that the evening getter 71 can be mounted on the first electrode 70 of the film forming chamber 60.
なお、 上記カセッ ト 7 9にはダミーターゲット 7 1 aも収納されていて、 必要 に応じてダミー夕ーゲット 7 1 aも成膜室 6 0に搬送できるようになつている。 図 4乃至図 6に示す薄膜の製造装置は、 1つの成膜室 6 0で 1つ以上の薄膜 （ 例えば、 ゲート電極 4 0を形成するための金属膜と銅膜と、 ゲート絶縁膜 4 1と 、 半導体能動膜 4 2と、 ォーミックコンタクト膜 4 3， 4 4と、 ソース電極 4 6 を形成するための金属膜と銅膜と、 ドレイン電極 4 8を形成するための金属膜と 銅膜、 パッシベーシヨン膜 4 9 ) を連続成膜することができる装置である。  The cassette 79 also contains a dummy target 71a, so that the dummy target 71a can be transported to the film forming chamber 60 as necessary. The thin film manufacturing apparatus shown in FIGS. 4 to 6 includes one or more thin films (for example, a metal film and a copper film for forming the gate electrode 40, a gate insulating film 41) in one deposition chamber 60. , A semiconductor active film 42, an ohmic contact film 43, 44, a metal film and a copper film for forming a source electrode 46, and a metal film and a copper for forming a drain electrode 48. This is an apparatus capable of continuously forming a film and a passivation film 49).
即ち、 成膜室 6 0において、 C V D成膜 （ゲート絶縁膜 ·半導体能動膜 ·パッシ ベーション膜 4 9の成膜） とスパッ夕成膜 （ォーミックコンタク 卜膜 · ゲー卜電 極を形成するための金属膜と銅膜 · ソース電極を形成するための金属膜と銅膜 · ドレイン電極を形成するための金属膜と銅膜の成膜） を電源を切り替えることに より行なうことができる。 That is, in the film forming chamber 60, a CVD film formation (film formation of a gate insulating film, a semiconductor active film, a passivation film 49) and a sputtering film formation (an ohmic contact film, a gate electrode) are formed. Metal film and copper film for forming a metal film and a copper film for forming a source electrode, and forming a metal film and a copper film for forming a drain electrode).
まず、 成膜室 6 0と搬送室 6 1とストツ力一チャンバ 6 5を減圧したならば、 ゲートバルブ 6 2と 6 8を開放して搬送機構 6 9によりガラス基板 3 6を第 2の 電極 7 2に装着する。 この状態からゲートバルブ 6 2を閉じたならば、 以下のェ 程に準じて基板 3 6上にゲ一卜電極 4 0などの薄膜を順次形成する。  First, if the pressure in the film forming chamber 60, the transfer chamber 61 and the stop force chamber 65 is reduced, the gate valves 62 and 68 are opened, and the glass substrate 36 is transferred to the second electrode by the transfer mechanism 69. 7 Attach to 2. When the gate valve 62 is closed from this state, thin films such as the gate electrode 40 are sequentially formed on the substrate 36 according to the following procedure.
( 1 - 1 ) ゲー卜電極用金属膜の成膜工程  (1-1) Deposition process of metal film for gate electrode
成膜室 6 0を A rガス雰囲気とし、 第 1の電極 7 0にチタン、 モリブデン、 ク ロム、 タンタルのうちから選択されたいずれかの金属からなるターゲット 7 1を 装着し、 第 2の電極 7 2にはガラス基板 3 6を装着したままで、 第 1の交流電源 7 5力ゝら第 1の電極 7 0に周波数 1 3 . 6 MH z程度の高周波を供給し、 更に直 流電源 7 8から負荷する負荷電位を一 2 0 0 Vにしてスパッタリングを行ない、 図 7 Aに示すように基板 3 6上に膜厚 5 0 n m程度の金属膜 4 0 eを形成する。 なお、 金属膜 4 0 eの表面には、 該金属膜 4 0を構成する金属元素と成膜室 6 0内の残留酸素が反応して金属の酸化層が形成されている場合があるため、 その 場合にはこの金属の酸化層を、 プラズマエッチングにより除去しておくことが好 ましい。 ここでのプラズマエッチングは、 成膜室 6 0を A rガス雰囲気とし、 第 1の電極 7 0にダミーターゲッ 卜 7 1 aを装着し、 第 2の電極 7 2には金属膜 4 0 eを形成したガラス基板 3 6を装着したままで、 第 1の交流電源 7 5から第 1 の電源 7 0に高周波を供給し、 負荷電位をフローティングしてプラズマを発生さ せるとともに、 第 2の電極 7 2に高周波電力を供給し基板 3 6に 2 0 0 W程度の 交流電力を 2分程度印加することにより行われる。 The film forming chamber 60 is set to an Ar gas atmosphere, and a target 71 made of a metal selected from titanium, molybdenum, chromium, and tantalum is mounted on the first electrode 70, and the second electrode 70 While a glass substrate 36 is attached to 72, a high frequency of about 13.6 MHz is supplied to the first AC power supply 75 to the first electrode 70, and a direct current power supply 7 Sputtering is performed with the load potential applied from 8 set to 120 V, and a metal film 40 e having a thickness of about 50 nm is formed on the substrate 36 as shown in FIG. 7A. Note that a metal oxide layer may be formed on the surface of the metal film 40 e by a reaction between a metal element constituting the metal film 40 and residual oxygen in the film formation chamber 60. In this case, it is preferable to remove the metal oxide layer by plasma etching. In this plasma etching, the film forming chamber 60 was set to an Ar gas atmosphere, With the dummy target 71 a attached to the first electrode 70 and the glass substrate 36 on which the metal film 40 e is formed attached to the second electrode 72, the first AC power supply 75 A high frequency is supplied to the first power source 70, a load potential is floated to generate plasma, and a high frequency power is supplied to the second electrode 72 to supply about 200 W AC power to the substrate 36. This is performed by applying for about 2 minutes.
( 1 - 2 ) ゲート電極用銅膜の 2周波励起スパッ夕成膜工程  (1-2) Dual frequency excitation sputtering deposition process of copper film for gate electrode
成膜室 6 0を非酸化雰囲気として A rガス雰囲気とし、 第 1の電極 7 0に銅か らなる夕ーゲッ 卜 7 1を装着し、 第 2の電極にはガラス基板 3 6を装着したまま で、 直流電源 7 8を作動させて直流電力を夕一ゲット 7 1に印加するとともに第 2の交流電源 8 0を作動させて交流電力をガラス基板 3 6に印加する 2周波励起 スパッ夕法により、 銅膜のスパッ夕成膜を行い、 図 7 Bに示すように基板 3 6に 形成された金属膜 4 0 e上に膜厚 1 5 0 n m程度の銅膜 4 0 cを形成する。 この 工程では、 基板 3 6に印加する交流電力は、 0 . 1乃至 5 WZ c m 2程度である。 このようにすると、 銅膜 4 0 cを構成する C uの結晶の粒径 を小さくできるので 、 C uの結晶の粒界が多くなり'、 上記金属膜 4 0 e中の元素が銅膜 4 0 c中に引 き込まれ、 この引き込まれた元素の拡散が促進される。 The film forming chamber 60 is a non-oxidizing atmosphere and an Ar gas atmosphere, and the first electrode 70 is equipped with a copper gate 71 and the second electrode is kept with the glass substrate 36 attached. Then, the DC power supply 78 is operated to apply DC power to the evening getter 71, and the second AC power supply 80 is operated to apply AC power to the glass substrate 36. Then, a copper film is formed by sputtering, and a copper film 40c having a thickness of about 150 nm is formed on the metal film 40e formed on the substrate 36 as shown in FIG. 7B. In this step, the AC power applied to the substrate 36 is about 0.1 to 5 WZ cm 2 . By doing so, the grain size of the Cu crystal constituting the copper film 40c can be reduced, so that the grain boundary of the Cu crystal increases, and the elements in the metal film 40e It is drawn into 0 c, and the diffusion of the drawn element is promoted.
( 1 - 3 ) ゲー卜電極用金属膜及び銅膜のパターニング工程  (1-3) Patterning process of gate electrode metal film and copper film
銅膜 4 0 cの表面にレジストを塗布してパターン露光し、 エッチングにより銅 膜 4 0 cと金属膜 4 0 eの不要部分を除去した後にレジストを剥離するパター二 ングを施して、 図 7 Cに示すような所望の線幅の銅層 （銅配線） 4 0 aと金属膜 4 0 eの積層膜を形成する。  A resist was applied to the surface of the copper film 40c and subjected to pattern exposure. After removing unnecessary portions of the copper film 40c and the metal film 40e by etching, patterning was performed to remove the resist. A laminated film of a copper layer (copper wiring) 40a and a metal film 40e having a desired line width as shown in C is formed.
( 1 - 4 ) 基板 （基体） の第一ァニール工程  (1-4) First annealing process of substrate (substrate)
銅層 4 0 aと金属膜 4 0 eの積層膜が形成された基板 3 6を A rガス雰囲気 でァニール処理し、 上記銅層 4 0 a中に引き込まれた金属膜 4 0 eの金属元素を 上記銅層 4 0 aの表面に拡散し、 図 7 Dに示すような上記銅層 4 0 aの周囲にチ タン、 モリブデン、 クロム、 タンタルのうちから選択された金属の被膜 4 0 が 形成されたゲート電極 4 0を得る。 ここで形成された被膜 4 0 bの厚みは、 5 n m乃至 2 0 n m程度である。  The substrate 36 on which the laminated film of the copper layer 40a and the metal film 40e is formed is subjected to an annealing treatment in an Ar gas atmosphere, and the metal element of the metal film 40e drawn into the copper layer 40a. Is diffused to the surface of the copper layer 40a, and a metal film 40 selected from titanium, molybdenum, chromium, and tantalum is formed around the copper layer 40a as shown in FIG. 7D. Obtained gate electrode 40 is obtained. The thickness of the coating 40b formed here is about 5 nm to 20 nm.
ここでのァニール処理条件は、 4 0 0 °C程度で 2時間程度である。 また、 ァニール時の雰囲気に酸素を含ませないで行うと酸素原子の含有割合が 0原子％の被膜 4 0 bが得られ、 また、 上記ァニール時の雰囲気の酸素分圧を順 次増やすことにより、 被膜 4 0 b中の酸素原子の含有割合を順次増加できる。 従って、 基板 3 6上にチタンからなる金属膜 4 0 eを形成した場合は、 チタン またはチタン酸化物からなる被膜 4 0 bが形成され、 より具体的には、 チタン原 子数に対する酸素原子数の比が 1対 0乃至 1対 2である組成の被膜 4 0 bが形成 され、 モリブデンからなる金属膜 4 0 eを形成した場合は、 モリブデンまたはモ リブデン酸化物からなる被膜 4 0 bが形成され、 より具体的にはモリブデン原子 数に対する酸素原子数の比が 1対 0乃至 1対 3である組成の被膜 4 0 bが形成さ れ、 クロムからなる金属膜 4 0 eを形成した場合はクロムまたはクロム酸化物か らなる被膜 4 0 bが形成され、 より具体的にはクロム原子数に対する酸素原子数 の比が 1対 0乃至 1対 2である組成の被膜 4 0 bが形成され、 タンタルからなる 金属膜 4 0 eを形成した場合はタンタルまたはタンタル酸化物からなる被膜 4 0 bが形成され、 より具体適にはタンタル原子数に対する酸素原子数の比が 1対 0 乃至 1対 2 . 5である組成の被膜 4 0 bが形成される。 The annealing treatment conditions here are about 400 ° C. for about 2 hours. In addition, when the annealing is performed without oxygen in the atmosphere, a film 40b having an oxygen atom content of 0 atomic% is obtained. In addition, by gradually increasing the oxygen partial pressure in the annealing atmosphere, The content ratio of oxygen atoms in the coating 40b can be sequentially increased. Therefore, when a metal film 40 e made of titanium is formed on the substrate 36, a coating 40 b made of titanium or titanium oxide is formed, and more specifically, the number of oxygen atoms with respect to the number of titanium atoms In the case where a coating 40b having a composition ratio of 1: 0 to 1: 2 is formed and a metal film 40e made of molybdenum is formed, a coating 40b made of molybdenum or molybdenum oxide is formed. More specifically, when a coating 40b having a composition in which the ratio of the number of oxygen atoms to the number of molybdenum atoms is 1: 0 to 1: 3 is formed, and the metal film 40e made of chromium is formed, A coating 40b made of chromium or chromium oxide is formed, and more specifically, a coating 40b having a composition in which the ratio of the number of oxygen atoms to the number of chromium atoms is 1: 0 to 1: 2 is formed, When a metal film made of tantalum 40 e is formed, tantalum Or a film 40b made of tantalum oxide, and more specifically, a film 40b having a composition in which the ratio of the number of oxygen atoms to the number of tantalum atoms is 1: 0 to 1: 2.5. You.
また、 チタンからなる金属膜 4 0 eの厚みや、 ァニール温度を 4 0 0 ° C乃至 1 2 0 0 ° Cの範囲、 ァニール時間 3 0分間乃至 1時間の範囲で変更することに より、 図 2に示すように銅層 4 0 aの周囲に形成されたチタン膜 4 0 f と該チ夕 ン膜 4 0 f の表面に形成されたチタン原子数に対する酸素原子数の比が 1対 1乃 至 1対 2である組成の膜などのチタン酸化物からなる膜 4 0 gとを有してなる被 膜 4 0 ゃ、 図 3に示すように銅層 4 0 aの周囲の一部に形成されたチタン膜 4 O hと、 銅層 4 0 aの周囲の残部に形成されたチタン原子数に対する酸素原子数 の比が 1対 1乃至 1対 2である組成の膜などのチタン酸化物からなる膜 4 0 i と を有してなる被膜 4 0 bを形成できる。  Further, by changing the thickness of the metal film 40e made of titanium and the anneal temperature in the range of 400 ° C. to 1200 ° C. and the anneal time in the range of 30 minutes to 1 hour, FIG. As shown in FIG. 2, the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the titanium film 40f formed on the periphery of the copper layer 40a and the titanium film 40f is 1: 1-1. A film 40 g comprising a film of titanium oxide, such as a film having a composition of 1 to 2, having a thickness of 40 g, which is formed on a part of the periphery of the copper layer 40 a as shown in FIG. Titanium oxide such as a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed in the remainder around the copper layer 40a is 1: 1 to 1: 2. The film 40b having the film 40i and the film 40b can be formed.
( 1 - 5 ) ゲート絶縁膜 （窒化ケィ素膜） 4 1の（： 0成膜ェ程  (1-5) Gate insulating film (silicon nitride film)
成膜室 6 0を S i H + N H + N 2混合ガス雰囲気とし、 第 1の電極 7 0にダ ミー夕ーゲットァ 1 aを装着し、 第 1の交流電源 7 5から第 1の電極 7 0に周波 数 2 0 O MH zの高周波を供給し、 負荷電位をフローティングしてプラズマを発 生させて窒化ケィ素膜を基板 3 6上に堆積させる C V D成膜を行ない、 図 8 Aに 示すようなゲート絶縁膜 4 1を形成する。 この CVD成膜の場合は、 第 1の電極 70に装着されたダミー夕ーゲッ 卜 7 1 aをスパッ夕しないように供給する周波 数を大きく設定し、 第 1の電極 70にかかるイオンエネルギーを小さくするとと もに、 第 2の電極 72に高周波電力を供給し、 基板 36にかかるイオンエネルギ —を制御する。 The film forming chamber 60 is set to a mixed gas atmosphere of SiH + NH + N2, a dummy electrode 1a is attached to the first electrode 70, and the first electrode power supply 75 to the first electrode 70 A high frequency of 20 OMHz is supplied to the substrate, and a load potential is floated to generate plasma to deposit a silicon nitride film on the substrate 36. A gate insulating film 41 as shown is formed. In the case of this CVD film formation, the frequency supplied to the dummy electrode 71a mounted on the first electrode 70 so as not to spatter is set to a large value, and the ion energy applied to the first electrode 70 is reduced. At the same time, high-frequency power is supplied to the second electrode 72 to control ion energy applied to the substrate 36.
( 1 - 6) 半導体能動膜 （a— S i層） 42の CVD成膜工程  (1-6) CVD process of semiconductor active film (a-Si layer) 42
成膜室 60を S i + 混合ガス雰囲気とし、 第 1の電極 70にダミー夕一 ゲッ ト 7 1 aを装着したままで第 1の交流電源 7 5力ゝら第 1の電極 70に周波数 200 MH z程度の高周波を供給し、 更に、 第 2の交流電源 80から第 2の電極 72に高周波電力を供給し、 ガラス基板 36にかかるイオンエネルギーを制御し て a - S i層の成膜を行い、 半導体能動膜 42を形成する。  The film formation chamber 60 is set to a mixed gas atmosphere of Si +, and the first AC power supply 75 is supplied to the first electrode 70 while the dummy electrode 71 1a is attached to the first electrode 70. A high frequency of about MH z is supplied, and a high frequency power is supplied from the second AC power supply 80 to the second electrode 72 to control the ion energy applied to the glass substrate 36 to form the a-Si layer. Then, a semiconductor active film 42 is formed.
( 1 - 7) ォーミックコンタク ト膜 （a— S i ： n+層） 43 aのスパッ夕成膜 工程  (1-7) Ohmic contact film (a- S i: n + layer) 43 a sputter deposition process
成膜室 60を A rガス雰囲気とし、 第 1の電極 70に a— S i ： n+層生成用 の Pドープ S iからなる夕ーゲッ 卜 7 1を装着し、 第 1の交流電源 75から第 1 の電極 70に周波数 1 3.6 MH z程度の高周波を供給し、 更に直流電源 78か ら負荷する負荷電位を一 200 Vにしてスパッタリングを行ない、 半導体能動膜 42上にォーミックコンタクト膜 43 aを形成する。 The film forming chamber 60 is set to an Ar gas atmosphere, and a first electrode 70 made of P-doped Si for a—Si: n + layer formation is mounted on the first electrode 70. A high frequency having a frequency of about 13.6 MHz is supplied to the first electrode 70, and a sputtering is performed by setting the load potential applied from the DC power supply 78 to 1200 V, and the ohmic contact film 43 is formed on the semiconductor active film 42. Form a.
(1 -8) 半導体能動膜とォーミックコンタクト膜のパターニング工程 ォ一ミックコンタクト膜 43 aの表面にレジストを塗布してパターン露光し、 エッチングにより不要部分を除去した後にレジストを剥離するパターニングを施 して、 図 8 Aに示すようにゲート電極 40よりも小さいアイランド状の半導体能 動膜 42とォーミックコンタクト膜 43 aを得る。 半導体能動膜 42と、 ォ一ミ ックコン夕クト膜 43 aの形成位置は、 ゲー卜電極 40上のゲート絶縁膜 4 1に おいてゲー卜電極 40と対向する位置である。  (1-8) Patterning process of semiconductor active film and ohmic contact film A resist is applied to the surface of the ohmic contact film 43a, pattern exposure is performed, and after removing unnecessary portions by etching, patterning for removing the resist is performed. As a result, an island-shaped semiconductor active film 42 and an ohmic contact film 43a smaller than the gate electrode 40 are obtained as shown in FIG. 8A. The positions where the semiconductor active film 42 and the amorphous contact film 43 a are formed are positions facing the gate electrode 40 in the gate insulating film 41 on the gate electrode 40.
(1 - 9) ソース電極及びドレイン電極用金属膜の成膜工程  (1-9) Deposition process of metal film for source electrode and drain electrode
図 8 Aに示すようにォーミックコンタクト膜 43 aの上面と両側面とその下の 半導体能動膜 42の両側面とそれらに連続するゲート絶縁膜 4 1の上面の一部分 を覆うように、 膜厚 50 nm程度の金属膜 46 eを上述のゲー卜電極用金属膜の 成膜工程と同様にして形成する。 なお、 金属膜 4 6 eの表面には、 金属の酸化層 が形成されている場合があるため、 その場合にはこの金属の酸化層を、 先に述べ た金属膜 4 0 eをプラズマエッチングする方法と同様にして除去しておくことが 好ましい。 As shown in FIG. 8A, the film is formed so as to cover the upper surface and both side surfaces of the ohmic contact film 43a, the both side surfaces of the semiconductor active film 42 therebelow, and a part of the upper surface of the gate insulating film 41 continuous therewith. The metal film 46 e having a thickness of about 50 nm is used as the metal film for the gate electrode described above. The film is formed in the same manner as the film forming process. In some cases, a metal oxide layer is formed on the surface of the metal film 46 e. In this case, the metal oxide layer is subjected to plasma etching of the metal film 40 e described above. It is preferable to remove them in the same manner as in the method.
( 1 - 1 0 ) ソース電極及びドレイン電極用銅膜の 2周波励起スパッ夕成膜工程 図 8 Aに示すように金属膜 4 6 e上に膜厚 1 5 0 n m程度の銅膜 4 6 cを上述 のゲート電極用銅膜の 2周波励起スパッ夕成膜工程と同様にして形成する。 この ようにすると、 上記金属膜 4 6 e中の元素が銅膜 4 6 c中に引き込まれる。 (1-10) Dual frequency excitation sputtering film formation process of copper film for source electrode and drain electrode As shown in Fig. 8A, copper film of about 150 nm thickness 46 c on metal film 46 e Is formed in the same manner as in the above-described two-frequency excitation sputtering film formation process of the gate electrode copper film. By doing so, the elements in the metal film 46e are drawn into the copper film 46c.
( 1 - 1 1 ) ソース電極及びドレイン電極用金属膜及び銅膜と、 半導体能動膜と ォーミックコン夕ク卜膜のパターニング工程 (1-1-1) Patterning process of metal film and copper film for source electrode and drain electrode, semiconductor active film and ohmic contact film
半導体能動膜 4 2の中央部分の上部をエッチングにより除去し、 半導体能動膜 4 2の中央部分上のォーミックコン夕クト膜 4 3 aと金属膜 4 3 aと銅膜 4 6 e を除去することで、 図 8 Bに示すように半導体能動膜 4 2の両端部分上に相互に 離隔したォーミックコンタクト膜 4 3， 4 4と、 ソース電極 4 6形成用金属膜 4 6 e及び銅層 4 6 aと、 ドレイン電極 4 8形成用金属膜 4 6 eと銅層 4 8 aとを 形成することができる。  The upper portion of the central portion of the semiconductor active film 42 is removed by etching, and the ohmic contact film 43 a, the metal film 43 a, and the copper film 46 e on the central portion of the semiconductor active film 42 are removed. As shown in FIG. 8B, ohmic contact films 43, 44 spaced apart from each other on both ends of the semiconductor active film 42, a metal film 46 e for forming a source electrode 46, and a copper layer 46. a, the drain electrode 48 forming metal film 46 e and the copper layer 48 a can be formed.
( 1 - 1 2 ) 基板の第二ァニール工程  (1-1 2) Second annealing process of substrate
ソース電極 4 6形成用金属膜 4 6 e及び銅層 4 6 aと、 ドレイン電極 4 8形成 用金属膜 4 6 eと銅層 4 8 aとが形成された基板 3 6を先に行った基板の第一ァ ニール工程と同様にしてァニール処理し、 上記銅層 4 6 a， 4 8 a中に引き込ま れた金属膜 4 6 eの金属元素を上記銅層 4 6 a， 4 8 aの表面に拡散し、 図 8 C に示すような銅層 4 6 a , 4 8 aの周囲にチタン、 モリブデン、 クロム、 タン夕 ルのうちから選択された金属の被膜 4 6 b , 4 8 bが形成されたソース電極 4 6 とドレイン電極 4 8が得られる。 ここで形成される被膜 4 6 b , 4 8 bは、 ゲー ト電極 4 0の被膜 4 0 bと同様に、 上述の割合で酸素が含まれていてもよい。 また、 ゲート電極 4 0の被膜 4 0 bを形成する場合と同様に金属膜 4 6 eの厚 みや、 ァニール条件を変更することにより、 銅層の周囲に形成されたチタン膜と 該チ夕ン膜の表面に形成されたチタン原子数に対する酸素原子数の比が 1対 1乃 至 1対 2である組成の膜などのチタン酸化物からなる膜とを有してなる被膜 4 6 b , 4 8 bや、 銅層の周囲の一部に形成されたチタン膜と、 銅層の周囲の残部に 形成されたチタン原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成 の膜などのチタン酸化物からなる膜 4 0 i とを有してなる被膜 4 6 b， 4 8 bを 形成できる。 Substrate 36 on which metal film 46 e for forming source electrode 46 and copper layer 46 a and metal film 46 e for forming drain electrode 48 and copper layer 48 a are formed first The metal element of the metal film 46 e drawn into the copper layers 46 a and 48 a is subjected to an annealing treatment in the same manner as in the first annealing step of FIG. Around the copper layers 46a and 48a, as shown in Fig. 8C, forming a film 46b and 48b of a metal selected from titanium, molybdenum, chromium, and tungsten. The source electrode 46 and the drain electrode 48 thus obtained are obtained. The coatings 46 b and 48 b formed here may contain oxygen in the above-described ratio, similarly to the coating 40 b of the gate electrode 40. Also, by changing the thickness of the metal film 46 e and the annealing conditions as in the case of forming the coating 40 b of the gate electrode 40, the titanium film formed around the copper layer and the titanium film are removed. A film comprising a film of titanium oxide, such as a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the film is 1: 1 to 1: 1 2 4 6 b, 48b, and the ratio of the number of oxygen atoms to the number of titanium atoms formed on the titanium film formed on a part of the periphery of the copper layer and the remainder on the periphery of the copper layer is 1: 1 to 1: 2. Coatings 46 b and 48 b comprising titanium oxide film 40 i such as a film of a certain composition can be formed.
( 1 一 1 3 ) ノ °ッシベーシヨン膜 4 9の C V D成膜工程  (1 1 1 3) CVD film formation process of the pressure-sensitive film 49
半導体能動膜 4 2とソース電極 4 6とドレイン電極 4 8を覆うように窒化ケィ 素からなるパッシベーション膜 4 9をゲート絶縁膜 4 1の C V D成膜工程とほぼ 同様にして成膜する。  A passivation film 49 made of silicon nitride is formed so as to cover the semiconductor active film 42, the source electrode 46, and the drain electrode 48 in substantially the same manner as the CVD film forming process of the gate insulating film 41.
( 1 - 1 4 ) 画素電極形成工程  (1-14) Pixel electrode formation process
ついで、 パッシベーシヨン膜 4 9を乾式法あるいは乾式法と湿式法の併用によ りエッチングしてコンタクトホール 5 0を形成した後、 ノ °ッシベーション膜 4 9 上に I T O層を形成し、 パターニングすることにより画素電極 3 5を形成し、 図 1に示すようにコンタク 卜ホール 5 0の底面および内壁面、 パッシベ一ション膜 4 9の上面にかけて接続導体部 5 1を形成し、 この接続導体部 5 1を介してドレ ィン電極 4 8と画素電極 3 5を接続すると、 図 1と同様の薄膜トランジスタ基板 3 1が得られる。  Next, the passivation film 49 is etched by a dry method or a combination of a dry method and a wet method to form a contact hole 50, and then, an ITO layer is formed on the nomination film 49 and patterned. A pixel electrode 35 is formed, and as shown in FIG. 1, a connection conductor 51 is formed over the bottom and inner wall surfaces of the contact hole 50 and the upper surface of the passivation film 49, and this connection conductor 51 is formed. When the drain electrode 48 and the pixel electrode 35 are connected through the same, a thin film transistor substrate 31 similar to that of FIG. 1 is obtained.
なお、 基板 3 6として表面に S i 膜 3 6 aが形成されたものを用いる場合 は、 基板 3 6上に金属膜 4 0 eを形成する前に、 上述のゲート絶縁膜 4 1の C V D成膜工程と同様の方法で S i N x膜を成膜しておく。  In the case where a substrate 36 on which a Si film 36 a is formed is used, the above-mentioned CVD of the gate insulating film 41 is performed before forming the metal film 40 e on the substrate 36. A SiNx film is formed in the same manner as in the film process.
なお、 ソース配線については図面に記載していないが、 ゲート絶縁膜 4 1上に ソース電極 4 6を形成する場合の成膜時とァニール時およびエッチング時に同時 に形成すれば良い。  Although the source wiring is not shown in the drawing, the source wiring may be formed at the same time as film formation, annealing, and etching when forming the source electrode 46 on the gate insulating film 41.
上述のような薄膜トランジスタ基板 3 1の製造によれば、 上記金属膜が形成さ れた基体 3 6上に 2周波励起スパッ夕法により銅膜を成膜する成膜工程と、 該銅 膜のパ夕一ニング工程と、 上記基体のァニール工程により、 水分や酸素に対する 耐酸化性を向上でき、 しかもエッチング剤やレジス卜剥離液などに対する耐腐食 性を向上でき、 下地との密着性を向上でき、 さらに隣接膜との間での元素の相互 拡散を防止できるゲート電極 4 0、 ソース電極 4 6、 ドレイン電極 4 8を基板 3 6上に容易に形成できるので製造工程が複雑になることがない。 さらに、 本発明の薄膜トランジスタ基板の製造方法は、 低温工程で基板 3 6上 に上述のような特性を有するゲート電極 4 0、 ソース電極 4 6、 ドレイン電極 4 8を形成できるので、 6 0 0 ° C以上の加熱に耐えられないガラス基板などを基 体として用いる場合にも適用できる。 According to the manufacture of the thin film transistor substrate 31 as described above, a film forming step of forming a copper film by a two-frequency excitation sputtering method on the substrate 36 on which the metal film is formed; By the evening process and the annealing process of the substrate, the oxidation resistance to moisture and oxygen can be improved, and the corrosion resistance to an etching agent and a resist stripping solution can be improved, and the adhesion to the base can be improved. Further, since the gate electrode 40, the source electrode 46, and the drain electrode 48, which can prevent mutual diffusion of elements between adjacent films, can be easily formed on the substrate 36, the manufacturing process does not become complicated. Further, according to the method for manufacturing a thin film transistor substrate of the present invention, the gate electrode 40, the source electrode 46, and the drain electrode 48 having the above-described characteristics can be formed on the substrate 36 in a low-temperature process. The present invention can be applied to a case where a glass substrate or the like that cannot withstand heating of C or more is used as a base.
なお、 上述の実施形態の薄膜トランジスタ基板の製造方法においては、 図 4に 示したようなプラズマ装置を構成する処理室内で電極の被膜用の金属膜を形成し た場合について説明したが、 上記金属膜は通常のスパッ夕装置で形成してもよい  In the method of manufacturing a thin film transistor substrate according to the above-described embodiment, the case where a metal film for coating an electrode is formed in a processing chamber constituting a plasma apparatus as shown in FIG. 4 has been described. May be formed with a normal sputter device
(第 2実施形態） (Second embodiment)
図 9は本発明の液晶表示装置の第 2実施形態の要部を示すもので、 この第 2実 施形態の液晶表示装置 3 0 aが図 1に示した第 1実施形態の液晶表示装置 3 0と 異なるところは、 薄膜トランジスタ基板として図 9に示すような構成のボトムゲ —ト型の薄膜トランジスタ基板 3 1 aが備えられている点である。  FIG. 9 shows a main part of a liquid crystal display device according to a second embodiment of the present invention. The liquid crystal display device 30a of the second embodiment differs from the liquid crystal display device 3 of the first embodiment shown in FIG. The difference from 0 is that a bottom-gate thin film transistor substrate 31a having a configuration as shown in FIG. 9 is provided as a thin film transistor substrate.
この薄膜トランジスタ基板 3 1 aが図 1に示した薄膜トランジスタ基板 3 1と 異なるところは、 ゲート電極 4 0のガラス基板 3 6側の面に T i N層 4 5 aが設 けられ、 ソース電極 4 6のォ一ミックコンタクト膜 4 3側の面に T i N層 4 7 a が設けられ、 ドレイン電極 4 8のォーミックコン夕クト膜 4 4側の面に T i N層 4 7 bが設けられている点である。 ここでのソース電極 4 6は T i N層 4 7 aを 介してォ一ミックコンタク 卜膜 4 3と半導体能動膜 4 2に電気的に接続されてい る。 ドレイン電極 4 8は T i N層 4 7 bを介してォ一ミックコンタク卜膜 4 4と 半導体能動膜 4 2に電気的に接続されている。  The thin film transistor substrate 31 a is different from the thin film transistor substrate 31 shown in FIG. 1 in that a TiN layer 45 a is provided on the surface of the gate electrode 40 on the glass substrate 36 side, and the source electrode 46 The TiN layer 47a is provided on the surface on the side of the ohmic contact film 43, and the TiN layer 47b is provided on the surface on the side of the ohmic contact film 44 of the drain electrode 48. Is a point. Here, the source electrode 46 is electrically connected to the atomic contact film 43 and the semiconductor active film 42 via the TiN layer 47a. The drain electrode 48 is electrically connected to the ohmic contact film 44 and the semiconductor active film 42 via the TiN layer 47b.
第 2実施形態の薄膜トランジスタ基板 3 1 aにあっては、 上記のような構成と したことにより第 1実施形態の薄膜トランジスタ 3 1と同様の作用効果がある。 さらに、 この第 2実施形態のものは、 電極 4 0 、 4 6 、 4 8と基板 3 6との間に T i N層4 5 a 、 4 7 a 、 4 7 bが設けられているので、 各電極の下側の隣接膜 である基板 3 6ゃゲー卜絶縁膜 4 1などから元素が拡散してきても T i N層 4 5 a、 4 7 a , 4 7 bにより電極 4 0 、 4 6 、 4 8への原子の拡散が阻害され、 基 板 3 6や隣接膜からの元素の拡散に起因する配線抵抗の上昇の防止効果が優れる 。 また、 T i N層 4 5 a 、 4 7 a、 4 7 bによって、 電極 4 0 、 4 6 、 4 8の密 着性が向上する。 The thin film transistor substrate 31a according to the second embodiment has the same configuration and effect as the thin film transistor 31 according to the first embodiment due to the above configuration. Furthermore, in the second embodiment, the TIN layers 45a, 47a, and 47b are provided between the electrodes 40, 46, and 48 and the substrate 36, so that Even if elements are diffused from the substrate 36-gate insulating film 41, which is an adjacent film below each electrode, the electrodes 40, 46 are formed by the TiN layers 45a, 47a, and 47b. The diffusion of atoms into the substrate 48 and 48 is inhibited, and the effect of preventing an increase in wiring resistance due to the diffusion of elements from the substrate 36 or an adjacent film is excellent. In addition, the denseness of the electrodes 40, 46, and 48 is achieved by the TIN layers 45a, 47a, and 47b. The wearability is improved.
この薄膜トランジスタ基板 3 1 も図 4乃至図 6に示した薄膜の製造装置を用 いて製造できる。  This thin film transistor substrate 31 can also be manufactured by using the thin film manufacturing apparatus shown in FIGS.
以下に第 2実施形態の薄膜トランジスタ基板 3 1 aの製造方法について詳しく 説明する。  Hereinafter, a method for manufacturing the thin film transistor substrate 31a according to the second embodiment will be described in detail.
(2 - 1) ゲート電極用 T i N膜の成膜工程  (2-1) Deposition process of TiN film for gate electrode
成膜室 60を Nを含むガス雰囲気とし、 第 1の電極 70にチタンからなる夕一 ゲット 7 1を装着し、 第 2の電極 72にはガラス基板 36を装着し、 第 1の交流 電源 75から第 1の電極 70に周波数 1 3.6 MHz程度の高周波を供給し、 更 に直流電源 78から負荷する負荷電位を一 200 Vにしてスパッタリングを行な い、 図 1 OAに示すように基板 36上に膜厚 50 nm程度の T i N膜 45を形成 する。 ここでの Nを含むガス雰囲気としては、 、 Ν,Ο, NO'などのガスと、 A rガスの混合ガスが用いられる。  The film forming chamber 60 is set to a gas atmosphere containing N, and a first electrode 71 made of titanium is mounted on the first electrode 70, a glass substrate 36 is mounted on the second electrode 72, and a first AC power supply 75 A high frequency having a frequency of about 13.6 MHz is supplied to the first electrode 70 from above, and the load potential applied from the DC power supply 78 is further set to 1200 V, and sputtering is performed. As shown in FIG. Then, a TiN film 45 having a thickness of about 50 nm is formed. As the gas atmosphere containing N, a mixed gas of a gas such as, 、, Ο, NO ′ and an Ar gas is used.
(2 - 2) ゲート電極用金属膜の成膜工程  (2-2) Deposition process of metal film for gate electrode
成膜室 60を Nを含むガス雰囲気から A rガス雰囲気に変更し、 第 1の電極 7 0に装着するターゲット 7 1をチタン、 モリブデン、 クロム、 タンタルのうちか ら選択されていずれかの金属からなるものに変更し、 上記 （1一 1) ゲート電極 用金属の成膜工程と同様の方法により、 図 10 Bに示すように基板 36に形成さ れた T i N膜 45上に膜厚 50 nm程度の金属膜 40 eを形成する。  The film formation chamber 60 is changed from a gas atmosphere containing N to an Ar gas atmosphere, and the target 71 to be mounted on the first electrode 70 is selected from titanium, molybdenum, chromium, and tantalum, and any one of the metals is selected. 10B, the film thickness is formed on the TiN film 45 formed on the substrate 36 as shown in FIG. A metal film 40e of about 50 nm is formed.
(2 - 3) ゲート電極用銅膜の 2周波励起スパッ夕成膜工程  (2-3) Dual frequency excitation sputtering deposition process of copper film for gate electrode
上記 （1— 2) の 2周波励起スパッ夕成膜工程と同様の方法により、 図 1 0 B に示すように金属膜 40 e上に膜厚 1 50 nm程度の銅膜 40 cを成膜して T i N膜 45と金属膜 40 eと銅膜 40 cとからなる積層膜 57を形成する。 このよ うにすると、 上記金属膜 40 e中の元素が銅膜 40 c中に引き込まれる。  A copper film 40c having a thickness of about 150 nm is formed on the metal film 40e as shown in FIG. 10B by a method similar to the dual frequency excitation sputtering film formation step (1-2) described above. Thus, a laminated film 57 including the TiN film 45, the metal film 40e, and the copper film 40c is formed. By doing so, the elements in the metal film 40e are drawn into the copper film 40c.
(2 -4) ゲート電極用 T i N膜及び金属膜及び銅膜のパターニング工程 上記 （1— 3) のパターニング工程と同様の方法により積層膜 57にパター二 ングを施して、 図 10 Cに示すような所望の線幅の T i N層 45 aと金属膜 40 eと銅層 40 aとからなる積層膜を形成する。  (2-4) Patterning step of gate electrode TiN film, metal film and copper film The laminated film 57 is patterned by the same method as the patterning step (1-3) described above, and FIG. A laminated film including the TiN layer 45a, the metal film 40e, and the copper layer 40a having a desired line width as shown is formed.
(2 - 5) 基板 （基体） の第一ァニール工程 T i N層 45 aと金属膜 40 eと銅層 40 aとの積層膜が形成された基板 36 を上記 （ 1一 4) の第一ァニール工程と同様にしてァニール処理し、 上記銅層 4 0 a中に引き込まれた金属膜 40 eの金属元素を上記銅層 40 aの表面に拡散し 、 図 1 0 Dに示すような上記銅層 40 aの周囲にチタン、 モリブデン、 クロム 、 タンタルのうちから選択された金属の被膜 40 bが形成されたゲート電極 40 を得る。 (2-5) First annealing process of substrate (substrate) The substrate 36 on which the laminated film of the TiN layer 45a, the metal film 40e, and the copper layer 40a is formed is annealed in the same manner as in the first annealing step (1-1-4). The metal element of the metal film 40e drawn into the metal layer 40e is diffused to the surface of the copper layer 40a, and titanium, molybdenum, chromium, and tantalum are formed around the copper layer 40a as shown in FIG. 10D. The gate electrode 40 on which the metal film 40b selected from the above is formed is obtained.
なお、 上記 T i N層 45 aはゲート電極 40と基板 36との間に介在されたま まである。  Note that the TiN layer 45a remains interposed between the gate electrode 40 and the substrate 36.
(2 - 6) ゲート絶縁膜 （窒化ケィ素膜） 41の(：¥0成膜ェ程  (2-6) Gate insulating film (silicon nitride film) 41 (: ¥ 0 film formation process)
上記 （ 1— 5) のゲート絶縁膜の CVD成膜工程と同様にして窒化ゲイ素膜を 基板 36上に堆積させる CVD成膜を行ない、 図 1 1 Aに示すようなゲート絶縁 膜 41を形成する。  In the same manner as the above (1-5) CVD film forming process of the gate insulating film, a CVD film forming process is performed to deposit a silicon nitride film on the substrate 36 to form a gate insulating film 41 as shown in FIG. 11A. I do.
(2 - 7) 半導体能動膜 （a - s i層） 42の C VD成膜工程 (2-7) CVD film forming process of semiconductor active film ( a -si layer) 42
上記 （1一 6) の半導体能動膜の CVD成膜工程と同様にしてゲート絶縁膜 4 1上に a— S i層の成膜を行い、 半導体能動膜 42を形成する。  An a-Si layer is formed on the gate insulating film 41 to form the semiconductor active film 42 in the same manner as in the above-mentioned CVD film forming step of the semiconductor active film (1-16).
(2 - 8) ォーミックコンタクト膜 （a— S i ： n+層） 43 aのスパッ夕成膜 工程 (2-8) Ohmic contact film (a—S i: n + layer) 43 a sputter deposition process
上記 （1— 7) のォーミックコンタク ト膜のスパッ夕工程と同様にして半導体 能動膜 42上にォ一ミックコンタクト膜 43 aを形成する。  An ohmic contact film 43a is formed on the semiconductor active film 42 in the same manner as the above (1-7), the ohmic contact film sputtering step.
(2 - 9) 半導体能動膜とォーミックコンタクト膜のパ夕一ニング工程 上記 （1— 8) のパターニング工程と同様にして半導体能動膜 42とォ一ミツ クコンタクト膜 43 aにパ夕一ニングを施して、 図 1 1 Aに示すようにゲート電 極 40よりも小さいアイランド状の半導体能動膜 42とォーミックコン夕ク 卜膜 43 aを得る。  (2-9) Passing process of semiconductor active film and ohmic contact film In the same manner as in the patterning process of (1-8) above, the passivation process of the semiconductor active film 42 and the ohmic contact film 43a is performed. Then, as shown in FIG. 11A, an island-shaped semiconductor active film 42 and an ohmic contact film 43a smaller than the gate electrode 40 are obtained.
(2 - 1 0) ソース電極及びドレイン電極用 T i N膜の成膜工程  (2-10) Deposition process of TIN film for source electrode and drain electrode
成膜室 60を上記 （2— 1) の工程と同様に Nを含むガス雰囲気とし、 第 1の 電極 70にチタンからなる夕一ゲット 7 1を装着し、 第 2の電極 72にはガラス 基板 36を装着したままで、 第 1の交流電源 75から第 1の電極 70に周波数 1 3.6 MHz程度の高周波を供給し、 更に直流電源 78から負荷する負荷電位を -200 Vにしてスパッタリングを行ない、 図 1 1 Aに示すようにォ一ミックコ ン夕ク卜膜 43 aの上面と両側面とその下の半導体能動膜 42の両側面とそれら に連続するゲー卜絶縁膜 41の上面の一部分を覆うように、 膜厚 50 nm程度の T i N膜 47を形成する。 The film formation chamber 60 is set to a gas atmosphere containing N in the same manner as in the above step (2-1), a titanium electrode 71 is attached to the first electrode 70, and a glass substrate is attached to the second electrode 72. With the 36 mounted, a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70, and the load potential applied from the DC power supply 78 is further reduced. Sputtering was performed at -200 V, and as shown in Fig. 11A, the upper surface and both side surfaces of the omnidirectional contact film 43a, the both side surfaces of the semiconductor active film 42 therebelow, and gates continuous to them. A TiN film 47 having a thickness of about 50 nm is formed so as to cover a part of the upper surface of the insulating film 41.
(2 - 1 1 ) ソース電極及びドレイン電極用金属膜の成膜工程  (2-1-1) Deposition process of metal film for source electrode and drain electrode
図 1 1 Aに示すように T i N膜 47上に膜厚 50 nm程度の金属膜 46 eを上 述のゲ一ト電極用金属膜の成膜工程と同様にして形成する。  As shown in FIG. 11A, a metal film 46e having a thickness of about 50 nm is formed on the TiN film 47 in the same manner as the above-described step of forming the gate electrode metal film.
(2 - 1 2) ソース電極及びドレイン電極用銅膜の 2周波励起スパッ夕成膜工程 図 1 1 Aに示すように金属膜 46 e上に膜厚 1 50 nm程度の銅膜 46 cを上 述のゲ一ト電極用銅膜の 2周波励起スパッ夕成膜工程と同様にして形成し、 T i N膜 47と金属膜 46 eと銅膜 46 cとからなる積層膜 58を得る。 このように すると、 上記金属膜 46 e中の元素が銅膜 46 c中に引き込まれる。  (2-1 2) Dual frequency excitation sputtering film formation process of copper film for source electrode and drain electrode As shown in Fig. 11A, a copper film 46c with a thickness of about 150 nm is formed on the metal film 46e. A copper film for a gate electrode is formed in the same manner as in the two-frequency excitation sputtering film forming process to obtain a laminated film 58 including a TiN film 47, a metal film 46e, and a copper film 46c. By doing so, the elements in the metal film 46e are drawn into the copper film 46c.
(2 - 1 3) ソース電極及びドレイン電極用 T i N膜と金属膜及び銅膜と、 半導 体能動膜とォーミックコン夕クト膜のパターニング工程  (2-1-3) Patterning process of TIN film, metal film and copper film for source electrode and drain electrode, semiconductor active film and ohmic contact film
半導体能動膜 42の中央部分の上部をエッチングにより除去し、 半導体能動膜 42の中央部分上のォーミックコンタクト膜 43 aと T i N膜 47と金属膜 43 aと銅膜 46 eを除去することで、 図 1 1 Bに示すように半導体能動膜 42の両 端部分上に相互に離隔したォーミックコンタクト膜 43, 44と、 ソース電極 4 6形成用 T i N層 47 aと金属膜 46 e及び銅層 46 aと、 ドレイン電極 48形 成用 T i N層 47 bと金属膜 46 eと銅層 48 aとを形成することができる。 （ 2 - 14) 基板の第二ァニール工程  The upper portion of the central portion of the semiconductor active film 42 is removed by etching, and the ohmic contact film 43a, the TiN film 47, the metal film 43a, and the copper film 46e on the central portion of the semiconductor active film 42 are removed. As a result, as shown in FIG. 11B, ohmic contact films 43 and 44 which are separated from each other on both ends of the semiconductor active film 42, the TiN layer 47a for forming the source electrode 46 and the metal film 46 e and a copper layer 46 a, a drain electrode 48 forming TiN layer 47 b, a metal film 46 e, and a copper layer 48 a can be formed. (2-14) Second annealing process of substrate
ソース電極 46形成用 T i N層 47 aと金属膜 46 e及び銅層 46 aと、 ドレ ィン電極 48形成用 T i N47 と金属膜 46 eと銅層 48 aとが形成された基 板 36を先に行った基板の第一ァニール工程と同様にしてァニール処理し、 上記 銅層 46 a, 48 a中に引き込まれた金属膜 46 eの金属元素を上記銅層 46 a ， 48 aの表面に拡散し、 図 1 1 Cに示すような銅層 46 a， 48 aの周囲にチ タン、 モリブデン、 クロム、 タンタルのうちから選択された金属の被膜 46 b， 48 bが形成されたソース電極 46とドレイン電極 48が得られる。  A substrate on which a TiN layer 47a for forming a source electrode 46, a metal film 46e, and a copper layer 46a, and a TiN47 for forming a drain electrode 48, a metal film 46e, and a copper layer 48a are formed. 36 is annealed in the same manner as in the first annealing step of the substrate, and the metal element of the metal film 46e drawn into the copper layers 46a and 48a is removed from the copper layers 46a and 48a. A source that diffuses to the surface and has a coating 46b, 48b of a metal selected from titanium, molybdenum, chromium, and tantalum formed around the copper layers 46a, 48a as shown in Figure 11C An electrode 46 and a drain electrode 48 are obtained.
(2 - 1 5) パッシベ一ション膜 49の CVD成膜工程 半導体能動膜 4 2とソース電極 4 6とドレイン電極 4 8を覆うように窒化ケィ 素からなるパッシベーション膜 4 9をゲ一ト絶縁膜 4 1の C V D成膜工程とほぼ 同様にして成膜する。 (2-15) CVD film formation process of passivation film 49 A passivation film 49 made of silicon nitride is formed so as to cover the semiconductor active film 42, the source electrode 46, and the drain electrode 48 in substantially the same manner as the CVD film forming process of the gate insulating film 41.
( 2 - 1 6 ) 画素電極形成工程  (2-16) Pixel electrode formation process
ついで、 パッシベーシヨン膜 4 9を乾式法あるいは乾式法と湿式法の併用によ りエッチングしてコンタク卜ホール 5 0を形成した後、 パッシベ一ション膜 4 9 上に I T O層を形成し、 パターニングすることにより画素電極 3 5を形成し、 図 9に示すようにコンタク 卜ホール 5 0の底面および内壁面、 パッシベーション膜 4 9の上面にかけて接続導体部 5 1を形成し、 この接続導体部 5 1を介してドレ ィン電極 4 8と画素電極 3 5を接続すると、 図 9と同様の薄膜トランジスタ基板 3 1 aが得られる。  Next, after etching the passivation film 49 by a dry method or a combination of a dry method and a wet method to form a contact hole 50, an ITO layer is formed on the passivation film 49 and patterned. To form a connection electrode 51 over the bottom and inner wall of the contact hole 50 and the upper surface of the passivation film 49, as shown in FIG. When the drain electrode 48 and the pixel electrode 35 are connected to each other, a thin film transistor substrate 31a similar to that of FIG. 9 is obtained.
上述のような薄膜トランジスタ基板の製造方法によれば、 図 9に示すような構 造の薄膜トランジスタ基板 3 1 aを製造できる。  According to the method for manufacturing a thin film transistor substrate as described above, a thin film transistor substrate 31a having a structure as shown in FIG. 9 can be manufactured.
なお、 ここでの薄膜トランジスタの製造方法において、 金属膜 4 0 e 、 4 6 e の厚みを変更したり、 基板 3 6をァニール処理する際のァニール温度を 5 0 0 ° C以上とすると、 基板 3 6と各銅層の間の金属膜 4 0 e 、 4 6 eを構成するチタ ンなどの金属元素のほぼ全てを銅層 4 0 a 、 4 6 a , 4 8 aの表面に拡散させる ことができ、 例えば、 図 1 2に示すような銅層 4 0 aの表面に、 チタン原子数に 対する酸素原子数の比が 1対 0乃至 1対 2である組成の被膜 4 0 bを有するよう なゲ一ト電極 4 0や、 図 1 3に示すように銅層 4 0 aの表面に形成されたチタン 膜 4 O mと該チタン膜 4 O mの表面に形成されたチタン原子数に対する酸素原子 数の比が 1対 1乃至 1対 2である組成の膜 4 0 nとを有するようなゲ一ト電極 4 0が得られる。 また、 ソース電極 4 6やドレイン電極 4 8についても、 銅層の表 面にチタン原子数に対する酸素原子数の比が 1対 0乃至 1対 2である組成の被膜 を有するようなものや、 銅層の表面に形成されたチタン膜と該チタン膜の表面に 形成されたチタン原子数に対する酸素原子数の比が 1対 1乃至 1対 2である組成 の膜とを有するようなものが得られる。  In the manufacturing method of the thin film transistor here, if the thickness of the metal films 40 e and 46 e is changed, and if the annealing temperature at the time of annealing the substrate 36 is set to 500 ° C. or more, the substrate 3 Almost all of the metal elements such as titanium constituting the metal film 40 e, 46 e between the copper layer 6 and each copper layer can be diffused to the surface of the copper layers 40 a, 46 a, 48 a. For example, as shown in FIG. 12, a copper layer 40 a has a coating 40 b having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1 to 0 to 1 to 2 on the surface of the copper layer 40 a. As shown in FIG. 13, the gate electrode 40 and the titanium film 4 O m formed on the surface of the copper layer 40 a and the oxygen atoms with respect to the number of titanium atoms formed on the surface of the titanium film 4 O m A gate electrode 40 having a film 40n having a composition in which the number ratio is 1: 1 to 1: 2 is obtained. In addition, the source electrode 46 and the drain electrode 48 also include a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms is 1: 0 to 1: 2 on the surface of the copper layer, A film having a titanium film formed on the surface of the layer and a film having a composition in which the ratio of the number of oxygen atoms to the number of titanium atoms formed on the surface of the titanium film is 1: 1 to 1: 2 is obtained. .
このようにして得られた電極 4 0 、 4 6 、 4 8は、 銅層 4 0 a 、 4 6 a 、 4 8 aの下面側に被膜 4 0 b 、 4 6 b , 4 8 bが設けられていない力 電極 4 0 、 4 6、 4 8と基板 3 6との間に T i N層 4 5 a、 4 7 a、 4 7 bが設けられている ので、 各電極の下側の隣接膜である基板 3 6やゲート絶縁膜 4 1などから元素が 拡散してきても T i N層 4 5 a、 4 7 a、 4 7 bにより電極 4 0 、 4 6 、 4 8へ の原子の拡散が阻害され、 基板 3 6や隣接膜からの元素の拡散に起因する配線抵 抗の上昇の防止効果が優れる。 The electrodes 40, 46, 48 obtained in this way are provided with coatings 40b, 46b, 48b on the lower surface side of the copper layers 40a, 46a, 48a. Not force electrode 4 0, 4 Since the TiN layers 45a, 47a, and 47b are provided between 6, 48 and the substrate 36, the substrate 36, which is the adjacent film below each electrode, and the gate insulation Even if the element diffuses from the film 41 etc., the diffusion of atoms to the electrodes 40, 46, 48 is inhibited by the TiN layers 45 a, 47 a, 47 b, and the substrate 36 or adjacent It has an excellent effect of preventing an increase in wiring resistance due to diffusion of elements from the film.
(第 3実施形態）  (Third embodiment)
次に、 本発明の薄膜トランジスタ基板の第 3実施形態について図 1 4を用いて 説明する。  Next, a third embodiment of the thin film transistor substrate of the present invention will be described with reference to FIG.
第 3実施形態の薄膜トランジスタ基板 3 l bは、 トップゲート型 T F Tを備え たものであり、 図 1 4に示すように、 例えばガラス等の透明基板 1 0 2上に多結 晶シリコンからなる半導体層 1 0 3が形成され、 その中央部上に S i N x等から なるゲート絶縁膜 1 0 4が形成され、 ゲート絶縁膜 1 0 4上に T i N層 1 0 1 a を介してゲート電極 1 0 5が形成されている。 このゲート電極 1 0 5は、 銅層 1 0 5 aの表面に、 第 2実施形態の被膜 4 0 bと同様の材料からなる被膜 1 0 5 b を有してなるものである。 なお、 ゲート電極 1 0 5は図示しないゲート配線と一 体形成されている。 The thin film transistor substrate 3 lb of the third embodiment is provided with a top gate type TFT, and as shown in FIG. 14, for example, a semiconductor layer 1 made of polycrystalline silicon is formed on a transparent substrate 102 such as glass. 0 3 is formed, and a gate insulating film 104 made of SiN x or the like is formed on the central portion thereof. The gate electrode 1 is formed on the gate insulating film 104 via the TiN layer 101 a. 0 5 is formed. The gate electrode 105 has a film 105b made of the same material as the film 40b of the second embodiment on the surface of the copper layer 105a. Note that the gate electrode 105 is formed integrally with a gate wiring (not shown).
半導体層 1 0 3には 1 0 1 K a tm/cm:i以下の低濃度で P A s—等の n型不純物 が導入された n—半導体層からなるソース領域 1 0 7およびドレイン領域 1 0 8 が形成され、 これらソース領域 1 0 7、 ドレイン領域 1 0 8に挟まれた領域がチ ャネル部 1 0 9となっている。 また、 これらソース領域 1 0 7、 ドレイン領域 1 0 8をなす n—半導体層は、 ゲート絶緣膜 1 0 4端部の下方にまで侵入する形で 形成されている。 The semiconductor layer 1 0 to 3 1 0 1 K a tm / cm: the source region i in the following low concentration n-type impurity PA s-like consisting introduced n- semiconductor layer 1 0 7 and the drain region 1 0 8 are formed, and a region sandwiched between the source region 107 and the drain region 108 is a channel portion 109. The n-semiconductor layer forming the source region 107 and the drain region 108 is formed so as to penetrate below the end of the gate insulating film 104.
また、 ソース領域 1 0 7およびドレイン領域 1 0 8表面にはタングステンシリ サイ ド、 モリブデンシリサイ ド等のシリサイド膜 1 1 0がそれぞれ形成されてお り、 一方のシリサイ ド膜 1 1 0上に T i N層 1 2 5 aを介してソース配線 1 1 1 とソース電極 1 1 2が形成され、 他方のシリサイ ド膜 1 1 0上に T i N層 1 2 5 bを介してドレイン電極 1 1 3が形成されている。 これらソース配線 1 1 1、 ソ ース電極 1 1 2は、 銅層 1 1 2 aの表面に第 2実施形態の被膜 4 6 bと同様の材 料からなる被膜 1 1 2 bを有してなるものである。 ドレイン電極 1 1 3は銅層 1 1 3 aの表面に第 2実施形態の被膜 48 と同様の材料からなる被膜 1 1 3 bを 有してなるものである。 Further, silicide films 110 such as tungsten silicide and molybdenum silicide are formed on the surfaces of the source region 107 and the drain region 108, respectively. The source wiring 1 1 1 and the source electrode 1 1 2 are formed via the T i N layer 1 2 5 a, and the drain electrode 1 via the T i N layer 1 2 5 b is formed on the other silicide film 110. 13 are formed. The source wiring 111 and the source electrode 112 have a coating 112 b made of the same material as the coating 46 b of the second embodiment on the surface of the copper layer 112 a. It becomes. Drain electrode 1 1 3 is copper layer 1 On the surface of 13a, a film 113b made of the same material as the film 48 of the second embodiment is provided.
そして、 全面を覆うようにパッシベーシヨン膜 1 14が形成され、 このパッシ ベーション膜 1 14を貫通してドレイン電極 1 1 3に達するコンタク卜ホール 1 1 1 5が形成され、 このコンタク卜ホール 1 1 5を通じてドレイン電極 1 1 3と 接続された I T〇からなる画素電極 1 1 6が形成されている。  Then, a passivation film 114 is formed so as to cover the entire surface, and a contact hole 111 through the passivation film 114 to reach the drain electrode 113 is formed. A pixel electrode 116 made of IT〇 connected to the drain electrode 113 through the drain electrode 113 is formed.
また、 図示を省略するが、 ゲート配線端部のゲート端子部およびソース配線端 部のソース端子部において、 上記コンタク トホール 1 1 5と同様、 ゲート配線お よびソース配線を覆うパッシベーシヨン膜 1 14が開口し、 I TOからなるパッ ドがゲー卜配線およびソース配線に接続してそれぞれ設けられている。  Although not shown, the passivation film 114 covering the gate wiring and the source wiring is opened at the gate terminal at the gate wiring end and at the source terminal at the source wiring end, similarly to the contact hole 115 described above. In addition, a pad composed of an ITO is provided to be connected to the gate wiring and the source wiring, respectively.
第 3実施形態の薄膜トランジスタ基板 3 l bにあっては、 電極や配線を構成す る銅層 1 05 a、 1 1 2 a, 1 1 3 aの表面に被膜 1 05 b、 1 12 b, 1 1 3 bが形成されているので、 水分や酸素に対する耐酸化性を向上でき、 しかもエツ チング剤ゃレジスト剥離液などに対する耐腐食性を向上できる。 またゲート電極 105、 ソース配線 1 1 1およびソース電極 1 1 2、 ドレイン電極 1 1 3と基板 1 02との間にそれぞれ T i N層 1 0 1 a、 1 25 a, 1 25 bが設けられてい るので、 各電極や配線の下側の隣接膜である基板 （基体） 1 02やゲート絶縁膜 104などから元素が拡散してきても T i N層 1 0 1 a、 12 5 a, 125 bに より原子の拡散が阻害され、 基板 102やゲート絶縁膜 1 04などからの元素の 拡散に起因する配線抵抗の上昇の防止効果が優れる。 また、 T i N層 1 0 1 a、 125 a, 12 5 bによって、 ゲート電極 1 05、 ソース配線 1 1 1およびソ一 ス電極 1 12、 ドレイン電極 1 1 3の密着性が向上する。  In the 3 lb thin film transistor substrate according to the third embodiment, a film 105b, 112b, 111 is formed on the surface of the copper layers 105a, 112a, 113a constituting electrodes and wiring. Since 3b is formed, the oxidation resistance to moisture and oxygen can be improved, and the corrosion resistance to an etching agent / resist stripper can be improved. Between the gate electrode 105, the source wiring 1 1 1 and the source electrode 1 1 2 and the drain electrode 1 1 3 and the substrate 102 are provided TiN layers 101a, 125a and 125b, respectively. Therefore, even if the element diffuses from the substrate (base) 102 or the gate insulating film 104 which is an adjacent film below each electrode or wiring, the TiN layer 101 a, 125 a, 125 b Accordingly, diffusion of atoms is hindered, and the effect of preventing an increase in wiring resistance due to diffusion of elements from the substrate 102, the gate insulating film 104, and the like is excellent. Further, the adhesion of the gate electrode 105, the source wiring 111, the source electrode 112, and the drain electrode 113 is improved by the TiN layers 101a, 125a, and 125b.
(実施例 1 )  (Example 1)
図 4ないし図 6に示した薄膜の製造装置を用い、 成膜室 60を A rガス雰囲気 とし、 第 1の電極 70にチタンからなる夕一ゲッ 卜 7 1を装着し、 第 2の電極 7 2に 1辺が 6インチの正方形のガラス基板を装着し、 第 1の交流電源 7 5から第 1の電極 70に周波数 1 3.6 MH ζ程度の高周波を供給し、 更に直流電源 78 から負荷する負荷電位を— 200 Vにしてスパッタリングを行ない、 ガラス基板 上に膜厚 50 nmのチタン膜を形成した。 ついで、 成膜室 6 0を A rガス雰囲気とし、 第 1の電極 7 0に銅からなる夕一 ゲット 7 1を装着し、 第 2の電極 7 2にはガラス基板を装着したままで、 直流電 源 7 8を作動させて直流電力を夕ーゲッ 卜 7 1に印加するとともに第 2の交流電 源 8 0を作動させて交流電力をガラス基板に印加する 2周波励起スパッ夕法によ り、 上記チタン膜上に膜厚 1 5 0 n mの C u膜を形成した。 ここでのガラス基板 に印加する交流電力は、 2 0 0 Wであった。 Using the thin film manufacturing apparatus shown in FIGS. 4 to 6, the film forming chamber 60 was set to an Ar gas atmosphere, and an evening getter 71 made of titanium was attached to the first electrode 70, and the second electrode 7 was made. A 2 inch 6-inch square glass substrate is attached to 2, a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70, and a load is further applied from the DC power supply 78. Sputtering was performed at a potential of -200 V to form a 50-nm-thick titanium film on a glass substrate. Then, the film formation chamber 60 was set to an Ar gas atmosphere, an evening get 71 made of copper was attached to the first electrode 70, and a DC voltage was applied while the glass substrate was attached to the second electrode 72. By operating the power source 78 to apply the DC power to the target 71 and activating the second AC power source 80 to apply the AC power to the glass substrate, the titanium A 150 nm thick Cu film was formed on the film. The AC power applied to the glass substrate here was 200 W.
ついで、 この C u膜の表面にレジストを塗布してパターン露光し、 エッチング 剤により C u膜とチタン膜の不要部分を除去した後に感光性レジストを剥離する パターニングを施して、 チタン膜と C u層の積層膜を形成した。  Next, a resist is applied to the surface of the Cu film, pattern exposure is performed, an unnecessary portion of the Cu film and the titanium film is removed with an etching agent, and then the photosensitive resist is removed. A layer stack was formed.
ついで、 上記の積層膜が形成された基板を窒素ガス雰囲気で 4 0 0 ° C、 2時 間ァニール処理して、 配線を作製した。 この実施例 1で得られた配線の構造をォ ージェ分析法により調べたところ、 銅層の周囲に T iを含有する被膜が形成され た構造のものであり、 また、 銅層上の被膜の厚みは 1 0 n mであった。 また、 実 施例 1の配線の比抵抗を測定したところ、 0 . 2 7 Ω Ζ口であり  Next, the substrate on which the above-mentioned laminated film was formed was subjected to annealing treatment at 400 ° C. for 2 hours in a nitrogen gas atmosphere, thereby producing a wiring. When the structure of the wiring obtained in Example 1 was examined by Auger analysis, it was found to have a structure in which a film containing Ti was formed around the copper layer. The thickness was 10 nm. When the specific resistance of the wiring of Example 1 was measured, it was 0.27 Ω
、 ァニール前後で変化なかった。 , Did not change before and after Anil.
(実施例 2 )  (Example 2)
ガラス基板に印加する交流電力を 1 0 0 Wにした以外は、 上記実施例 1と同様 にして配線を作製した。 この実施例 2で得られた配線の構造をォージェ分析法に より調べたところ、 銅層の周囲に T iを含有する被膜が形成された構造のもので あり、 また、 銅層上の被膜の厚みは 8 n mであった。 また、 実施例 2の配線層の 比抵抗を測定したところ、 0 . 2 3 Ω /口であった。  Wiring was produced in the same manner as in Example 1 except that the AC power applied to the glass substrate was set to 100 W. When the structure of the wiring obtained in Example 2 was examined by Auger analysis, it was found that the film containing Ti was formed around the copper layer. The thickness was 8 nm. Further, the specific resistance of the wiring layer of Example 2 was measured and found to be 0.23 Ω / port.
(比較例 1 )  (Comparative Example 1)
ガラス基板に印加する交流電力を 0 Wにした以外は、 上記実施例 1と同様にし て配線を作製した。 この比較例 1で得られた配線の構造をォージェ分析法により 調べたところ、 銅層の周囲に T iを含有する被膜が形成された構造のものであり 、 また、 銅層上の被膜の厚みは 4 n mであった。 また、 比較例 1の配線の比抵抗 を測定したところ、 0 . 2 3 Ω Ζ口であった。  Wiring was fabricated in the same manner as in Example 1 except that the AC power applied to the glass substrate was set to 0 W. When the structure of the wiring obtained in Comparative Example 1 was examined by Auger analysis, it was found to be a structure in which a film containing Ti was formed around the copper layer, and the thickness of the film on the copper layer Was 4 nm. The specific resistance of the wiring of Comparative Example 1 was measured and found to be 0.23 Ω square.
上記実施例 1 、 2及び比較例 1からガラス基板に印加する交流電力を大きくす るに従って C u層上に形成される被膜の厚みが厚くなることがわかる。 (比較例 2 ) It can be seen from Examples 1 and 2 and Comparative Example 1 that the thickness of the film formed on the Cu layer increases as the AC power applied to the glass substrate increases. (Comparative Example 2)
図 4ないし図 6に示した薄膜の製造装置を用い、 成膜室 6 0を A rガス雰囲気 とし、 第 1の電極 7 0に銅からなる夕一ゲット 7 1を装着し、 第 2の電極 7 2に はガラス基板を装着し、 直流電源 7 8を作動させて直流電力を夕一ゲッ ト 7 1に 印加するとともに第 2の交流電源 8 0を作動させて交流電力をガラス基板に印加 する 2周波励起スパッ夕法により、 膜厚 1 5 0 n mの C u膜を形成した。 ここで のガラス基板に印加する交流電力は、 2 0 0 Wであった。  Using the thin film manufacturing apparatus shown in FIGS. 4 to 6, the film forming chamber 60 was set to an Ar gas atmosphere, and a first electrode 71 made of copper was mounted on the first electrode 70, and the second electrode was A glass substrate is mounted on 72, and a DC power supply 78 is operated to apply DC power to the evening target 71, and a second AC power supply 80 is operated to apply AC power to the glass substrate. A 150 nm-thick Cu film was formed by the dual frequency excitation sputtering method. The AC power applied to the glass substrate here was 200 W.
ついで、 この C u膜の表面にレジストを塗布してパターン露光し、 エッチング 剤により C u膜の不要部分を除去した後に感光性レジストを剥離するパ夕一ニン グを施して、 C u層を形成し、 配線を作製した。 この比較例 2で得られた配線の 比抵抗は、 0 . 2 0 Ω Ζ口であった。  Next, a resist is applied to the surface of the Cu film, pattern exposure is performed, and unnecessary portions of the Cu film are removed with an etching agent, and then the photosensitive resist is peeled off. The wiring was formed. The specific resistance of the wiring obtained in Comparative Example 2 was 0.20 Ω square.
(比較例 3 )  (Comparative Example 3)
ガラス基板に印加する交流電力を 1 0 0 Wにした以外は、 上記比較例 2と同様 にして配線を作製した。 この比較例 3で得られた配線の比抵抗を測定したところ 、 0 . 1 8 Ω /口であった。  Wiring was produced in the same manner as in Comparative Example 2 except that the AC power applied to the glass substrate was set to 100 W. When the specific resistance of the wiring obtained in Comparative Example 3 was measured, it was 0.18 Ω / port.
(実験例 1 ) '  (Experimental example 1) ''
実施例 1 、 2、 比較例 1乃至 3で得られた配線の薬液耐性について調べた。 こ こでの薬液耐性は、 各配線を過硫酸アンモニゥムエッチング液に 6 0秒間浸漬し 、 これらを剥離液から取り出し、 リンス洗浄、 乾燥させたときのエッチング液浸 漬前後の配線の表面の状態を原子力間顕微鏡 （A F M) により観察することによ り評価した。 その結果を図 1 5から図 1 7に示す。 図 1 5は、 過硫酸アンモニゥ ムエッチング液浸漬後の実施例 1の配線の表面の金属組織を示す写真である。 図 1 6は、 過硫酸アンモニゥムエッチング液浸漬後の実施例 2の配線の表面の金属 組織を示す写真である。 図 1 7は、 過硫酸アンモニゥムエッチング液浸漬後の比 較例 1の配線の表面の金属組織を示す写真である。  The chemical resistance of the wirings obtained in Examples 1 and 2 and Comparative Examples 1 to 3 was examined. The chemical resistance here is as follows. Each wiring is immersed in an ammonium persulfate etching solution for 60 seconds, these are removed from the stripping solution, rinsed, and dried. The condition was evaluated by observing it with an atomic force microscope (AFM). The results are shown in FIGS. 15 to 17. FIG. 15 is a photograph showing the metal structure of the wiring surface of Example 1 after immersion in an ammonium persulfate etching solution. FIG. 16 is a photograph showing the metallographic structure of the wiring surface of Example 2 after immersion in an ammonium persulfate etching solution. FIG. 17 is a photograph showing the metal structure of the wiring surface of Comparative Example 1 after immersion in an ammonium persulfate etching solution.
また、 各配線のエッチングレートを測定したところ、 ァニール前の実施例 1の 配線は 1 3 2 n mZ分、 ァニール後の実施例 1の配線は約 3分間の保持時間の後 ァニール前の配線と同様 1 3 2 n m/分、 ァニール前の実施例 2の配線は 1 2 6 n mZ分、 ァニール後の実施例 2の配線は 1分間以上の保持時間の後ァニール前 の配線と同様 1 2 6 n mZ分、 ァニール前の比較例 1の配線は 1 2 8 n m/分、 ァニール後の比較例 1の配線は保持時間は 1分未満で、 その後はァニール前の配 線と同様 1 2 8 n mZ分、 比較例 2の配線は 1 2 7 n mZ分、 比較例 3の配線は 1 2 8 n mZ分であり、 さらに実施例 1と同様のァニールをした後でもエツチン グレートは変わらなかった。 Also, when the etching rate of each wiring was measured, the wiring of Example 1 before annealing was equivalent to 132 nmZ, and the wiring of Example 1 after annealing was compared with the wiring before annealing after a holding time of about 3 minutes. Similarly, 132 nm / min, the wiring of Example 2 before annealing is 12.6 nm mZ, and the wiring of Example 2 after annealing is 1 minute or more after holding time and before annealing. The wiring of Comparative Example 1 before annealing is 128 nm / min, the wiring of Comparative Example 1 after annealing is less than 1 minute, and the wiring before annealing is thereafter As with the wire, the amount of 1 282 n mZ, the wiring of Comparative Example 2 was 1 279 nm mZ, the wiring of Comparative Example 3 was 1 278 n mZ, and even after the same annealing as in Example 1 was performed. Etching Great did not change.
図 1 5乃至図 1 7に示した結果ならびにエッチングレートの測定結果から明ら かなように基板に印加する交流電力が 0 Wの比較例 1の配線や銅層のみ形成した 比較例 2 , 3の配線は、 エッチング液によるエッチングレートがエッチング開始 直後から大きく、 また、 比較例 1の配線は銅膜がほぼ全面に亘つてエッチングさ れており （表面保護率が 7 % ) 、 エッチング液により大きなダメージを受けてい ることがわかる。 これに対して実施例 1 , 2のものは、 約 1分間以上エッチング が進行しない保持時間を有し、 基板に印加する交流電力が 2 0 0 Wの実施例 1の 配線の表面保護率は 9 0 %、 基板に印加する交流電力が 1 0 0 Wの実施例 2の配 線の表面保護率は 6 0 %であり、 エッチング液浸漬前後の配線の表面の状態があ まり変化しておらず、 比較例 1のものに比べて薬液耐性が優れていることがわか る。 なお、 ここでの表面保護率とは、 エッチング液浸漬前の配線の表面積 （ 1 0 0 % ) に対するエッチング液浸漬後に残った表面部分の合計面積の割合である。 また、 実施例し 2の配線においては、 ァニール前後の比抵抗はあまり変化が ない。  As is clear from the results shown in FIGS. 15 to 17 and the measurement results of the etching rate, the AC power applied to the substrate was 0 W, and the wirings and the copper layers of Comparative Example 1 of Comparative Example 1 were formed. The wiring has a large etching rate with the etchant immediately after the start of the etching, and the wiring of Comparative Example 1 has the copper film etched over almost the entire surface (surface protection rate is 7%), and the wiring is greatly damaged by the etching liquid. You can see that they are receiving On the other hand, those of Examples 1 and 2 have a holding time in which the etching does not proceed for about 1 minute or more, and the surface protection ratio of the wiring of Example 1 where the AC power applied to the substrate is 200 W is 9 W The surface protection ratio of the wiring in Example 2 where the AC power applied to the substrate was 0% and the AC power applied to the substrate was 100 W was 60%, and the state of the wiring surface before and after immersion in the etching solution was not significantly changed. However, it is found that the drug solution resistance is superior to that of Comparative Example 1. Here, the surface protection ratio is the ratio of the total area of the surface portion remaining after the immersion in the etching solution to the surface area (100%) of the wiring before the immersion in the etching solution. Further, in the wiring of Example 2, the specific resistance before and after annealing does not change much.
図 1 8乃至図 1 9に、 実施例 1の配線のァニール処理前後の配線構造をォージ ェ分析法より調べた結果を示す。 図 1 8は、 実施例 1の配線のァニール処理前の デプスプロファイルであり、 図 1 9は実施例 1の配線のァニール処理後のデプス プロファイルである。  FIGS. 18 to 19 show the results of the wiring analysis of the wiring of Example 1 before and after the annealing process, using the age analysis method. FIG. 18 shows a depth profile of the wiring of the first embodiment before the annealing process, and FIG. 19 shows a depth profile of the wiring of the first embodiment after the annealing process.
図 1 8乃至図 1 9に示した結果からァニール処理前は、 ガラス基板と C u層の 間の T iの含有量が多く、 C u層中には T iがわずかに含まれており、 また、 C u層表面には殆ど T iが含まれていないことがわかる。 ここで C u層中に T iが 含まれているのは、 C uをスパッ夕成膜する際に基板に交流電力を印加したため であると考えられる。 また、 ァニール処理後は、 ガラス基板と C u層の間の T i の含有量がァニール処理前に比べて少なくなり、 また、 C u層表面側に T i及び Oのピークが認められ、 C u層表面の T iおよび Oがァニール処理前に比べて多 くなつていることがわかる。 これらのことから、 ァニール処理を施すことにより 、 T iが C u層の表面に拡散したことがわかる。 From the results shown in FIGS. 18 to 19, before the annealing treatment, the Ti content between the glass substrate and the Cu layer is large, and the Ti layer contains a small amount of Ti. Further, it can be seen that Ti is hardly contained on the surface of the Cu layer. Here, it is considered that the reason why Ti is included in the Cu layer is that AC power was applied to the substrate when Cu was deposited by sputtering. Also, after the annealing treatment, the Ti content between the glass substrate and the Cu layer becomes smaller than before the annealing treatment, and the Ti and the Ti layer on the surface side of the Cu layer become less. An O peak was observed, indicating that Ti and O on the surface of the Cu layer were larger than before the annealing treatment. From these facts, it can be seen that Ti was diffused to the surface of the Cu layer by performing the annealing treatment.
(実施例 3 )  (Example 3)
チタンからなるターゲット 7 1に代えてクロムからなる夕ーゲット 7 1を用い 、 ガラス基板上にクロム膜を形成した以外は、 上記実施例 1と同様にして配線を 作製した。 また、 実施例 3の配線層の比抵抗を測定したところ、 0. 1 4 ΩΖ口 であった。  A wiring was produced in the same manner as in Example 1 except that a chromium film was formed on a glass substrate using a chromium target 71 instead of the titanium target 71. The specific resistance of the wiring layer of Example 3 was 0.14 Ω / cm.
(実施例 4)  (Example 4)
ガラス基板に印加する交流電力を 1 0 0Wにした以外は、 上記実施例 3と同様 にして配線を作製した。 また、 実施例 4の配線層の比抵抗を測定したところ、 0 . 14 ΩΖ口であった。  Wiring was manufactured in the same manner as in Example 3 except that the AC power applied to the glass substrate was set to 100 W. The specific resistance of the wiring layer of Example 4 was measured and found to be 0.14 Ω.
(比較例 4)  (Comparative Example 4)
ガラス基板に印加する交流電力を 0Wにした以外は、 上記実施例 3と同様にし て配線を作製した。 また、 比較例 1の配線の比抵抗を測定したところ、 0. 14 Wiring was fabricated in the same manner as in Example 3 except that the AC power applied to the glass substrate was set to 0 W. The specific resistance of the wiring of Comparative Example 1 was measured.
ΩΖ口であった。 It was ΩΖ mouth.
(実験例 2 )  (Experimental example 2)
実施例 3、 4、 比較例 4で得られた配線の薬液耐性について上記実験例 1と同 様にして調べた。 その結果を図 20乃至図 22に示す。 図 20は、 過硫酸アンモ ニゥムエッチング液浸漬後の実施例 3の配線の表面の金属組織を示す写真である 。 図 2 1は、 過硫酸アンモニゥムエッチング液浸漬後の実施例 4の配線の表面の 金属組織を示す写真である。 図 22は、 過硫酸アンモニゥムエッチング液浸漬後 の比較例 4の配線の表面の金属組織を示す写真である。  The chemical resistance of the wirings obtained in Examples 3, 4 and Comparative Example 4 was examined in the same manner as in Experimental Example 1 above. The results are shown in FIGS. FIG. 20 is a photograph showing the metallographic structure of the wiring surface of Example 3 after immersion in an ammonium persulfate etching solution. FIG. 21 is a photograph showing the metallographic structure of the wiring surface of Example 4 after immersion in an ammonium persulfate etching solution. FIG. 22 is a photograph showing the metallographic structure of the wiring surface of Comparative Example 4 after immersion in an ammonium persulfate etching solution.
また、 各配線のエッチングレートを測定したところ、 ァニール前の実施例 3の 配線は 1 28 n mZ分、 ァニール後の実施例 3の配線は約 2分間の保持時間の後 ァニール前の配線と同様 1 2 8 nmZ分、 ァニール前の実施例 4の配線は 1 3 1 nmZ分、 ァニール後の実施例 4の配線は 1分間以上の保持時間の後ァニール前 と同様 1 3 1 nmZ分、 ァニール前の比較例 4の配線は 1 27 n mZ分、 ァニ一 ル後の比較例 4の配線は保持時間は 1分未満で、 その後はァニール前の配線と同 様 1 2 7 n mZ分であった。 Also, when the etching rate of each wiring was measured, the wiring of Example 3 before annealing was 128 nmZ, and the wiring of Example 3 after annealing was the same as the wiring before annealing after a holding time of about 2 minutes. The wiring of Example 4 before anneal is 1 2 8 nmZ, the wiring of Example 4 after anneal is the same as that before anneal after the retention time of 1 minute or more. The wiring of Comparative Example 4 was 127 nmZ, the retention time of the wiring of Comparative Example 4 after annealing was less than 1 minute, and the same as the wiring before annealing. It was 127 nmZ minutes.
図 2 0乃至図 2 2に示した結果ならびにエッチングレー卜の測定結果から明ら かなように基板に印加する交流電力が 0 Wの比較例 4の配線や銅層のみ形成した 比較例 2 , 3の配線は、 エッチング液によるエッチングレートがエッチング開始 直後から大きく、 また、 比較例 4の配線は銅膜がほぼ全面に亘つてエッチングさ れており （表面保護率が 1 5 % ) 、 エッチング液により大きなダメージを受けて いることがわかる。 これに対して実施例 3 , 4のものは、 約 1分間以上エツチン グが進行しない保持時間を有し、 基板に印加する交流電力が 2 0 0 Wの実施例 3 の配線の表面保護率は 7 0 %、 基板に印加する交流電力が 1 0 0 Wの実施例 4の 配線の表面保護率は 5 0 %であり、 エッチング液浸漬前後の配線の表面の状態が あまり変化しておらず、 比較例 4のものに比べて薬液耐性が優れていることがわ かる。  As is clear from the results shown in FIGS. 20 to 22 and the measurement results of the etching rate, Comparative Examples 2 and 3 in which only the wiring and the copper layer of Comparative Example 4 in which the AC power applied to the substrate was 0 W were formed. The wiring of Example 4 has a large etching rate with the etchant immediately after the start of the etching, and the wiring of Comparative Example 4 has the copper film etched over almost the entire surface (a surface protection rate of 15%). You can see that it is taking great damage. On the other hand, those of Examples 3 and 4 have a holding time in which etching does not proceed for about 1 minute or more, and the surface protection ratio of the wiring of Example 3 where the AC power applied to the substrate is 200 W is In Example 4 where the AC power applied to the substrate was 100% and the AC power applied to the substrate was 100 W, the wiring surface protection ratio was 50%, and the state of the wiring surface before and after immersion in the etching solution did not change much. It can be seen that the drug solution resistance is superior to that of Comparative Example 4.
また、 実施例 3 , 4の配線においては、 ァニール前後の比抵抗はあまり変化が ない。  In the wirings of Examples 3 and 4, the specific resistance before and after annealing does not change much.
図 2 3乃至図 2 4に、 実施例 3の配線のァニール処理前後の配線構造をォ一ジ ェ分析法より調べた結果を示す。 図 2 3は、 実施例 3の配線のァニール処理前の デプスプロフアイルであり、 図 2 4は実施例 1の配線のァニール処理後のデプス プロファイルである。  FIGS. 23 to 24 show the results of a wiring analysis of the wiring structure of the third embodiment before and after the annealing treatment, by a page analysis method. FIG. 23 shows a depth profile of the wiring of the third embodiment before the annealing process, and FIG. 24 shows a depth profile of the wiring of the first embodiment after the annealing process.
図 2 3乃至図 2 4に示した結果からァニール処理前は、 ガラス基板と C u層の 間の C rの含有量が多く、 C u層中には C rがわずかに含まれており、 また、 C u層表面には殆ど T iが含まれていないことがわかる。 ここで C u層中に T iが 含まれているのは、 C uをスパッ夕成膜する際に基板に交流電力を印加したため であると考えられる。  From the results shown in FIGS. 23 to 24, before the annealing treatment, the Cr content between the glass substrate and the Cu layer was large, and the Cr layer contained a small amount of Cr. Further, it can be seen that Ti is hardly contained on the surface of the Cu layer. Here, it is considered that the reason why Ti is included in the Cu layer is that AC power was applied to the substrate when Cu was deposited by sputtering.
また、 ァニール処理後は、 ガラス基板と C u層の間の C rの含有量がァニール 処理前に比べて少なくなり、 また、 C u層表面側に C r及び 0のピークが認めら れ、 C u層表面の C rおよび〇がァニール処理前に比べて多くなつていることが わかる。 これらのことから、 ァニール処理を施すことにより、 C rが C u層の表 面に拡散したことがわかる。  After the annealing treatment, the Cr content between the glass substrate and the Cu layer was smaller than before the annealing treatment, and the peaks of Cr and 0 were observed on the surface of the Cu layer. It can be seen that Cr and 〇 on the surface of the Cu layer are larger than before the annealing treatment. From these facts, it can be understood that Cr was diffused to the surface of the Cu layer by performing the annealing treatment.
(実験例 3 ) チタンからなる夕ーゲッ 卜 7 1に代えてモリブデンからなる夕ーゲッ卜 7 1を 用い、 また、 ガラス基板に印加する交流電力を 0〜 2 0 0 Wの範囲で変更し、 ガ ラス基板上にモリブデン膜を形成した以外は、 上記実施例 1と同様にして配線を 作製したときの、 C u層上に形成される被膜とガラス基板に印加する交流電力と の関係を調べた。 その結果、 ガラス基板に印加する交流電力が 2 0 0 Wのときに 得られる被膜は、 7 n m、 1 0 0 Wのときに得られる被膜は 6 n m、 0 Wのとき に得られる被膜は 2 n mであった (Experimental example 3) Instead of the titanium target 71, a molybdenum target 71 was used.Also, the AC power applied to the glass substrate was changed in the range of 0 to 200 W, and the molybdenum was set on the glass substrate. The relationship between the film formed on the Cu layer and the AC power applied to the glass substrate was examined when a wiring was produced in the same manner as in Example 1 except that the film was formed. As a result, the film obtained when the AC power applied to the glass substrate was 200 W was 7 nm, the film obtained at 100 W was 6 nm, and the film obtained at 0 W was 2 nm. nm
。 このことからガラス基板に印加する交流電力を大きくするに従って C u層上に 形成されるモリブデンを含む被膜の厚みが厚くなることがわかる。  . This indicates that as the AC power applied to the glass substrate is increased, the thickness of the molybdenum-containing film formed on the Cu layer increases.
(実験例 4 )  (Experimental example 4)
図 4ないし図 6に示した薄膜の製造装置を用い、 成膜室 6 0を と A rガス の混合雰囲気とし、 第 1の電極 7 0にチタンからなる夕ーゲッ ト 7 1を装着し、 第 2の電極 7 2には 1辺が 6ィンチの正方形のガラス基板を装着し、 第 1の交流 電源 7 5から第 1の電極 7 0に周波数 1 3 . 6 MH z程度の高周波を供給し、 更 に直流電源 7 8から負荷する負荷電位を— 2 0 0 Vにしてスパッタリングを行な うことにより膜厚 5 0 n mの T i N膜を成膜した。  Using the thin film manufacturing apparatus shown in FIGS. 4 to 6, the film formation chamber 60 was set to a mixed atmosphere of and Ar gas, the titanium electrode 71 was mounted on the first electrode 70, and the The second electrode 72 is equipped with a square glass substrate having a side of 6 inches, and a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70. Further, a TiN film having a thickness of 50 nm was formed by performing sputtering by setting the load potential applied from the DC power supply 78 to −200 V.
ついで、 成膜室 6 0を A rガス雰囲気とし、 第 1の電極 7 0にチタンからなる 夕一ゲット 7 1を装着し、 第 2の電極 7 2に上記 1辺が 6インチの正方形のガラ ス基板を装着したままで、 第 1の交流電源 7 5から第 1の電極 7 0に周波数 1 3 . 6 MH z程度の高周波を供給し、 更に直流電源 7 8 から負荷する負荷電位を一 2 0 0 Vにしてスパッタリングを行ない、 ガラス基板上に膜厚 2 0 n mのチタン 膜を形成した。  Next, the film forming chamber 60 was set to an Ar gas atmosphere, an evening get 71 made of titanium was attached to the first electrode 70, and the above-mentioned square glass having a side of 6 inches was attached to the second electrode 72. With the circuit board mounted, a high frequency of about 13.6 MHz is supplied from the first AC power supply 75 to the first electrode 70, and the load potential applied from the DC power supply 78 is reduced by one. Sputtering was performed at 00 V to form a 20-nm-thick titanium film on a glass substrate.
ついで、 成膜室 6 0を A rガス雰囲気とし、 第 1の電極 7 0に銅からなる夕一 ゲッ ト 7 1を装着し、 第 2の電極 7 2にはガラス基板を装着したままで、 直流電 源 7 8を作動させて直流電力を夕ーゲッ 卜 7 1に印加するとともに第 2の交流電 源 8 0を作動させて交流電力をガラス基板に印加する 2周波励起スパッ夕法によ り、 上記チタン膜上に膜厚 1 4 0 n mの C u膜を成膜し、 T i N膜とチタン膜と C u膜からなる積層膜を形成した。 ここでのガラス基板に印加する交流電力は、 2 0 0 Wであった。 ついで、 上記の積層膜が形成された基板を窒素ガス雰囲気で 4 0 0 ° C 、 2時 間ァニール処理して、 試験片 1を作製した。 Then, the film formation chamber 60 was set to an Ar gas atmosphere, an evening gate 71 made of copper was attached to the first electrode 70, and a glass substrate was attached to the second electrode 72, The two-frequency excitation sputtering method, in which the DC power source 78 is operated to apply DC power to the target 71 and the second AC power source 80 is operated to apply AC power to the glass substrate, A Cu film having a thickness of 140 nm was formed on the titanium film, and a laminated film including a TiN film, a titanium film, and a Cu film was formed. The AC power applied to the glass substrate here was 200 W. Then, the substrate on which the above-mentioned laminated film was formed was annealed at 400 ° C. for 2 hours in a nitrogen gas atmosphere to prepare a test piece 1.
また、 C u膜の厚みを 1 5 0 n m、 ァニール処理時の温度を 5 0 0 ° Cとした 以外は、 上記の方法と同様にして試験片 2を作製した。  A test piece 2 was prepared in the same manner as described above, except that the thickness of the Cu film was set at 150 nm and the temperature during the annealing treatment was set at 500 ° C.
また、 図 4ないし図 6に示した薄膜の製造装置を用い、 成膜室 6 0を S i H 4 + H 2混合ガス雰囲気とし、 第 1の電極 7 0にダミー夕ーゲット 7 1 aを装着し 、 第 2の電極 7 2にガラス基板 3 6を装着し、 第 1の交流電源 7 5から第 1の電 極 7 0に周波数 2 0 0 M H z程度の高周波を供給し、 更に、 第 2の交流電源 8 0 から第 2の電極 7 2に高周波電力を供給し、 ガラス基板 3 6にかかるイオンエネ ルギーを制御して膜厚 1 0◦ n mの a — S i層 （ i— S i ) を成膜した。 In addition, using the thin film manufacturing apparatus shown in FIGS. 4 to 6, the film forming chamber 60 was set to a mixed gas atmosphere of SiH 4 + H 2 , and the dummy electrode 71 a was mounted on the first electrode 70. Then, a glass substrate 36 is mounted on the second electrode 72, and a high frequency of about 200 MHz is supplied from the first AC power supply 75 to the first electrode 70, and the second RF power is supplied from the AC power supply 80 to the second electrode 72 to control the ion energy applied to the glass substrate 36 to form an a-Si layer (i-Si) having a thickness of 10 ° nm. A film was formed.
ついで、 成膜室 6 0を A rガス雰囲気とし、 第 1の電極 7 0に a— S i ： n一 層生成用の Pドープ S iからなる夕一ゲッ卜 7 1を装着し、 第 1の交流電源 7 5 から第 1の電極 7 0に周波数 1 3 . 6 M H z程度の高周波を供給し、 更に直流電 源 7 8から負荷する負荷電位を— 2 0 0 Vにしてスパッタリングを行ない、 上記 a - S i層上に膜厚 2 0 11 01の21— 5 i ： n†層 （n ナ S i ) を成膜した。 Then, the film forming chamber 60 was set to an Ar gas atmosphere, and an evening gate 71 made of P-doped Si for a-Si: n monolayer formation was mounted on the first electrode 70. A high frequency of about 13.6 MHz is supplied from the AC power supply 75 to the first electrode 70, and the load potential applied from the DC power supply 78 is set to −200 V to perform sputtering. On the a-Si layer, a 21-5i: n † layer (nnna S i) having a film thickness of 201 1 01 was formed.
ついで、 この a — S i ： n +層上に膜厚 5 0 n mの T i N膜を 上記試験片 1と 同様にして成膜し、 さらにこの T i N膜上に膜厚 1 5 0 n mの C u膜を上記試験 片 1と同様にして成膜した。 Then, a 50 nm-thick TiN film was formed on the a-Si: n + layer in the same manner as in the above-mentioned test piece 1, and a 150 nm-thick film was further formed on the TiN film. The Cu film was formed in the same manner as in Test Piece 1 above.
この後、 この基板を窒素ガス雰囲気で 5 0 0 ° (：、 2時間ァニール処理して、 試験片 3を作製した。  Thereafter, this substrate was annealed in a nitrogen gas atmosphere at 500 ° (:, 2 hours) to prepare a test piece 3.
図 2 5乃至図 2 7に、 試験片 1乃至 3の構造をォージェ分析法より調べた結果 を示す。 図 2 5は、 4 0 0 ° Cで 2時間ァニール処理を施した試験片 1のデプス プロファイルであり、 図 2 6は、 5 0 0 ° Cで 2時間ァニール処理を施した試験 片 2のデプスプロファイルであり、 図 2 7は、 5 0 0 ° Cで 2時間ァニール処理 を施した試験片 3のデプスプロファイルである。  FIGS. 25 to 27 show the results of examining the structures of the test pieces 1 to 3 by Auger analysis. Fig. 25 shows the depth profile of test piece 1 subjected to annealing at 400 ° C for 2 hours, and Fig. 26 shows the depth profile of test piece 2 subjected to annealing at 500 ° C for 2 hours. FIG. 27 shows the depth profile of the test piece 3 subjected to annealing at 500 ° C. for 2 hours.
図 2 5乃至図 2 7に示した結果から、 T i N膜と C u膜の間に T i膜を設けて いない試験片 3のものは、 C u膜の表面側に T iのピークがなく、 5 0 (Γ Cで ァニール処理しても C u膜の表面には T iが拡散していないことがわかる。 また 、 C uのピークと S iのピークの間 （C u膜と S i層の間） には、 一◊—で示さ れる Nのピークと、 一△一で示される T iのピークがあり、 また、 Nのピークは 、 T iのピークより大きいが、 それはォージェ分析法では、 Nのピークの近傍に ある T iのピークも検出されてしまうため、 一◊—で示される Nのピークには、 N以外に T iも含まれており、 従って、 Nと T i との含有率はほぼ 1 ： 1である と推定されるため、 C u膜と a— S i ： n+層との間に T i N膜が残存している ことがわかる。 From the results shown in FIG. 25 to FIG. 27, the test piece 3 in which the Ti film was not provided between the TiN film and the Cu film showed a peak of Ti on the surface side of the Cu film. It can be seen that Ti is not diffused to the surface of the Cu film even after annealing at 50 (ΓC. In addition, between the Cu peak and the Si peak (the Cu film and the S between the i-th layer) There is a peak of N and a peak of T i indicated by 1101, and the peak of N is larger than the peak of T i, but it is determined by Auger analysis that the peak of T i is near the peak of N Since peaks are also detected, the peaks of N indicated by a line include Ti in addition to N, and therefore the content ratio of N and T i is estimated to be approximately 1: 1. Therefore, it can be seen that the TiN film remains between the Cu film and the a—Si: n + layer.
T i N膜と C u膜の間に T i膜を設けた試験片 2のものは、 Cu膜の表面側に T iのピークが認められ、 40 (T Cでァニール処理することにより C u膜の表 面に T iが拡散していることがわかる。 また、 Cuのピークと、 ガラス基板中の 〇のピークの間では、 一◊一で示される Nのピークは一△一で示される T iのピ ークより大きいが、 先に述べた同様の理由により、 T i N膜が残存していること がわかる。 なお、 C u膜の表面側に〇のピークが認められるが、 これは Oが T i と反応して、 チタン酸化膜が生成したためである。  In the test piece 2 in which the Ti film was provided between the TiN film and the Cu film, the peak of Ti was observed on the surface side of the Cu film, and 40 (the Cu film was treated by annealing with TC). It can be seen that T i is diffused on the surface of Cu. Also, between the peak of Cu and the peak of の in the glass substrate, the peak of N indicated by the letter T is indicated by the symbol T Although it is larger than the peak of i, it can be seen that the TiN film remains for the same reason as described above, and a peak of 〇 is observed on the surface side of the Cu film. This is because O reacted with T i to form a titanium oxide film.
また、 試験片 3のものは、 試験片 2のものより C u膜の表面側の T iのピーク が大きく、 また、 C uのピークとガラス基板中の〇のピークの間の一△—で示さ れる T iのピークが小さくなつており、 500° Cでァニール処理することによ り、 T i膜を構成する T iの殆どが、 C u膜の表面に拡散したと考えられる。 (実験例 5 )  In addition, the test piece 3 had a larger Ti peak on the surface side of the Cu film than the test piece 2, and also had a peak between the Cu peak and the black peak in the glass substrate. It is considered that most of the Ti constituting the Ti film was diffused to the surface of the Cu film by performing annealing at 500 ° C. because the peak of the indicated Ti was small. (Experimental example 5)
ァニール条件を変更した以外は、 上記試験片 3の作製方法と同様にして試験片 4を作製した。  Specimen 4 was prepared in the same manner as in the preparation of Specimen 3 except that the annealing conditions were changed.
また、 a— S i : η 層上に T i N膜に代えて各種の金属膜 （膜厚 50 nmの T i膜、 膜厚 50 nmの C r膜、 膜厚 50 nmの Mo膜、 膜厚 50 nmの T i N膜 と膜厚 20 nmの T i膜） を形成し、 また、 ァニール条件を変更した以外は、 上 記試験片 3の作製方法と同様にして試験片 5乃至 8を作製した。  Various metal films (Ti film with a thickness of 50 nm, Cr film with a thickness of 50 nm, Mo film with a thickness of 50 nm, film on the a—Si: η layer instead of the TiN film Specimens 5 to 8 were prepared in the same manner as for Specimen 3 except that a 50 nm thick TiN film and a 20 nm thick Ti film were formed, and the annealing conditions were changed. Produced.
そして、 試験片 4乃至試験片 8の積層膜のシート抵抗について調べた。 その結 果を図 28に示す。 図 28中、 横軸はァニール温度 （° C) 、 縦軸の RZR ( i n) はじ u膜のシー卜抵抗値に対する積層膜のシート抵抗値の比である。  Then, the sheet resistance of the laminated films of the test pieces 4 to 8 was examined. Figure 28 shows the results. In FIG. 28, the horizontal axis represents the anneal temperature (° C.), and the vertical axis represents the ratio of the sheet resistance value of the laminated film to the sheet resistance value of the RZR (i n).
図 28の結果から a— S i ： 11+層と（：11膜の間に丁 i膜を設けた試験片 5の ものは、 ァニール温度が 300° Cを超えると膜のシート抵抗が徐々に大きくな り、 ァニール温度が 400° Cでのシート抵抗が C u膜のシート抵抗の約 1. 5 倍で、 500° Cで最もシート抵抗が大きいことわかる。 ここでァニール温度の 上昇によりシート抵抗が大きくなるのは、 温度の上昇により C u膜を構成する C uと、 下地の金属膜の元素が C uと相互拡散し、 C uの中に固溶するためのであ る。 Results a- S i in Figure 28: 11 + layer and (: 11 film Ding i film as the test piece 5 provided between, Aniru temperature gradually exceeds the sheet resistance of the film to 300 ° C Big The sheet resistance at an annealing temperature of 400 ° C is about 1.5 times the sheet resistance of the Cu film, and the sheet resistance is the highest at 500 ° C. Here, the sheet resistance increases with an increase in the annealing temperature because the Cu that forms the Cu film and the element of the underlying metal film interdiffuse with Cu as a result of the rise in temperature, forming a solid solution in Cu. To do so.
これに対して、 a— S i ： n+層と C u膜の間に T i N膜又は Moを設けた試 験片 4、 7のものは、 ァニール温度を変更しても殆どシート抵抗は変化せず、 C u膜と同じ程度の低抵抗の膜であることがわかる。 また、 a— S i ： n†層と C u膜の間に C r膜を設けた試験片 6のものは、 400° Cでのシート抵抗が Cu 膜の抵抗の約 1. 1倍で、 また、 ァニール温度を変更しても殆どシート抵抗は変 化していないことがわかる。 また、 a— S i ： n+層と C u膜の間に T i N膜と T i膜を設けた試験片 8のものは、 ァニ一ル温度が 400° Cでのシート抵抗が (：11膜の約1. 3倍となるが、 500° Cを超えると C u膜と同じ程度の低抵抗 となることがわかる。 On the other hand, in the test pieces 4 and 7 in which the TiN film or Mo was provided between the a-Si: n + layer and the Cu film, the sheet resistance almost changed even when the annealing temperature was changed. However, it can be seen that the film has a resistance as low as that of the Cu film. Moreover, a- S i: n † layer and C u film intended C r specimen 6 having a film between is about 1.1 times the sheet resistance of the resistance of the Cu film in the 400 ° C, Also, it can be seen that the sheet resistance hardly changed even when the annealing temperature was changed. The specimen 8 having a TiN film and a Ti film between the a—Si: n + layer and the Cu film has a sheet resistance of (400 ° C). : About 1.3 times that of the 11 film, but it can be seen that when the temperature exceeds 500 ° C, the resistance becomes as low as the Cu film.
(実験例 6 )  (Experimental example 6)
上記試験片 4乃至 8を 400° Cで 2時間ァニール処理したときの C u膜の下 層の金属膜 （T i N膜、 T i膜、 C r膜、 Mo膜、 T i N膜と T i膜） の拡散状 態についてォージェ分析法により調べた。 結果を以下に述べる。  When the test pieces 4 to 8 were annealed at 400 ° C. for 2 hours, the metal film (TiN film, Ti film, Cr film, Mo film, TiN film and T The diffusion state of the i-film) was investigated by Auger analysis. The results are described below.
試験片 4、 7のものは、 Cu膜の表面には金属膜 （Mo膜、 T i N膜） を構成 する元素は殆ど拡散していないことが分かった。  In the test pieces 4 and 7, it was found that the elements constituting the metal film (Mo film, TiN film) hardly diffused on the surface of the Cu film.
これに対して試験片 5、 6のものは、 C u膜の表面に厚さ 1 0 nm程度のチタ ンの酸化膜やク口ムの酸化膜からなる被膜が形成されていることがわかった。 ま た、 試験片 8のものは、 C u膜の表面に厚さ 10 nm程度のチタンの酸化膜から なる被膜が形成されていることがわかった。  On the other hand, for the test pieces 5 and 6, it was found that a film consisting of a titanium oxide film and a Kumumu oxide film with a thickness of about 10 nm was formed on the surface of the Cu film. . It was also found that the test piece 8 had a film of titanium oxide having a thickness of about 10 nm formed on the surface of the Cu film.
(実験例 7 )  (Experimental example 7)
上記試験片 4乃至 7について a— S i ： n+層と C u膜間に形成された金属膜 のバリヤ一性について評価した。 ここでのバリヤ一性は、 Cu膜に電圧を印加し たときのシート抵抗を測定することにより評価した。 結果を図 29に示す。 図 29に示した結果から a— S i ： n+層と Cu膜間に T i膜や C r膜を設け た試験片 5 、 6は、 ァニール温度が 4 0 0 ° Cを超えると急激にシート抵抗が上 昇していることがわかる。 また、 a— S i ： n +層と C u膜間に M o膜を設けた 試験片 7は、 5 0 0 ° Cまでシート抵抗は殆ど変化せず、 5 0 0 ° Cを超えると 急激に上昇していることがわかる。 ここで急激にシート抵抗が上昇するのは、 ァ ニール温度の上昇により、 メタルシリサイ ド反応により、 a— S i ： n—層と C u膜間の金属膜のバリヤ一性が低下し、 a— S i ： n +層中の S iが拡散して、 C u膜中に入り込むためである。 The test pieces 4 to 7 were evaluated for barrier property of the metal film formed between the a—S i: n + layer and the Cu film. The barrier property here was evaluated by measuring the sheet resistance when a voltage was applied to the Cu film. The results are shown in FIG. From the results shown in Fig. 29, a Ti film or a Cr film was provided between the a-Si: n + layer and the Cu film. It can be seen that the test pieces 5 and 6 showed a sharp rise in sheet resistance when the anneal temperature exceeded 400 ° C. In the test piece 7 in which the Mo film was provided between the a—Si: n + layer and the Cu film, the sheet resistance hardly changed up to 500 ° C., and suddenly exceeded 500 ° C. It can be seen that it has risen. Here, the sheet resistance sharply rises because of the increase in the annealing temperature, the metal silicide reaction causes the barrier property of the metal film between the a—Si: n— layer and the Cu film to decrease, and S i: This is because S i in the n + layer diffuses and enters the Cu film.
これに対して a— S i ： n ÷層と C u膜間に T i N膜を設けた試験片 4は、 ァ ニール温度が 5 0 0 ° Cまでシート抵抗が殆ど変化せず、 また、 5 0 0 ° Cを超 えても試験片 7に比べて緩やかに上昇していることがわかる。 On the other hand, in the test piece 4 having the TiN film between the a— Si : n ÷ layer and the Cu film, the sheet resistance hardly changes until the annealing temperature reaches 500 ° C. It can be seen that even when the temperature exceeds 500 ° C., the temperature rises more slowly than that of the test piece 7.
従って T i N膜は、 T i 、 C r 、 M oに比べて、 耐熱性が優れており、 隣接膜 からの元素の拡散の防止に有効であることがわかる。  Therefore, it can be seen that the TiN film has better heat resistance than Ti, Cr, and Mo, and is effective in preventing the diffusion of elements from the adjacent film.
(実験例 8 )  (Experimental example 8)
ガラス基板と T i膜との間に T i N膜を設けず、 また、 丁 膜上にじリ膜を形 成する前に T i膜の表面にプラズマエッチングを施して T iの酸化層を除去し、 ァニール条件を変更した以外は試験片 1の作製方法と同様にして試験片 9を作製 した。  No TiN film is provided between the glass substrate and the Ti film, and the surface of the Ti film is subjected to plasma etching to form a Ti oxide layer before forming a thin film on the thin film. Specimen 9 was produced in the same manner as in Specimen 1 except that it was removed and the annealing conditions were changed.
ここでのプラズマエッチングは、 成膜室 6 0を A rガス雰囲気とし、 第 1の電 極 7 0にダミー夕ーゲッ ト 7 1 aを装着し、 第 2の電極に T i膜を成膜したガラ ス基板を装着したままで、 第 1の交流電源 7 5から第 1の電源 7 0に高周波を供 給し、 負荷電位をフローティングしてプラズマを発生させるとともに、 第 2の電 極 7 2に高周波電力を供給しガラス基板に 2 0 0 W程度の交流電力を 2分程度印 加することにより行われる。  In this plasma etching, the film formation chamber 60 was set to an Ar gas atmosphere, a dummy electrode 71 a was mounted on the first electrode 70, and a Ti film was formed on the second electrode 70. While the glass substrate is still mounted, high frequency is supplied from the first AC power supply 75 to the first power supply 70 to generate a plasma by floating the load potential, and to the second electrode 72. It is performed by supplying high frequency power and applying AC power of about 200 W to the glass substrate for about 2 minutes.
また、 T i膜の表面にプラズマエッチングを施す際、 ガラス基板に印加する交 流電力を 5 0 W、 1分とした以外は上記試験片 1 0の作製方法と同様にして各種 の試験片 9乃至 1 3を作製した。  When performing plasma etching on the surface of the Ti film, various test pieces were prepared in the same manner as the above-described test piece 10 except that the AC power applied to the glass substrate was set to 50 W for 1 minute. To 13 were produced.
図 3 0に、 ァニール処理前の試験片 9の構造と、 ァニール温度を 2 5 0 ° Cか ら 5 0 0 ° Cの範囲で変更したときの試験片 9の構造をォージェ分析法により調 ベた結果を示す。 また、 図 3 1にァニール処理前の試験片 1 0の構造と、 ァニール温度を 3 0 0 ° Cから 5 0 0 ° Cの範囲で変更したときの試験片 1 0の構造をォージェ分析法 により調べた結果を示す。 Fig. 30 shows the structure of test piece 9 before annealing and the structure of test piece 9 when the annealing temperature was changed in the range of 250 ° C to 500 ° C by Auger analysis. The results are shown below. Fig. 31 shows the structure of test piece 10 before annealing and the structure of test piece 10 when the annealing temperature was changed in the range of 300 ° C to 500 ° C by Auger analysis. The result of the examination is shown.
図 3 0乃至図 3 1の結果からァニール処理前の試験片 1 0は、 C u膜と T i膜 の境界付近に〇のピークが認められ、 T i膜の表面にチタンの酸化膜が生成され ていることがわかる。 また、 T iが C u膜の表面側に拡散し始める温度は 3 5 0 ° Cであり、 さらにァニール温度を高くするに従って、 C u膜の表面側に拡散す る T iの量が増えることがわかる。 これに対してァニール処理前の試験片 9は、 C u膜と T i膜の境界付近に〇のピークが認められないことから、 プラズマエツ チング処理によりチタンの酸化膜が除去されたことがわかる。 また、 T iが C u 膜の表面側に拡散し始める温度は 3 0 0 = Cであり、 試験片 1 0よりも低い温度 で T iが拡散し始めていることがわかる。 従って、 プラズマエッチングにより T i膜表面のチタンの酸化膜を除去することが、 T iを C u膜の表面に拡散させる ためのァニール温度を下げるのに有効であることがわかる。 From the results of FIGS. 30 to 31, the test piece 10 before the annealing treatment showed a peak near the boundary between the Cu film and the Ti film, and a titanium oxide film was formed on the surface of the Ti film. You can see that it has been done. The temperature at which Ti begins to diffuse to the surface of the Cu film is 350 ° C., and as the annealing temperature increases, the amount of Ti diffused to the surface of the Cu film increases. I understand. On the other hand, in the test piece 9 before the annealing treatment, no peak of 〇 was observed near the boundary between the Cu film and the Ti film, indicating that the titanium oxide film was removed by the plasma etching treatment. The temperature at which Ti starts to diffuse to the surface side of the Cu film is 300 = C, which indicates that Ti starts to diffuse at a temperature lower than that of test piece 10. Therefore, it can be seen that removing the titanium oxide film on the Ti film surface by plasma etching is effective in lowering the annealing temperature for diffusing Ti to the Cu film surface.
(実験例 9 )  (Experimental example 9)
T i N膜とガラス基板との間に膜厚 3 0 0 n mの S i〇2膜を 形成し、 T i N 膜と C u膜の間の T i膜の厚みを 1 0 n mから 5 0 n mの範囲で変更し、 さらに ァニール条件を変更以外は、 上記実験例 4の試験片 3とほぼ同様にして試験片 1 1乃至 1 4を作製した。  A 300 nm thick Si〇2 film is formed between the TiN film and the glass substrate, and the thickness of the Ti film between the TiN film and the Cu film is reduced from 10 nm to 50 nm. Test pieces 11 to 14 were prepared in substantially the same manner as test piece 3 of Experimental Example 4 except that the thickness was changed in the range of nm and the annealing conditions were further changed.
そして、 試験片 1 1乃至試験片 1 4の積層膜のシート抵抗について調べた。 そ の結果を図 3 2に示す。 図 3 2中、 横軸はァニール温度 （° C ) 、 縦軸の R Z R ( i n ) は C u膜のシート抵抗値に対する積層膜のシート抵抗値の比である。 図 3 2の結果から S i〇2と C u膜の間に厚さ 5 0 n mの T i N膜と厚さ 3 0 乃至 5 0 n mの T i膜を設けた試験片 1 1乃至 1 2のものは、 ァニ一ル温度が 3 0 0 ° Cを超えると膜のシート抵抗が徐々に大きくなり、 4 0 0 ° Cで最もシ一 卜抵抗が大きくなつていることがわかる。 Then, the sheet resistance of the laminated film of the test pieces 11 to 14 was examined. Figure 32 shows the results. In FIG. 32, the horizontal axis is the anneal temperature (° C.), and the vertical axis is RZR (in), which is the ratio of the sheet resistance of the laminated film to the sheet resistance of the Cu film. From the results shown in Fig. 32, the test pieces 11 to 12 with a 50 nm thick TiN film and a 30 to 50 nm thick Ti film between Si〇2 and the Cu film It can be seen that, when the annealing temperature exceeds 300 ° C., the sheet resistance of the film gradually increases, and the sheet resistance becomes highest at 400 ° C.
これに対して S i と C u膜の間に厚さ 5 0 n mの T i N膜 と厚さ 2 0 n m の T i膜を設けた試験片 1 3のものは、 試験片 1 1乃至 1 2のものよりもシート 抵抗の変化が小さいことがわかる。 また、 S i 0 2と C u膜の間に厚さ 5 0 n mの T i Ν膜と厚さ 1 0 n mの T i膜を設けた試験片 1 4のものは、 ァニール温度を 変更しても殆どシート抵抗は変化していないことがわかる。 On the other hand, the test piece 13 in which a 50 nm thick TiN film and a 20 nm thick Ti film were provided between the Si and Cu films, It can be seen that the change in sheet resistance is smaller than that in the case of 2. In addition, a 50 nm thick It can be seen that the sheet resistance of the test piece 14 provided with a Ti film and a Ti film having a thickness of 10 nm hardly changed even when the annealing temperature was changed.
従って、 T i N膜上に成膜する T i膜の厚みを 2 0 n m以下とすることにより 、 抵抗上昇が少なく、 低抵抗の配線とすることができることがわかる。  Therefore, it can be seen that by setting the thickness of the Ti film formed on the TiN film to 20 nm or less, a wiring having a small resistance rise and a low resistance can be obtained.
以上説明したように本発明によれば、 低抵抗の銅を配線材料として用いる場合 に、 水分や酸素に対する耐酸化性を向上でき、 しかもエッチング剤やレジスト剥 離液などに対する耐腐食性を向上でき、 下地との密着性を向上でき、 さらに隣接 膜との間での元素の相互拡散を防止できる配線とこれを用いた薄膜トランジスタ 基板およびその製造方法と、 そのような薄膜トランジスタ基板を備えた液晶表示 装置を提供できる。  As described above, according to the present invention, when low-resistance copper is used as a wiring material, oxidation resistance to moisture and oxygen can be improved, and corrosion resistance to an etching agent, a resist stripping solution, and the like can be improved. A wiring capable of improving adhesion to a base and preventing interdiffusion of elements between adjacent films, a thin film transistor substrate using the same, a method of manufacturing the same, and a liquid crystal display device having such a thin film transistor substrate Can be provided.

Claims

請求の範囲 The scope of the claims
1 . 銅層の周囲に、 チタンまたはチタン酸化物からなる被膜を有することを特徴 とする配線。  1. A wiring characterized by having a coating made of titanium or titanium oxide around a copper layer.
2 . 銅層の周囲に、 モリブデンまたはモリブデン酸化物からなる被膜を有するこ とを特徴とする配線。  2. Wiring characterized by having a coating made of molybdenum or molybdenum oxide around a copper layer.
3 . 銅層の周囲に、 クロムまたはクロム酸化物からなる被膜を有することを特徴 とする配線。  3. Wiring characterized by having a coating of chromium or chromium oxide around a copper layer.
4 . 銅層の周囲に、 タンタルまたはタンタル酸化物からなる被膜を有することを 特徴とする配線。  4. Wiring characterized by having a coating of tantalum or tantalum oxide around a copper layer.
5 . 前記被膜は、 チタン膜と、 チタン酸化物からなる膜とを有することを特徴と する請求項 1記載の配線。  5. The wiring according to claim 1, wherein the coating has a titanium film and a film made of titanium oxide.
6 . 前記被膜は、 前記銅層の周囲に形成されたチタン膜と該チタン膜の表面に形 成されたチタン酸化物からなる膜とを有することを特徴とする請求項 1記載の配 線。  6. The wiring according to claim 1, wherein the coating has a titanium film formed around the copper layer and a film made of titanium oxide formed on the surface of the titanium film.
7 . 前記被膜は、 前記銅層の周囲の一部に形成されたチタン膜と、 前記銅層の周 囲の残部に形成されたチタン酸化物からなる膜とを有することを特徴とする請求 項 1記載の配線。  7. The film has a titanium film formed on a part of the periphery of the copper layer and a film made of titanium oxide formed on the remaining part of the periphery of the copper layer. The wiring described in 1.
8 . 前記被膜は、 クロム膜と、 クロム酸化物からなる膜とを有することを特徴と する請求項 3記載の配線。  8. The wiring according to claim 3, wherein the coating has a chromium film and a film made of chromium oxide.
9 . 前記被膜は、 前記銅層の周囲に形成されたクロム膜と該クロム膜の表面に形 成されたクロム酸化物からなる膜とを有することを特徴とする請求項 3記載の配 線。  9. The wiring according to claim 3, wherein the coating has a chromium film formed around the copper layer and a film made of chromium oxide formed on the surface of the chromium film.
1 0 . 前記被膜は、 前記銅層の周囲の一部に形成されたクロム膜と、 前記銅層の 周囲の残部に形成されたクロム酸化物からなる膜とを有することを特徴とする請 求項 3記載の配線。  10. The claim, wherein the coating has a chromium film formed on a part of the periphery of the copper layer and a film made of chromium oxide formed on the remaining part of the periphery of the copper layer. The wiring described in item 3.
1 1 . 請求項 1乃至 4のいずれかに記載の配線を有することを特徴とする薄膜ト ランジス夕基板。  11. A thin-film transistor substrate having the wiring according to any one of claims 1 to 4.
1 2 . 基体上に T i N膜を介して請求項 1に記載の配線を設けたことを特徴とす る薄膜トランジスタ基板。 12. A thin-film transistor substrate comprising the wiring according to claim 1 provided on a substrate via a TiN film.
1 3 . 銅層の表面に、 チタンまたはチタン酸化物からなる被膜を有する配線が、 基体上に T i N膜を介して設けられたことを特徴とする薄膜トランジスタ基板。 13. A thin film transistor substrate characterized in that a wiring having a coating made of titanium or titanium oxide is provided on a surface of a copper layer on a substrate via a TiN film.
1 4 . 前記配線の被膜は、 前記銅層の表面に形成されたチタン膜と該チタン膜の 表面に形成されたチタン酸化物からなる膜とを有することを特徴とする請求項 1 3記載の薄膜トランジスタ基板。  14. The wiring according to claim 13, wherein the wiring film includes a titanium film formed on the surface of the copper layer and a film made of titanium oxide formed on the surface of the titanium film. Thin film transistor substrate.
1 5 . チタン、 モリブデン、 クロム、 タンタルのうちから選択されたいずれかの 金属膜を形成した基体の前記金属膜上に、 銅からなる夕ーゲッ 卜を使用して銅膜 を成膜し、 該銅膜と前記金属膜とを所望配線形状にパターニングし、 ついで前記 基体をァニール処理して前記パターニングした銅膜上にチタン、 モリブデン、 ク ロム、 タンタルのうちから選択された金属の被膜を形成することを特徴とする薄 膜トランジスタ基板の製造方法。  15. A copper film is formed on the base metal film on which a metal film selected from titanium, molybdenum, chromium, and tantalum is formed using a copper gate, and The copper film and the metal film are patterned into a desired wiring shape, and then the base is annealed to form a film of a metal selected from titanium, molybdenum, chromium, and tantalum on the patterned copper film. A method for manufacturing a thin film transistor substrate, characterized by comprising:
1 6 . 基体上に T i N膜を成膜し、 ついで前記 T i N膜上にチタンまたはチタン 酸化物からなる膜を成膜し、 ついで前記チタンまたはチタン酸化物からなる膜上 に銅からなる夕ーゲッ 卜を使用して銅膜を成膜して積層膜とし、 該積層膜を所望 配線形状にパターニングし、 ついで前記基体をァニール処理して前記パ夕一ニン グした銅膜上にチタンまたはチタン酸化物からなる被膜を形成することを特徴と する薄膜トランジス夕基板の製造方法。  16. A TiN film is formed on the substrate, a film made of titanium or titanium oxide is formed on the TiN film, and copper is formed on the film made of titanium or titanium oxide. Then, a copper film is formed using a target to form a laminated film, and the laminated film is patterned into a desired wiring shape. Then, the substrate is annealed to form a titanium film on the patterned copper film. Alternatively, a method for producing a thin film transistor substrate, comprising forming a film made of titanium oxide.
1 7 . 前記 T i N膜上に成膜するチタンまたはチタン酸化物からなる膜の膜厚を 1 0 n m乃至 2 0 n mとすることを特徴とする請求項 1 6に記載の薄膜トランジ ス夕基板の製造方法。  17. The thin film transistor according to claim 16, wherein the film made of titanium or titanium oxide formed on the TiN film has a thickness of 10 nm to 20 nm. Substrate manufacturing method.
1 8 . 前記被膜が酸素を含有することを特徴とする請求項 1 5又は 1 6に記載の 薄膜卜ランジス夕基板の製造方法。  18. The method for manufacturing a thin film transistor substrate according to claim 15, wherein the coating contains oxygen.
1 9 . 前記銅膜の成膜前にチタンまたはチタン酸化物からなる膜の表面に生成し たチタンの酸化層を、 プラズマエッチングにより除去することを特徴とする請求 項 1 6記載の薄膜トランジスタ基板の製造方法。  19. The thin film transistor substrate according to claim 16, wherein an oxide layer of titanium formed on the surface of the film made of titanium or titanium oxide before the formation of the copper film is removed by plasma etching. Production method.
2 0 . 対向配置された一対の基板の間に液晶が挟持され、 前記一対の基板の一方 が請求項 1 1又は 1 2又は 1 3に記載の薄膜トランジスタ基板であることを特徴 とする液晶表示装置。  20. A liquid crystal display device, wherein a liquid crystal is sandwiched between a pair of substrates arranged to face each other, and one of the pair of substrates is the thin film transistor substrate according to claim 11 or 12 or 13. .
PCT/JP1999/006877 1998-12-14 1999-12-08 Wiring, thin-film transistor substrate with the wiring, method of manufacture thereof, and liquid crystal display device WO2000036641A1 (en)

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KR1020007008531A KR100399556B1 (en) 1998-12-14 1999-12-08 Wiring, thin-film transistor substrate with the wiring, method of manufacture thereof, and liquid crystal display device
EP99959702.4A EP1063693B1 (en) 1998-12-14 1999-12-08 Method for manufacturing a wiring member on a thin-film transistor substate suitable for a liquid crystal display
US11/100,432 US7804174B2 (en) 1998-12-14 2005-04-07 TFT wiring comprising copper layer coated by metal and metal oxide

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US9178071B2 (en) * 2010-09-13 2015-11-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR20130006999A (en) * 2011-06-28 2013-01-18 삼성디스플레이 주식회사 Thin film transistor and method of manufacturing the same
JP6006558B2 (en) * 2012-07-17 2016-10-12 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
KR20140090019A (en) * 2013-01-08 2014-07-16 삼성디스플레이 주식회사 Display device
CN104882488B (en) * 2015-06-15 2018-03-20 合肥鑫晟光电科技有限公司 Thin film transistor (TFT), array base palte and preparation method thereof, display device
CN106328693B (en) * 2015-06-23 2019-07-05 群创光电股份有限公司 Display panel
CN108735761A (en) * 2017-04-20 2018-11-02 京东方科技集团股份有限公司 Conductive pattern structure and preparation method thereof, array substrate and display device
KR102547313B1 (en) * 2018-04-26 2023-06-23 삼성디스플레이 주식회사 Wiring substrate, display device including the same, and method of manufacturing wiring substrate
US11088078B2 (en) * 2019-05-22 2021-08-10 Nanya Technology Corporation Semiconductor device and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53116089A (en) * 1977-03-22 1978-10-11 Hitachi Ltd Wiring constituent body
JPH03152807A (en) * 1989-11-07 1991-06-28 Casio Comput Co Ltd Structure of wiring layer
JPH0697164A (en) * 1992-09-11 1994-04-08 Mitsubishi Electric Corp Wiring in integrated circuit and structure thereof
JPH07170043A (en) * 1993-12-15 1995-07-04 Matsushita Electric Ind Co Ltd Wiring board
JPH08138461A (en) * 1994-11-02 1996-05-31 Sharp Corp Manufacture of substrate provided with dielectric thin film
JPH10153788A (en) * 1996-11-25 1998-06-09 Toshiba Corp Liquid crystal display device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3784605T2 (en) * 1986-09-17 1993-06-17 Fujitsu Ltd METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE.
US5166085A (en) * 1987-09-09 1992-11-24 Casio Computer Co., Ltd. Method of manufacturing a thin film transistor
US5153754A (en) * 1989-06-30 1992-10-06 General Electric Company Multi-layer address lines for amorphous silicon liquid crystal display devices
US5405655A (en) * 1992-11-19 1995-04-11 Sri International Temperature-resistant and/or nonwetting coatings of cured, silicon-containing polymers
US5831283A (en) * 1995-11-30 1998-11-03 International Business Machines Corporation Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD
JPH10150110A (en) * 1996-11-15 1998-06-02 Semiconductor Energy Lab Co Ltd Semiconductor device
US6956236B1 (en) 1998-12-14 2005-10-18 Lg. Phillips Lcd Co., Ltd. Wiring, TFT substrate using the same and LCD

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53116089A (en) * 1977-03-22 1978-10-11 Hitachi Ltd Wiring constituent body
JPH03152807A (en) * 1989-11-07 1991-06-28 Casio Comput Co Ltd Structure of wiring layer
JPH0697164A (en) * 1992-09-11 1994-04-08 Mitsubishi Electric Corp Wiring in integrated circuit and structure thereof
JPH07170043A (en) * 1993-12-15 1995-07-04 Matsushita Electric Ind Co Ltd Wiring board
JPH08138461A (en) * 1994-11-02 1996-05-31 Sharp Corp Manufacture of substrate provided with dielectric thin film
JPH10153788A (en) * 1996-11-25 1998-06-09 Toshiba Corp Liquid crystal display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1063693A4 *

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7804174B2 (en) 1998-12-14 2010-09-28 Lg Display Co., Ltd. TFT wiring comprising copper layer coated by metal and metal oxide
US6956236B1 (en) 1998-12-14 2005-10-18 Lg. Phillips Lcd Co., Ltd. Wiring, TFT substrate using the same and LCD
KR20020057029A (en) * 2000-12-30 2002-07-11 주식회사 현대 디스플레이 테크놀로지 Method for manufacturing thin film transistor lcd comprising low impedance wiring
JP2002246607A (en) * 2001-02-05 2002-08-30 Samsung Electronics Co Ltd Thin film transistor substrate and its fabricating method
US7102231B2 (en) 2002-09-20 2006-09-05 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US7897973B2 (en) 2002-09-20 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US9082768B2 (en) 2002-09-20 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US9847386B2 (en) 2002-09-20 2017-12-19 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US7585761B2 (en) 2002-09-20 2009-09-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US7781772B2 (en) 2002-09-20 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US9622345B2 (en) 2002-09-20 2017-04-11 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US7417256B2 (en) 2002-09-20 2008-08-26 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US7094684B2 (en) 2002-09-20 2006-08-22 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US8450851B2 (en) 2002-09-20 2013-05-28 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US8749061B2 (en) 2002-09-20 2014-06-10 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US10090373B2 (en) 2002-09-20 2018-10-02 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
JP2009038284A (en) * 2007-08-03 2009-02-19 Mitsubishi Materials Corp Thin film transistor
JP2009043856A (en) * 2007-08-08 2009-02-26 Mitsubishi Materials Corp Thin film transistor
US10096623B2 (en) 2009-02-20 2018-10-09 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, method for manufacturing the same, and semiconductor device
US10586811B2 (en) 2009-02-20 2020-03-10 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, method for manufacturing the same, and semiconductor device
US11824062B2 (en) 2009-02-20 2023-11-21 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, method for manufacturing the same, and semiconductor device
US11011549B2 (en) 2009-02-20 2021-05-18 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, method for manufacturing the same, and semiconductor device
JP2015111688A (en) * 2009-02-20 2015-06-18 株式会社半導体エネルギー研究所 Semiconductor device manufacturing method and semiconductor device
US9859306B2 (en) 2009-02-20 2018-01-02 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, method for manufacturing the same, and semiconductor device
JP2017038093A (en) * 2009-12-04 2017-02-16 株式会社半導体エネルギー研究所 Semiconductor element
JP2018088538A (en) * 2010-12-28 2018-06-07 株式会社半導体エネルギー研究所 Semiconductor device
US10714625B2 (en) 2010-12-28 2020-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US11430896B2 (en) 2010-12-28 2022-08-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2012101994A1 (en) * 2011-01-28 2012-08-02 シャープ株式会社 Method for manufacturing thin-film transistor substrate and thin-film transistor substrate manufactured by this manufacturing method
JP2014527288A (en) * 2011-07-22 2014-10-09 京東方科技集團股▲ふん▼有限公司 Array substrate, manufacturing method thereof, liquid crystal panel, display
US10249764B2 (en) 2012-02-09 2019-04-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device including semiconductor device, electronic device including semiconductor device, and method for manufacturing semiconductor device
JP2016178309A (en) * 2012-02-09 2016-10-06 株式会社半導体エネルギー研究所 Semiconductor device
JP2018019098A (en) * 2012-05-31 2018-02-01 株式会社半導体エネルギー研究所 Semiconductor device
US10483113B2 (en) 2015-12-14 2019-11-19 Sakai Display Products Corporation Wiring board, TFT substrate, method for manufacturing wiring board, and method for manufacturing TFT substrate
WO2017103977A1 (en) * 2015-12-14 2017-06-22 堺ディスプレイプロダクト株式会社 Wiring board, tft substrate, method for manufacturing wiring board, and method for manufacturing tft substrate
TWI671416B (en) * 2017-01-05 2019-09-11 日商愛發科股份有限公司 Deposition method and roll-to-roll deposition apparatus

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US20070102818A1 (en) 2007-05-10
JP4247772B2 (en) 2009-04-02
US6956236B1 (en) 2005-10-18
EP1063693A1 (en) 2000-12-27
EP1063693A4 (en) 2007-06-06
TW452860B (en) 2001-09-01
US7804174B2 (en) 2010-09-28
KR20010040659A (en) 2001-05-15
EP1063693B1 (en) 2016-06-29
KR100399556B1 (en) 2003-10-17

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