WO2000039932A3 - Serial d/a converter - Google Patents

Serial d/a converter Download PDF

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Publication number
WO2000039932A3
WO2000039932A3 PCT/DK1999/000700 DK9900700W WO0039932A3 WO 2000039932 A3 WO2000039932 A3 WO 2000039932A3 DK 9900700 W DK9900700 W DK 9900700W WO 0039932 A3 WO0039932 A3 WO 0039932A3
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
signal
driving
bit
capacitors
Prior art date
Application number
PCT/DK1999/000700
Other languages
French (fr)
Other versions
WO2000039932A2 (en
Inventor
Jesper Steensgaard-Madsen
Original Assignee
Steensgaard Madsen Jesper
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Steensgaard Madsen Jesper filed Critical Steensgaard Madsen Jesper
Priority to US09/609,848 priority Critical patent/US6473011B1/en
Publication of WO2000039932A2 publication Critical patent/WO2000039932A2/en
Publication of WO2000039932A3 publication Critical patent/WO2000039932A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
    • H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
    • H03M1/0673—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using random selection of the elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
    • H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/667—Recirculation type

Abstract

A digital-to-analog converter system (150) based on a symmetrical circuit (152) comprising matched capacitors (104, 106) for pseudo-passive, serial D/A conversion of a digital input signal x(n). Each bit x(n,k) of x(n) is converted by selecting one of the two in each capacitor pair (104, 106) as the driving one, and charging it to plus/minus the reference voltage according to the value of x(n,k). The other capacitor in each capacitor pair (104, 106) stores the previously generated voltage signal representing the bits of x(n) less significant than the bit x(n,k) being processed in the considered cycle k of the serial conversion process. After the driving capacitor has been charged according to x(n,k), the capacitors in each capacitor pair (104, 106) are connected in parallel. Voltage signals representing the bits of x(n) having significance of up to and including x(n,k) is thereby generated on the capacitors (104, 106). Because the circuit (152) is symmetrical, a selector signal t(n,k/i>) may designate arbitrarily which capacitor in each capacitor pair (104, 106) be the driving one, and which be the storing one. The selector signal t(n,k) may attain a new value for the processing of each bit x(n,k). The selector signal t(n,k) is generated such that the error signal induced by mismatch of the matched capacitor pairs (104, 106) will be noise-like and have a reduced power spectral density in the selected signal band. The selector signal t(n,k) is particularly simple to generate if each sample of the input signal x(n) is repeated twice, which it will be when using a popular type of interpolation filters. When each serial conversion cycle is completed, the generated voltage will represent x(n); only then, the capacitor pairs (104, 106) are connected to the driving opamps (118A, 118B).
PCT/DK1999/000700 1998-12-14 1999-12-14 Serial d/a converter WO2000039932A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/609,848 US6473011B1 (en) 1999-08-19 2000-07-05 Serial D/A converter compensating for capacitor mismatch errors

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11250798P 1998-12-14 1998-12-14
US60/112,507 1998-12-14
US14982999P 1999-08-19 1999-08-19
US60/149,829 1999-08-19

Publications (2)

Publication Number Publication Date
WO2000039932A2 WO2000039932A2 (en) 2000-07-06
WO2000039932A3 true WO2000039932A3 (en) 2001-02-22

Family

ID=26810038

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DK1999/000700 WO2000039932A2 (en) 1998-12-14 1999-12-14 Serial d/a converter

Country Status (1)

Country Link
WO (1) WO2000039932A2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906488A (en) * 1974-02-14 1975-09-16 Univ California Reversible analog/digital (digital/analog) converter
US5369403A (en) * 1992-09-01 1994-11-29 The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Dual quantization oversampling digital-to-analog converter
US5389928A (en) * 1990-06-28 1995-02-14 Italtel Societa Italiana Communicazioni, S.P.A. Process for the D/A conversion of signed binary codes of a Bi-polar, time-varying signal and a digital-to-analog converter employing this process
US5406283A (en) * 1992-05-01 1995-04-11 University Of Waterloo Multi-bit oversampled DAC with dynamic element matching
US5724038A (en) * 1995-02-10 1998-03-03 Motorola, Inc. Noise cancelling circuit and arrangement
WO1998048515A1 (en) * 1997-04-18 1998-10-29 Steensgaard Madsen Jesper Oversampled digital-to-analog converter based on nonlinear separation and linear recombination

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906488A (en) * 1974-02-14 1975-09-16 Univ California Reversible analog/digital (digital/analog) converter
US5389928A (en) * 1990-06-28 1995-02-14 Italtel Societa Italiana Communicazioni, S.P.A. Process for the D/A conversion of signed binary codes of a Bi-polar, time-varying signal and a digital-to-analog converter employing this process
US5406283A (en) * 1992-05-01 1995-04-11 University Of Waterloo Multi-bit oversampled DAC with dynamic element matching
US5369403A (en) * 1992-09-01 1994-11-29 The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Dual quantization oversampling digital-to-analog converter
US5724038A (en) * 1995-02-10 1998-03-03 Motorola, Inc. Noise cancelling circuit and arrangement
WO1998048515A1 (en) * 1997-04-18 1998-10-29 Steensgaard Madsen Jesper Oversampled digital-to-analog converter based on nonlinear separation and linear recombination

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
STEENSGAARD J ET AL: "Mismatch-shaping serial digital-to-analog converter", ISCAS'99. PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS VLSI (CAT. NO.99CH36349), ISCAS'99. PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. VLSI, ORLANDO, FL, USA, 30 MAY-2 JUNE 1999, 1999, Piscataway, NJ, USA, IEEE, USA, pages 5 - 8 vol.2, XP002900962, ISBN: 0-7803-5471-0 *

Also Published As

Publication number Publication date
WO2000039932A2 (en) 2000-07-06

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