WO2000052109A1 - Electronic tag assembly and method therefor - Google Patents

Electronic tag assembly and method therefor Download PDF

Info

Publication number
WO2000052109A1
WO2000052109A1 PCT/US2000/005522 US0005522W WO0052109A1 WO 2000052109 A1 WO2000052109 A1 WO 2000052109A1 US 0005522 W US0005522 W US 0005522W WO 0052109 A1 WO0052109 A1 WO 0052109A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
integrated circuit
circuit die
antenna pattern
conductive
Prior art date
Application number
PCT/US2000/005522
Other languages
French (fr)
Inventor
Noel H. Eberhardt
Sean Loving
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Priority to AU37190/00A priority Critical patent/AU3719000A/en
Priority to KR10-2001-7011167A priority patent/KR100460473B1/en
Priority to CA002364448A priority patent/CA2364448C/en
Priority to CN00804478A priority patent/CN1374993A/en
Publication of WO2000052109A1 publication Critical patent/WO2000052109A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07786—Antenna details the antenna being of the HF type, such as a dipole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • This invention relates in general to electronic assemblies, and in particular, to electronic tag assemblies that include the use of an integrated circuit part.
  • assemblies that include an integrated circuit part and a carrier substrate, with an electrical connection therebetween.
  • an electrical interface is established between the integrated circuit die and the carrier substrate, by soldering, wire bonding, electroplating, or by anistropic conductive adhesive.
  • Anistropic conductive adhesives have gained in popularity because of certain identified advantages in the manufacturing process.
  • a typical anistropic conductive adhesive contains metallic or other conductive particles which when compressed between electrical interfaces form a unidirectional electrical bond between the interfaces. Compression may be promoted by bumps or raised portions on one or more of the electrical interfaces.
  • the adhesive must be accurately applied so as to avoid short circuiting closely spaced terminals. Additionally, contact surfaces may need to be specially prepared to promote proper electrical connections.
  • Electronic tag assemblies require a low-cost approach for attaching integrated circuit dies that is suitable for use in high-volume production.
  • the integrated circuit die bonding approaches described in the prior art do not adequately address these needs. Therefore, an improved method for bonding an integrated circuit to form an assembly, such as an electronic tag assembly is needed.
  • FIG. 1 is a plan view of an electronic tag assembly, in accordance with the present invention.
  • FIG. 2 is a cross-sectional view of electronic tag assembly of FIG. 1.
  • FIG. 3 shows a substrate and an integrated circuit die in a pre-assembled stage, in accordance with the present invention.
  • FIG. 4 shows electrical interface terminals on the integrated circuit die in contact with an antenna in the form of a conductive pattern on the substrate, in accordance with the present invention.
  • FIG. 5 shows a non-conductive adhesive being introduced in between the integrated circuit die and the substrate, in accordance with the present invention.
  • FIG. 6 shows the integrated circuit assembly in which the adhesive maintains electrical contact between the electrical interface terminals of the integrated circuit die and the conductive pattern of the substrate, in accordance with the present invention.
  • the present invention provides for an electronic tag assembly suitable for use in high-volume, low-cost applications in which an integrated circuit die is bonded to a substrate using non-conductive adhesive.
  • the integrated circuit die is placed on the substrate such that electrical terminals thereon contact an antenna in the form of a conductive pattern on the substrate.
  • a non-conductive adhesive is introduced in between the circuit die and the substrate, to secure the integrated circuit die to the substrate, and to maintain contact between the electrical conductors and the conductive pattern.
  • a clamping force is exerted on the integrated circuit die to maintain contact between the electrical terminals and the conductive pattern while the non-conductive adhesive is being introduced.
  • FIG. 1 shows a plan view and FIG. 2 shows a cross-sectional view of an electronic tag assembly 100, in accordance with the present invention.
  • the electronic tag assembly 100 is an integrated circuit assembly that includes a chip-type part 108 having communication circuitry thereon, and an electrically coupled antenna 104, 106.
  • the chip-type part 108 is a semiconductor die formed using a standard manufacturing process.
  • the die 108 has electrical interface terminals in the form of raised electrical conductors 204, 206 or bumps that function as electrical interface contacts.
  • the antenna 104, 106 is implemented on a substrate 102, preferably formed from fibrous material, such as paper or cloth, plastic, or other inexpensive material.
  • the antenna 104, 106 is formed as a pattern of two spaced apart deposits of conductive material.
  • Preferred conductive materials include carbon ink, carbon filled polymer, or other materials suitable for low cost applications.
  • the conductive pattern may be printed, painted, or otherwise disposed on the substrate in a low cost manner.
  • the conductive pattern and the electrical interface conductors are devoid of transitional elements.
  • the integrated circuit die 108 is adhesively affixed to the substrate 102 using an electrically non-conductive adhesive 202.
  • the electrical interface contacts 204, 206 protrude from the integrated circuit die 108 and directly contact or interface with the conductive pattern 104, 106 on the substrate 102.
  • the electrically non-conductive adhesive 202 is interposed between the integrated circuit die 108 and the substrate 102, and makes direct contact therewith. The adhesive 202 secures the integrated circuit die 108 to the substrate 102, and maintains electrical contact between the electrical conductors 204, 206 and the conductive pattern 104, 106.
  • FIGs. 3,4,5, and 6 show the electronic tag assembly 100 in various stages of construction, in accordance with the present invention.
  • the antenna or conductive pattern 104, 106 is printed on or otherwise disposed on the substrate, and the integrated circuit die 108 is separately prepared, such as by using a standard manufacturing process.
  • the integrated circuit die 108 and the substrate 102 are brought together such that contact is established between the electrical conductors 204, 206 on the die 108, and the conductive pattern 104, 106 on the substrate 102.
  • a clamping force is applied to maintain contact between the electrical conductors 204, 206 and the conductive pattern 104, 106.
  • the integrated circuit die 108 is held in place by the clamping force, while an adhesive dispensing needle 502 is positioned in between the die 108 and the substrate 102, and an adhesive dispensed.
  • the clamping force is maintained while the adhesive cures.
  • contact between the electrical conductors 204, 206 and the conductive pattern 104, 106 is maintained by the adhesive 602, see FIG. 6.
  • the present invention provides for significant advantages over the prior art.
  • An electronic tag assembly suitable for high- volume, low-cost applications is provided without the use of expensive anistropic adhesives, and without the use of special materials and processes that add substantial expense or complexity.

Abstract

An electronic tag assembly (100) includes a substrate (102) having an antenna pattern (140, 106) disposed thereon, an integrated circuit die (108) having electrical interface terminals (204, 206) that directly contact or interface with the antenna pattern (104, 106), and electrically non-conductive adhesive (202) interposed between the substrate and the integrated circuit die (108) that secures both together, and that maintains the integrity of the electrical interface. Preferably, a clamping force is exerted on the integrated circuit die (108) to maintain contact between the electrical terminals (204, 206) and the antenna pattern (104, 106) while the non-conductive adhesive (202) is being introduced.

Description

ELECTRONIC TAG ASSEMBLY AND METHOD THEREFOR
Technical Field
This invention relates in general to electronic assemblies, and in particular, to electronic tag assemblies that include the use of an integrated circuit part.
Background of Invention
In electronic applications, there is often a need to form assemblies that include an integrated circuit part and a carrier substrate, with an electrical connection therebetween. Oftentimes, an electrical interface is established between the integrated circuit die and the carrier substrate, by soldering, wire bonding, electroplating, or by anistropic conductive adhesive. Each of these prior art approaches has its own advantages and disadvantages including suitability for use with specific types of parts and manufacturing processes, assembly costs, and the like.
Anistropic conductive adhesives have gained in popularity because of certain identified advantages in the manufacturing process. A typical anistropic conductive adhesive contains metallic or other conductive particles which when compressed between electrical interfaces form a unidirectional electrical bond between the interfaces. Compression may be promoted by bumps or raised portions on one or more of the electrical interfaces. There are certain manufacturing difficulties involved when using conductive adhesives with small dimension parts. For example, the adhesive must be accurately applied so as to avoid short circuiting closely spaced terminals. Additionally, contact surfaces may need to be specially prepared to promote proper electrical connections. These and other costs disadvantages have limited the use of conductive adhesive for bonding integrated circuit dies to carrier substrates.
Electronic tag assemblies require a low-cost approach for attaching integrated circuit dies that is suitable for use in high-volume production. The integrated circuit die bonding approaches described in the prior art do not adequately address these needs. Therefore, an improved method for bonding an integrated circuit to form an assembly, such as an electronic tag assembly is needed.
Brief Description of the Drawings
FIG. 1 is a plan view of an electronic tag assembly, in accordance with the present invention.
FIG. 2 is a cross-sectional view of electronic tag assembly of FIG. 1.
FIG. 3 shows a substrate and an integrated circuit die in a pre-assembled stage, in accordance with the present invention.
FIG. 4 shows electrical interface terminals on the integrated circuit die in contact with an antenna in the form of a conductive pattern on the substrate, in accordance with the present invention.
FIG. 5 shows a non-conductive adhesive being introduced in between the integrated circuit die and the substrate, in accordance with the present invention.
FIG. 6 shows the integrated circuit assembly in which the adhesive maintains electrical contact between the electrical interface terminals of the integrated circuit die and the conductive pattern of the substrate, in accordance with the present invention.
Detailed Description of the Preferred Embodiment
The present invention provides for an electronic tag assembly suitable for use in high-volume, low-cost applications in which an integrated circuit die is bonded to a substrate using non-conductive adhesive. The integrated circuit die is placed on the substrate such that electrical terminals thereon contact an antenna in the form of a conductive pattern on the substrate. While maintaining contact between the electrical terminals and the conductive pattern, a non-conductive adhesive is introduced in between the circuit die and the substrate, to secure the integrated circuit die to the substrate, and to maintain contact between the electrical conductors and the conductive pattern. Preferably, a clamping force is exerted on the integrated circuit die to maintain contact between the electrical terminals and the conductive pattern while the non-conductive adhesive is being introduced.
FIG. 1 shows a plan view and FIG. 2 shows a cross-sectional view of an electronic tag assembly 100, in accordance with the present invention. The electronic tag assembly 100 is an integrated circuit assembly that includes a chip-type part 108 having communication circuitry thereon, and an electrically coupled antenna 104, 106. The chip-type part 108 is a semiconductor die formed using a standard manufacturing process. Preferably, the die 108 has electrical interface terminals in the form of raised electrical conductors 204, 206 or bumps that function as electrical interface contacts.
In the preferred embodiment, the antenna 104, 106 is implemented on a substrate 102, preferably formed from fibrous material, such as paper or cloth, plastic, or other inexpensive material. The antenna 104, 106 is formed as a pattern of two spaced apart deposits of conductive material. Preferred conductive materials include carbon ink, carbon filled polymer, or other materials suitable for low cost applications. The conductive pattern may be printed, painted, or otherwise disposed on the substrate in a low cost manner. In the preferred embodiment, the conductive pattern and the electrical interface conductors are devoid of transitional elements.
The integrated circuit die 108 is adhesively affixed to the substrate 102 using an electrically non-conductive adhesive 202. The electrical interface contacts 204, 206 protrude from the integrated circuit die 108 and directly contact or interface with the conductive pattern 104, 106 on the substrate 102. The electrically non-conductive adhesive 202 is interposed between the integrated circuit die 108 and the substrate 102, and makes direct contact therewith. The adhesive 202 secures the integrated circuit die 108 to the substrate 102, and maintains electrical contact between the electrical conductors 204, 206 and the conductive pattern 104, 106.
FIGs. 3,4,5, and 6 show the electronic tag assembly 100 in various stages of construction, in accordance with the present invention. With reference to FIG. 3, the antenna or conductive pattern 104, 106 is printed on or otherwise disposed on the substrate, and the integrated circuit die 108 is separately prepared, such as by using a standard manufacturing process. With reference to FIG. 4, the integrated circuit die 108 and the substrate 102 are brought together such that contact is established between the electrical conductors 204, 206 on the die 108, and the conductive pattern 104, 106 on the substrate 102. A clamping force is applied to maintain contact between the electrical conductors 204, 206 and the conductive pattern 104, 106.
With reference to FIG. 5, while maintaining contact between the electrical conductors 204, 206 and conductive pattern 104, 106, and non-conductive adhesive is introduced in between the integrated circuit die 108 and the substrate 102. Preferably, the integrated circuit die 108 is held in place by the clamping force, while an adhesive dispensing needle 502 is positioned in between the die 108 and the substrate 102, and an adhesive dispensed. The clamping force is maintained while the adhesive cures. When such clamping force is removed, contact between the electrical conductors 204, 206 and the conductive pattern 104, 106 is maintained by the adhesive 602, see FIG. 6.
The present invention provides for significant advantages over the prior art. An electronic tag assembly suitable for high- volume, low-cost applications is provided without the use of expensive anistropic adhesives, and without the use of special materials and processes that add substantial expense or complexity. By establishing direct electrical contact between the integrated circuit die terminals and the antenna pattern, and by using an
electrically non-conductive adhesive to maintain such contact, an inexpensive manufacturing process is provided. What is claimed is:

Claims

Claims
1. A method of forming an integrated circuit assembly, comprising the steps of: bringing together an integrated circuit die, having electrical terminals thereon, and a substrate, having an antenna pattern thereon, such that contact is established between the electrical terminals and the antenna pattern; establishing direct contact between electrical terminals and the antenna pattern; introducing an electrically non-conductive adhesive in between the integrated circuit die and the substrate; and maintaining direct contact between the electrical terminals and the antenna pattern using the electrically non-conductive adhesive.
2. The method of claim 1, further comprising the step of printing the antenna pattern on the substrate.
3. The method of claim 2, wherein the step of printing comprises the step of printing a conductive pattern using carbon containing material.
4. The method of claim 3, wherein the step of printing comprises the step of printing the conductive pattern on paper.
5. A method of forming an electronic tag assembly, comprising in order the steps of:
(a) placing an integrated circuit die on a substrate such that electrical conductors on the integrated circuit die contact an antenna pattern disposed on the substrate; and
(b) while maintaining contact between the electrical conductors and the antenna pattern, introducing an adhesive in between the integrated circuit die and the substrate to secure the integrated circuit die to the substrate, and to secure contact between the electrical conductors and the antenna pattern.
6. The method of claim 5, wherein the adhesive consists of electrically non- conductive adhesive.
7. The method of claim 5, wherein step (b) comprises the step of disposing the adhesive to contact the integrated circuit die and the antenna pattern to form a bond therebetween.
8. The method of claim 5, wherein the substrate is formed from paper, and further comprising the step of printing the antenna pattern on the paper.
9. An electronic tag, comprising: a substrate; an antenna comprising first and second spaced apart conductive patterns formed on the substrate; an integrated circuit die having first and second electrical interface conductors projecting therefrom, that directly interface with the first and second spaced apart conductive patterns, respectively; and electrically non-conductive adhesive interposed around the first and second electrical interface conductors, and on the first and second spaced apart conductive patterns, which electrically non-conductive adhesive secures the integrated circuit die to the substrate.
10. The electronic tag of claim 9, wherein the substrate is formed from fibrous material, and conductive pattern comprises conductive ink disposed thereon.
PCT/US2000/005522 1999-03-02 2000-03-02 Electronic tag assembly and method therefor WO2000052109A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU37190/00A AU3719000A (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor
KR10-2001-7011167A KR100460473B1 (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor
CA002364448A CA2364448C (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor
CN00804478A CN1374993A (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12254799P 1999-03-02 1999-03-02
US60/122,547 1999-03-02

Publications (1)

Publication Number Publication Date
WO2000052109A1 true WO2000052109A1 (en) 2000-09-08

Family

ID=22403347

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/005522 WO2000052109A1 (en) 1999-03-02 2000-03-02 Electronic tag assembly and method therefor

Country Status (5)

Country Link
KR (1) KR100460473B1 (en)
CN (1) CN1374993A (en)
AU (1) AU3719000A (en)
CA (1) CA2364448C (en)
WO (1) WO2000052109A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2828570A1 (en) * 2001-08-09 2003-02-14 Cybernetix Production of a contact-less chip support comprises laminating an insulating film on a micro-module film, laminating an adhesive film on the micro-module film, cutting the micro-module and applying an antenna to each micro-module
WO2005076353A2 (en) * 2004-01-30 2005-08-18 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
EP1584125A2 (en) * 2002-12-31 2005-10-12 Avery Dennison Corporation Organisation Rfid device and method of forming
US7224280B2 (en) 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
CN100417038C (en) * 2002-08-28 2008-09-03 株式会社日立制作所 Input device usable as electronic label
US7559486B2 (en) 2001-08-17 2009-07-14 Alien Technology Corporation Apparatuses and methods for forming wireless RF labels
GB2435183B (en) * 2004-11-02 2009-12-02 Precisia L L C Variation of conductive cross section or material to enchance performance and reduce material comsumption of electronic assemblies
US8912907B2 (en) 2003-03-24 2014-12-16 Alien Technology, Llc RFID tags and processes for producing RFID tags
US9070063B2 (en) 2004-11-22 2015-06-30 Ruizhang Technology Limited Company Radio frequency identification (RFID) tag for an item having a conductive layer included or attached

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006068286A1 (en) * 2004-12-24 2006-06-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2007108894A (en) * 2005-10-12 2007-04-26 Brother Ind Ltd Tag tape roll-manufacturing device and tag tape roll-manufacturing method
JP4915323B2 (en) * 2006-11-28 2012-04-11 ブラザー工業株式会社 Wireless tag information communication device
DE102011009577A1 (en) * 2011-01-27 2012-08-02 Texas Instruments Deutschland Gmbh RFID transponder and method for connecting a semiconductor die to an antenna

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
US6002343A (en) * 1996-10-28 1999-12-14 Hi-G-Tek Ltd. Changing Indicia in an electronic tag when tampered with
US6018299A (en) * 1998-06-09 2000-01-25 Motorola, Inc. Radio frequency identification tag having a printed antenna and method
US6055724A (en) * 1997-02-04 2000-05-02 Matsushita Electric Industrial Co., Ltd. Method and device for sealing IC chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2769389B1 (en) * 1997-10-07 2000-01-28 Rue Cartes Et Systemes De MICROCIRCUIT CARD COMBINING EXTERIOR CONTACT RANGES AND AN ANTENNA, AND METHOD FOR MANUFACTURING SUCH A CARD

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
US6002343A (en) * 1996-10-28 1999-12-14 Hi-G-Tek Ltd. Changing Indicia in an electronic tag when tampered with
US6055724A (en) * 1997-02-04 2000-05-02 Matsushita Electric Industrial Co., Ltd. Method and device for sealing IC chip
US6018299A (en) * 1998-06-09 2000-01-25 Motorola, Inc. Radio frequency identification tag having a printed antenna and method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2828570A1 (en) * 2001-08-09 2003-02-14 Cybernetix Production of a contact-less chip support comprises laminating an insulating film on a micro-module film, laminating an adhesive film on the micro-module film, cutting the micro-module and applying an antenna to each micro-module
US7559486B2 (en) 2001-08-17 2009-07-14 Alien Technology Corporation Apparatuses and methods for forming wireless RF labels
CN100417038C (en) * 2002-08-28 2008-09-03 株式会社日立制作所 Input device usable as electronic label
US8072333B2 (en) 2002-12-31 2011-12-06 Avery Dennison Corporation RFID device and method of forming
EP1584125A4 (en) * 2002-12-31 2006-12-27 Avery Dennison Corp Organisati Rfid device and method of forming
US7224280B2 (en) 2002-12-31 2007-05-29 Avery Dennison Corporation RFID device and method of forming
EP1584125A2 (en) * 2002-12-31 2005-10-12 Avery Dennison Corporation Organisation Rfid device and method of forming
US8912907B2 (en) 2003-03-24 2014-12-16 Alien Technology, Llc RFID tags and processes for producing RFID tags
US9418328B2 (en) 2003-03-24 2016-08-16 Ruizhang Technology Limited Company RFID tags and processes for producing RFID tags
WO2005076353A3 (en) * 2004-01-30 2006-02-02 Alien Technology Corp Apparatus incorporating small-feature-size and large-feature-size components and method for making same
WO2005076353A2 (en) * 2004-01-30 2005-08-18 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
GB2435183B (en) * 2004-11-02 2009-12-02 Precisia L L C Variation of conductive cross section or material to enchance performance and reduce material comsumption of electronic assemblies
US9070063B2 (en) 2004-11-22 2015-06-30 Ruizhang Technology Limited Company Radio frequency identification (RFID) tag for an item having a conductive layer included or attached

Also Published As

Publication number Publication date
CA2364448C (en) 2004-10-26
KR100460473B1 (en) 2004-12-08
CA2364448A1 (en) 2000-09-08
CN1374993A (en) 2002-10-16
KR20010102475A (en) 2001-11-15
AU3719000A (en) 2000-09-21

Similar Documents

Publication Publication Date Title
CA2364448C (en) Electronic tag assembly and method therefor
US20040183182A1 (en) Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US6008993A (en) Chip card with chip support element and coil support element
CN1295646C (en) Method for connecting chip to antenna of radio frequency identification device of contactless chip card variety
US4970624A (en) Electronic device employing a conductive adhesive
US6911606B2 (en) Electronic component for adhesion of a plurality of electrodes and method of mounting the same
US6580369B1 (en) Electronic tag assembly and method therefor
US20010006118A1 (en) Non-contact type IC card and process for manufacturing same
US6281048B1 (en) Method of making an electronic component, and an electronic component
US7431218B2 (en) RFID tag, module component, and RFID tag fabrication method
US6559523B2 (en) Device for attaching a semiconductor chip to a chip carrier
JPH04259104A (en) Small sized oscillator
JP3891743B2 (en) Manufacturing method of semiconductor component mounted component, manufacturing method of semiconductor component mounted finished product, and finished semiconductor component mounted product
US20070159341A1 (en) Packaging structure for radio frequency identification devices
MX2008012339A (en) Methods for attaching a flip chip integrated circuit assembly to a substrate.
JPH0878599A (en) Integrated circuit package and manufacture thereof
JP2004062634A (en) Connectless communication device and method for connecting the same
JPH01196844A (en) Mounting method for electronic component
JP2002259923A (en) Non-contact ic card and producing method thereof
JPH0747900Y2 (en) Wiring board
JP3040682U (en) Printed circuit
JPH11126964A (en) Flexible circuit board with anisotropic conductive adhesive and its manufacture
JP2000123888A (en) Connecting method of lead wire to film base board
TH63893A (en) The process of producing transponder for contactlee chip card
JPH0461150A (en) Connecting method of terminal to printed wiring board

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 00804478.3

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref document number: 2364448

Country of ref document: CA

Ref document number: 2364448

Country of ref document: CA

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020017011167

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020017011167

Country of ref document: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
WWG Wipo information: grant in national office

Ref document number: 1020017011167

Country of ref document: KR