WO2000052567A1

WO2000052567A1 - System for transmitting data records that are divided into a plurality of words

Info

Publication number: WO2000052567A1
Application number: PCT/DE2000/000663
Authority: WO
Inventors: Jürgen BERMANN; Jörg Mensinger; Harald Raab
Original assignee: Siemens Aktiengesellschaft
Priority date: 1999-03-02
Filing date: 2000-03-02
Publication date: 2000-09-08
Also published as: DE19909081A1; DE19909081C2

Abstract

The invention relates to a system for transmitting data records that are divided into a plurality of words between two control units (5, 20). The inventive system comprises a memory configuration having a first memory (A) and a second memory (B) which can be accessed by at least one control device. The data records are consistently copied from one memory (A; B) into the other memory (B; A) by a copying unit (S2). A synchronization logic unit (SL) ensures collision-free access. As a result, it is possible to obtain a consistent transmission of data records without mutually influencing the processes running on the control units. The invention is used in data interfaces between different control units.

Description

description

Arrangement for the transmission of data records divided into several words

The invention relates to an arrangement for the transmission of data records divided into several words between two control units with a memory arrangement according to the preamble of claim 1.

Such an arrangement is already known from EP 0 377 886 A2. For decoupling data paths of different widths and transmission speeds, a buffer memory is used, in which the data to be transmitted are written and read out, controlled by a synchronization unit. Both control units can have read and / or write access to the buffer memory. The synchronization unit prevents the case in which one control unit has only partially written a data record and the other control unit has subsequently written the entire one

Retrieves the data record before the first unit was able to completely write the data record. The second control unit was then received a corrupt data record. Accordingly, an error would occur if one control unit would retrieve some words of a data record from a memory area of the buffer memory and the other unit would enter the complete data record in the same memory area before the first control unit could completely retrieve the words of the data record. If one control unit wants to write a data record into the buffer memory or read it from it, it first checks to synchronize the accesses whether it accesses the same address range as the other control unit. The address range includes such a number of addresses as is required to record the words of a data record. The address area is compared with the address area of the access of the other control unit stored in a register and checked whether the address ranges match. As long as there is a match, the other control unit has exclusive access to the buffer memory. One control unit must therefore wait until the other control unit has read out or written in the complete data record. This ensures data consistency. This means that it is ensured that data records are always exchanged in a continuous manner between the two control units.

This arrangement for the transmission of data sets presupposes that both control units have a deterministic behavior. Such behavior of the control is required, for example, in automation systems. To ensure that a process is operated correctly and a malfunction can be reacted to sufficiently quickly, orders are processed cyclically by control units in automation technology. If one of the two control units is implemented by a fieldbus controller, in particular a PROFIBUS DP master, to which a decentralized periphery consisting of sensors and actuators is connected via the fieldbus, the buffer memory must be accessed cyclically. The PROFIBUS DP master reads out new output data from the buffer memory and forwards it to the connected distributed I / O via the PROFIBUS. It receives new input information from the sensors operated as PROFIBUS DP slaves, which it stores in the buffer memory. The input data are read from the buffer memory by another control unit, necessary interventions in the process are determined therefrom and the corresponding output data are written into the buffer memory. In the event that a control system fails, an intrinsically safe state is usually provided in automation systems, in which all motors are stopped, for example, in the case of a belt control system. To detect such an error, actuators operated as PROFIBUS DP slaves are equipped with time monitoring. If they are not supplied with new output data cyclically within a predefinable time, they initiate the intrinsically safe state. For the operation of the one control unit, which in the example described works as a PROFIBUS DP master, compliance with a defined, predictable cycle time must be ensured. If a processor of a personal computer with a non-real-time operating system, for example Windows NT, is used as the other control unit, it can happen that, for example, a writing process of a new data record is interrupted before all the words belonging to the data record have been written into the buffer memory. There is no guarantee that the PC processor will continue to write within the defined cycle time and that the data record will be written completely into the buffer memory. On one side of the buffer memory, however, the fieldbus controller must wait to read this data record until the PC processor on the other side has completed its writing process. The cycle time specified for the fieldbus is thus exceeded and the distributed I / O connected to the fieldbus initiates the intrinsically safe state. The known arrangement for the transmission of data records is therefore only suitable for transmission between two control units, both of which have a deterministic behavior.

The invention has for its object to provide an arrangement for the transmission of data sets divided into several words, in which a consistent transmission of the data sets is guaranteed and at the same time two control units involved in the transmission can be operated largely without mutual interference.

To solve this problem, the new transmission arrangement of the type mentioned has the features specified in the characterizing part of claim 1. Advantageous further developments are described in the subclaims. The invention has the advantage that each control unit can always access a memory that is available to it almost exclusively. Processes can therefore run separately on the two control units and each control unit has all the information it needs in its memory. If a new data record has been completely entered into a first memory which is assigned to a first control unit by the first control unit, then this data record is copied in a comparatively fast manner at a point in time at which a second control unit points to the corresponding data record in a second one assigned to it Memory is not currently being accessed, transferred to the second memory. After a slight delay, current data is available in both memories. This advantageously ensures a consistent one of the access times

Control unit independent transfer of data between two control units achieved. The new arrangement is also suitable for the transmission of data records of any length. In principle, an access of a control unit to the memory assigned to it can take any length of time since all information is constantly available in the memory assigned to the other control unit.

A comparatively fast copying process has the advantage that the control units are blocked correspondingly shorter times during the copying process from accesses to the currently copied data record. Access to both sides is therefore not significantly delayed.

Copying processes, during which access to both control units is blocked, have no restrictive effect on the temporal accessibility of the first control unit if the latter can initiate the copying processes itself. For this purpose, the first control unit can advantageously be designed in such a way that it initiates copying processes precisely when they are not accessing this data record want. The first control unit thus has virtually all of the data records available in the first memory at all times.

The first control unit initiates copying of the data record into the second memory immediately after it has completely written a data record into the first memory. In this way, current data records are advantageously immediately available in the second memory for the second control unit.

Another advantage is achieved if the first control unit initiates copying of the data record, which corresponds to the last one read, from the second memory into the first memory before reading a data record from the first memory. If changes have occurred during the reading time of the last data record read and have been stored in the second memory by the second control unit, the first memory is updated with these changes without additional delay.

So that new data are advantageously more quickly available for the first control unit, the second control unit can simultaneously write access to the first memory and the second memory. Copying processes, which would be necessary without this possibility, are omitted. In an application in a personal computer with a fieldbus interface, a cyclical operation of the fieldbus is advantageously ensured if the arrangement for the transmission of data records is part of a plug-in card for the personal computer, which is an interface between the

Processor of the personal computer as the first control unit and the fieldbus implemented with a fieldbus master as the second control unit.

Based on the drawings, in which an embodiment of the invention is shown, the invention and embodiments and advantages are described in more detail below. FIG. 1 shows a block diagram of a personal computer with a connected fieldbus, FIG. 2 shows a block diagram with the essential parts of an arrangement for the transmission of data records,

3 shows a flow chart for a write access and FIG. 4 shows a flow chart for read access to a data record.

FIG. 1 shows a simple automation system for controlling a process, which has a personal computer 1 and a field bus 2 connected to it, which is designed as PROFIBUS DP, with a sensor 3 and an actuator 4. The personal computer 1 is constructed in the usual way and contains a processor 5 which is connected via a PCI bus 6 to a working memory 7, a ROM 8 and a drive 9. Other components of the personal computer are not shown for reasons of clarity. An operating system, for example Windows NT, is loaded onto the personal computer that is not real-time capable. The interface between the personal computer 1 and the fieldbus 2 forms a plug-in card 10, which is inserted into the personal computer 1 and connected to the PCI bus 6. Via this plug-in card 10, a control program, which runs as an application in the personal computer 1, can read in measurement data acquired by the sensor 3 on the process and issue control commands to the actuator 4, which acts as an actuator on the process. For this purpose, data is exchanged cyclically between the connected components 3, 4 and 10 via the fieldbus 2. The plug-in card 10 contains a PROFIBUS DP master which cyclically calls the sensor 3 and the actuator 4, both of which are operated as PROFIBUS DP slaves, for data exchange.

According to FIG. 2, an arrangement for the transmission of data records divided into several words essentially consists of a first memory A, a second memory B, one Copy unit S2 and a synchronization logic SL. The processor 5 (FIG. 1) of the personal computer 1 can access the first memory A assigned to it via the system bus 6 and a controllable gate S1. On the other hand, a controller 20, which is part of a connection to the fieldbus 2, has access to the second memory B via a controllable gate S3. In the first memory A there is storage space for data records Eil ... Ein for input data and Storage space for data records All ... Alm provided for output data. The second points accordingly

Memory B Storage space for data records E21, .. E2n for input data and for data records A21 ... A2m for output data. For the example of a PROFIBUS DP as fieldbus, this can be 128 data records with 256 bytes each in memories A and B. 256 bytes are also available for diagnostic data per slave (128 data records with 256 bytes). Since diagnostic data is treated like input data, it is not necessary to consider these data records in the further description. One data record is therefore available in the first memory A and in the second memory B for each slave that can be connected to the PROFIBUS DP. The first memory A can be accessed with a 32-bit data width and the second memory B with a 16-bit data width. To control the access, two control cells ZO and ZI and a register DS are also provided, which are the first to be processed by the processor 5

Control unit can be described and evaluated by the synchronization logic SL. The controller 20 as the second control unit cyclically reads the data records A21 ... A2m of the output data from the second memory B and writes the data records E21 ... E2n with current input data. A complete data record is always read or written. Via a line 21, the controller 20 signals the synchronization logic SL in each case to the start and end of a write or read operation on a data record. The signal on line 21 is used by the synchronization logic SL to control copying processes by the copying unit S2. The controller 20 can also Describe input data records Eil ... On in memory A at the same time as writing data records E21 ... E2n for input data in memory B via a path 22. Controlled by the synchronization logic SL, however, this possibility only exists if the first control unit, the processor 5, does not also access the respective data set express ... one of the input data in the memory A. An access of the first control unit to a data record in the memory A is indicated to the synchronization logic SL with the control cells ZO and ZI and with the register DS. The control cells ZO and ZI differentiate between write access to one of the data records All ... Alm in memory A or read access to one of the data records Express ... On for input data in memory A. The respective number of the data record is entered in the DS register.

The individual steps of a write access by the first control unit to one of the data records All ... Alm of the output data in the memory A are to be explained below with reference to the flow chart in FIG. In a step 33, the first control unit writes the new output data, for example, into a data record A12 of the memory A assigned to it. In principle, he has any time to write in the new output data. During the writing process, the second control unit 20 still has the old output data stored in the data record A22. After the first control unit 5 (FIG. 1) has completely written the data record A12 with the new output data, it accesses the control cell ZO and writes the number of the data record A12 in the register DS. When writing to the control cell ZO, the number of the data record A12 is entered directly in the register DS. The synchronization logic SL is thus indicated that new output data have been completely entered in the data record with the number entered in the DS register. The copying unit S2 is caused in a step 36 to output the output data of the data record A12 to the corresponding data record A22 Copy memory B if a query 35 has determined that the second control unit 20 is not currently accessing the data record A22 in memory B. During the copying process in step 36, the two controllable gates S1 and S3 are blocked by the synchronization logic SL for access by the first control unit 5 to the data record A12 and for access by the second control unit 20 to the data record A22. In a step 37, the register DS is set to a DEFAULT value by the synchronization logic SL, for example the hexadecimal value FF, which is not one of the occurring ones

Corresponds to record numbers, reset. The first control unit 5 advantageously initiates copying processes itself, so that copying processes are always carried out when the first control unit 5 does not want to access the corresponding data record. Access by the first control unit 5 is thus possible without delay. The copying process itself is carried out comparatively quickly by a control unit in the copying unit S2, which is implemented by a programmable integrated circuit.

The first control unit 5 initiates read access, for example, to the data record E12 in memory A by writing access to the control cell ZI and writing the corresponding data record number into the register DS. This write access is carried out in the flow chart according to FIG. 4 with a step 41. However, the number of data record E12 is not yet entered in the DS register. In a query 42, the synchronization logic SL then checks whether the second control unit 20 is currently writing access to the data record, the number of which is still entered in the register DS, since the first control unit 5 has read access to it was, for example on the data record express. If this is not the case, a step is made to step 43, in which the previously blocked data record, in this example the data record Express for input data, is updated by copying the data record E21 from the memory B into the memory A. becomes. The number of the data record E12 is then entered in the register DS in a step 44. As a result, further accesses of the second control unit 20 to the data record E12 are blocked by the synchronization logic SL. The first control unit 5 now reads it for the second

Control unit 20 blocked data record E12 with input data from memory A. This takes place in a step 45. While the data record E12 is blocked for the second control unit 20, the latter can of course have write access to the corresponding data record E22 in memory B for one cycle of its processing cycle. When the next data record is read out by the first control unit 5, the steps of the flow chart according to FIG. 4 are carried out again. A possibly updated data record E22 is copied into the corresponding data record E12 of the memory A. All input data records which are not locked are updated by the second control unit 20 both in the memory A and in the memory B. This means that current data is immediately available in the memory A for the first control unit 5 without first having to be copied from the memory B into the memory A.

The exemplary embodiment shown makes it clear that the arrangement for the transmission of data does not impose any requirements on the control units. For example, a process running on the first control unit can be non-deterministic and asynchronous, without the behavior of a deterministic process on the second control unit being influenced thereby. In addition, the data records are always exchanged consistently between the two control units. Each control unit has access to a memory assigned to it, in which a process image can be kept for the example of an automation system described.

Claims

claims

1. Arrangement for the transmission of data records divided into several words between two control units (5, 20) with a memory arrangement (A, B), to which the two control units can read and / or write access, characterized in that the memory arrangement has a first memory (A) and a second memory (B) for the data sets to be transmitted (Eil ... Ein, All ... Alm; E21 ... E2n, A21 ... A2m), with a first control unit (5) at least the first memory (A) and a second control unit (20) can access at least the second memory (B), that a copying unit (S2) is provided, through which data records from the first memory (A) into the second memory (B) and / or vice versa, and that a synchronization logic (SL) is present such that during an access of the first control unit (5) to a data record (A12) in the first memory (A) the corresponding data record (A22) and Indent If the second control unit (20) cannot access the respective data record (A12) in the first memory (A), the second control unit (20) can, however, access the corresponding data record (A22) in the second memory (B).

2. Arrangement according to claim 1, characterized in that the copying unit (S2) is designed such that a copying process of a data record from one memory to the other is much faster than reading or writing a data record by a control unit, and that during a copying process Accesses of the first control unit (5) to the respective data record (A12) in the first memory (A) and the second control unit (20) to the respective data record (A22) in the second memory (B) are blocked by the synchronization logic (SL).

3. Arrangement according to claim 1 or 2, characterized in that copying operations can be initiated by the first control unit (5).

4. Arrangement according to claim 3, characterized in that the first control unit (5) initiates copying of the data set into the second memory (B) after writing a complete data set in the first memory (A).

5. Arrangement according to claim 3 or 4, characterized in that the first control unit (5) before reading a data record from the first memory (A) copying the data record, which corresponds to the last read, from the second memory (B) in initiates the first memory (A).

6. Arrangement according to one of the preceding claims, characterized in that the second control unit (20) can simultaneously write access to the first memory (A) and to the second memory (B).

7. Arrangement according to one of the preceding claims, characterized in that it is part of a plug-in card (10) for a personal computer (1) which has an interface between a PC processor (5) as the first control unit and a fieldbus (2nd ) with a fieldbus master (20) as the second control unit.