WO2000052639A3 - Two architectures for integrated realization of sensing and processing in a single device - Google Patents

Two architectures for integrated realization of sensing and processing in a single device Download PDF

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Publication number
WO2000052639A3
WO2000052639A3 PCT/US2000/005785 US0005785W WO0052639A3 WO 2000052639 A3 WO2000052639 A3 WO 2000052639A3 US 0005785 W US0005785 W US 0005785W WO 0052639 A3 WO0052639 A3 WO 0052639A3
Authority
WO
WIPO (PCT)
Prior art keywords
sensor processor
array
sensing
transconductance amplifier
amplifier configured
Prior art date
Application number
PCT/US2000/005785
Other languages
French (fr)
Other versions
WO2000052639A2 (en
Inventor
Gamze Erten
Fathi M Salam
Original Assignee
Clarity Llc
Gamze Erten
Fathi M Salam
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarity Llc, Gamze Erten, Fathi M Salam filed Critical Clarity Llc
Priority to CA002364182A priority Critical patent/CA2364182A1/en
Priority to EP00914830A priority patent/EP1175659A2/en
Priority to AU36167/00A priority patent/AU3616700A/en
Priority to JP2000602988A priority patent/JP2002538557A/en
Priority to US09/914,030 priority patent/US6735482B1/en
Publication of WO2000052639A2 publication Critical patent/WO2000052639A2/en
Publication of WO2000052639A3 publication Critical patent/WO2000052639A3/en
Priority to HK02101234.2A priority patent/HK1039992A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

An integrated sensing device comprising an array of sensor processor cells capable of being arranged into a detection array. Each sensor processor cell comprises a sensing medium; at least one transconductance amplifier configured for feedforward template multiplication; at least one transconductance amplifier configured for feedback template weights; a plularity of local dynamic memory cells; a data bus for data transfer; and a local logic unit. The array of sensor processor cells, by responding to data control signals, is capable of transforming, reshaping, and modulating the original sensed image into varied represenations which include (and extend) traditional spatial and temporal processing transformations.
PCT/US2000/005785 1999-03-05 2000-03-06 Two architectures for integrated realization of sensing and processing in a single device WO2000052639A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CA002364182A CA2364182A1 (en) 1999-03-05 2000-03-06 Two architectures for integrated realization of sensing and processing in a single device
EP00914830A EP1175659A2 (en) 1999-03-05 2000-03-06 Two architectures for integrated realization of sensing and processing in a single device
AU36167/00A AU3616700A (en) 1999-03-05 2000-03-06 Two architectures for integrated realization of sensing and processing in a single device
JP2000602988A JP2002538557A (en) 1999-03-05 2000-03-06 Two architectures for integrated implementation of sensing and processing in a single device
US09/914,030 US6735482B1 (en) 1999-03-05 2000-03-06 Integrated sensing and processing
HK02101234.2A HK1039992A1 (en) 1999-03-05 2002-02-20 Two architectures for integrated realization of sensing and processing in a single device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12317799P 1999-03-05 1999-03-05
US60/123,177 1999-03-05

Publications (2)

Publication Number Publication Date
WO2000052639A2 WO2000052639A2 (en) 2000-09-08
WO2000052639A3 true WO2000052639A3 (en) 2001-02-15

Family

ID=22407147

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/005785 WO2000052639A2 (en) 1999-03-05 2000-03-06 Two architectures for integrated realization of sensing and processing in a single device

Country Status (7)

Country Link
EP (1) EP1175659A2 (en)
JP (1) JP2002538557A (en)
CN (1) CN1457471A (en)
AU (1) AU3616700A (en)
CA (1) CA2364182A1 (en)
HK (1) HK1039992A1 (en)
WO (1) WO2000052639A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9283900B2 (en) 1999-08-25 2016-03-15 Magna Electronics Inc. Accessory mounting system for a vehicle

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100864703B1 (en) 1999-11-19 2008-10-23 젠텍스 코포레이션 Vehicle accessory microphone
US7120261B1 (en) 1999-11-19 2006-10-10 Gentex Corporation Vehicle accessory microphone
ES2209642B1 (en) * 2002-11-04 2005-10-01 Innovaciones Microelectronicas, S.L. MIXED SIGNAL PROGRAMMED INTEGRATED CIRCUIT ARCHITECTURE FOR THE PERFORMANCE OF AUTONOMOUS VISION SYSTEMS OF A SINGLE CHIP AND / OR PRE-PROCESSING OF IMAGES IN HIGHER LEVEL SYSTEMS.
US10346944B2 (en) * 2017-04-09 2019-07-09 Intel Corporation Machine learning sparse computation mechanism
CN111368253B (en) * 2018-12-26 2023-09-26 兆易创新科技集团股份有限公司 Convolution operation method and device based on nonvolatile memory
CN111539178B (en) * 2020-04-26 2023-05-05 成都市深思创芯科技有限公司 Chip layout design method and system based on neural network and manufacturing method
CN111983629B (en) * 2020-08-14 2024-03-26 西安应用光学研究所 Linear array signal target extraction device and extraction method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140670A (en) * 1989-10-05 1992-08-18 Regents Of The University Of California Cellular neural network
US5355528A (en) * 1992-10-13 1994-10-11 The Regents Of The University Of California Reprogrammable CNN and supercomputer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140670A (en) * 1989-10-05 1992-08-18 Regents Of The University Of California Cellular neural network
US5355528A (en) * 1992-10-13 1994-10-11 The Regents Of The University Of California Reprogrammable CNN and supercomputer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ERTEN G ET AL: "Modified cellular neural network architecture for integrated image sensing and processing", ISCAS'99. PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS VLSI (CAT. NO.99CH36349), ISCAS'99. PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. VLSI, ORLANDO, FL, USA, 30 MAY-2 JUNE 1999, 1999, Piscataway, NJ, USA, IEEE, USA, pages 120 - 123 vol.5, XP002149482, ISBN: 0-7803-5471-0 *
ERTEN G ET AL: "Two cellular architectures for integrated image sensing and processing on a single chip", JOURNAL OF CIRCUITS, SYSTEMS AND COMPUTERS, OCT.-DEC. 1998, WORLD SCIENTIFIC, SINGAPORE, vol. 8, no. 5-6, pages 637 - 659, XP000952076, ISSN: 0218-1266 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9283900B2 (en) 1999-08-25 2016-03-15 Magna Electronics Inc. Accessory mounting system for a vehicle

Also Published As

Publication number Publication date
JP2002538557A (en) 2002-11-12
CN1457471A (en) 2003-11-19
WO2000052639A2 (en) 2000-09-08
CA2364182A1 (en) 2000-09-08
EP1175659A2 (en) 2002-01-30
AU3616700A (en) 2000-09-21
HK1039992A1 (en) 2002-05-17

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