WO2000063958A1

WO2000063958A1 - In situ, controlled ambient deposition of ono for application to flash eprom

Info

Publication number: WO2000063958A1
Application number: PCT/US2000/009724
Authority: WO
Inventors: Robert Bertram Ogle, Jr.; Arvind Halliyal
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1999-04-16
Filing date: 2000-04-11
Publication date: 2000-10-26

Abstract

An integrated circuit manufacturing process and the product formed thereby for an interpoly dielectric used in floting gate memory devices such as Flash EPROM provides for scaling down in dielectric thickness without lowering yield. The use of a cluster deposition system for the ONO layers of the interpoly dielectric lowers the amount of carbon-based residue on the dielectric layers and lowers the leakage current.

Description

IN SITU, CONTROLLED AMBIENT DEPOSITION OF ONO FOR

APPLICATION TO FLASH EPROM

Field of the Invention

This invention pertains to integrated circuit manufacturing technology, and in particular to an improved process and product produced therefrom for forming an interpoly dielectric for Flash EPROM.

Background of the Invention

Flash EPROM' s (Erasable Programmable Read-Only Memory) are a type of programmable memory cell, wherein channel conductivity of a transistor therein may be maintained at one of two levels, corresponding to two binary states. In Flash EPROM technology, the contents of all of the memory's array cells can be simultaneously and rapidly erased through the use of an electrical erase signal. Flash EPROM 's utilize a floating gate which retains charge until discharged through an erase process wherein the erasing mechanism is Fowler-Nordheim tunneling from the floating gate to the drain region. Flash EPROM 's offer high density, low cost, and easy erasability. The basic structure of a Flash EPROM is shown in Figure la and Figure lb. The floating gate 2 (generally polysilicon) is separated from substrate 4 by gate oxide 6. Composite interpoly dielectric layer 8, which may be composed of an Oxide-Nitride-Oxide (ONO) sandwich, separates floating gate 2 from control gate 10, also generally polysilicon. The interpoly layer must have a sufficiently high breakdown voltage to provide for effective charge retention, i.e., to prevent charge loss from the floating gate at all times other than during an erase cycle. The interpoly dielectric breakdown voltage must be high enough so that Fowler-Nordheim tunneling from floating gate to control gate is blocked when the control gate has 12 - 20 volts applied thereto.

One prior-art embodiment of an interpoly dielectric structure usable for Flash EPROM is described in US patent No. 5,104,819, by Freiberger et al, which is hereby incorporated by reference.

In current Flash EPROM technology, the effective thickness of the ONO composite layer, i.e., the thickness of an oxide layer having equivalent capacitance, is approximately 150 Angstroms. However, as device dimensions shrink, circuit performance improves, and circuit density increases, it is desirable, as in conventional transistor scaling, to thin the interpoly dielectric layer. Capacitative coupling between the control electrode and the floating gate electrode is improved with thinner interpoly dielectric thickness, thereby improving transistor speed and performance. The scaling of the interpoly dielectric thickness has in the past been limited by an increase of leakage current and the resultant lowering of the dielectric breakdown voltage, both of which reduce the Flash EPROM device yield for thinner dielectric layers. A method for providing interpoly dielectric layers with effective thickness below 130 Angstroms without lowering device yield would be desirable for scaling down of Flash EPROMs. The same method would also be useful for other EPROM-related technologies such as EEPROM's, and any other technologies which utilize the ONO interpoly dielectric layer.

Summary of the Invention

It is therefore an object of this invention to provide an improved interpoly dielectric usable for Flash EPROM and other EPROM- related technologies, and an improved manufacturing process for its forming. It is a further object of this invention to provide an improved interpoly dielectric usable for Flash EPROM and other EPROM- related technologies, which has an equivalent thickness below 130 Angstroms, while maintaining device yield, and an improved manufacturing process for its forming. It is a further object of this invention to provide an improved interpoly dielectric usable for Flash EPROM and other EPROM- related technologies, which has an equivalent thickness below 130 Angstroms, while maintaining leakage current at acceptably low levels, and an improved manufacturing process for its forming. These objects are met by utilizing a process for forming the interpoly dielectric layer which provides for a sufficiently lower amount of organic film between the ONO layers to allow scaling of the dielectric thickness below 130 Angstroms while maintaining device yield. Brief Description of the Drawings

Fig. la shows the gate region of a prior art Flash EPROM cell.

Fig. lb shows an expanded view of the gate and dielectric region of the cell of Fig. la. Fig. 2 is a schematic drawing of the cluster deposition system used in the experiments described herein.

Fig. 3 shows the gate and dielectric region of a Flash EPROM cell having the inventive structure and made by the inventive process.

Detailed Description of the Invention

Figure la shows the configuration of the gate region of an embodiment of a Flash EPROM cell, which is known in the art. The floating polysilicon gate 2 is separated from substrate 4 by gate oxide 6. Composite interpoly dielectric layer 8, composed of an Oxide- Nitride-Oxide (ONO) sandwich, separates floating gate 2 from polysilicon control gate 10. Voltage applied to control gate 10 controls the charge on floating gate 2. The charge on floating gate 2 in turn determines the surface channel conductivity in channel region 12 beneath gate 2, which determines the binary state of that cell. Figure lb is an expanded view of the gate and dielectric region of the cell of Figure la. ONO composite layer is comprised of a bottom silicon dioxide layer 14 atop floating gate 2, silicon nitride layer 16 atop oxide layer 14, and top silicon dioxide layer 18 atop nitride layer 16. Control gate 10 is shown atop oxide layer 18. In prior art processes for forming the ONO layer, bottom oxide layer 14 is generally formed by Low Pressure Chemical Vapor Deposition (LPCVD) in a high throughput batch oxide deposition chamber, and has a thickness of approximately 50 - 60 Angstroms. Silicon nitride layer 16 is also generally LPCVD, is deposited in a separate nitride deposition chamber, and has a thickness of approximately 100 Angstroms (with an equivalent oxide thickness of approximately 50 Angstroms). Top oxide layer 18 is generally LPCVD or thermally formed by partial oxidation of nitride, and has a thickness of approximately 40 - 50 Angstroms.

In transferring wafers from a separate oxide deposition chamber to a separate nitride deposition chamber and back, as has been done in prior art processes, exposure to the fabrication facility environment allows for the adsorption of organic contaminants onto the surface of the wafer. These organic contaminants have been generally thought to be burned off during oxidation processes. However, we have discovered that in the LPCVD nitride system, the organic contaminants decompose and leave a residue 19 on the surface of bottom oxide 14, composed of such material as carbon or silicon carbide.

It has been experimentally determined, by measuring leakage current in conventional MOS diodes with varying queue times that presence of such an organic film residue causes increased leakage currents through dielectric layers.

According to our invention, the problem of organic residue on the surface of the bottom oxide layer in the ONO structure is recognized as being a limiting factor in the ability to successfully scale down interpoly dielectric thickness in Flash EPROM 's while maintaining device yield, and the problem is solved by utilizing a cluster deposition system to deposit the bottom two, or alternately all three, layers of the ONO film without return to the atmospheric environment, so as to essentially eliminate this organic residue. Figure 2 shows a schematic drawing of a cluster deposition system, which was used in the experiments described herein. A single wafer enters evacuated region 20 through load lock 22 and is transferred through transfer chamber 23 into oxide deposition chamber 24 or nitride deposition chamber 26. Upon completion of the oxide deposition, the wafer is transported into the nitride deposition chamber via transfer chamber 23, without being removed from the vacuum environment (pressure = approximately 23 Torr) and therefore has very little exposure to organic contaminants between deposition of the bottom oxide and nitride layer of the ONO structure. The top oxide is either deposited in the same cluster tool, or thermally grown in a separate batch furnace. Better results have been obtained with thermally grown top oxide, by partial oxidation of the nitride layer. Figure 3 shows the gate and dielectric region of a Flash EPROM cell formed using the inventive method. There is no measurable organic residue 19 atop bottom oxide layer 14.

Table 1 shows experimental results from Flash EPROM devices fabricated using the standard batch process for the ONO layer, wherein separate nitride and oxide deposition chambers are utilized, compared with Flash EPROM devices fabricated using the inventive process for the ONO layer, wherein the nitride and bottom oxide layers are deposited in the vacuum environment of the cluster chamber. The wafers fabricated using the standard process will be hereinafter referred to as the control wafers. Wafer # Process Equiv. Oxide thickness (A)

1 control

2 control 141.7

4 control 142.6

5 control

6 control

11 inventive 115 12 inventive 118 17 inventive 125 18 inventive 122 23 inventive 131 24 inventive 132

TABLE 1 EXPERIMENTAL DATA

The standard ONO deposition process for the control wafers comprises: 1) 50-60 Angstroms LPCVD oxide deposited atop the floating poly gate, using a conventional batch oxide deposition system;

2) 80-100 Angstroms LPCVD nitride deposited atop the oxide, using a conventional batch nitride deposition system;

3) 40-50 Angstroms thermal oxide grown by partial oxidation of the nitride, in batch mode.

The equivalent oxide thickness for the conventionally prepared ONO layer on the control wafers, as measured by capacitance-voltage (CV) tests is approximately 140 - 150 Angstroms. The inventive ONO deposition process for the experimental wafers comprises:

1) 40-50 Angstroms Rapid Thermal CVD (RTCVD) oxide, deposited in the cluster deposition tool. The process chamber is brought to a pressure of 50 Torr and a mixture of dichlorosilane (DCS) and nitrous oxide (N20) is flowed into the process chamber with nitrogen carrier gas while the temperature is ramped to 750C. The target oxide thickness is achieved by controlling the duration of deposition, ranging between 20 and 60 seconds. The pressure and temperature remain constant during the deposition process.

2) 80-100 Angstroms RTCVD nitride, deposited in the cluster deposition tool. The process chamber is brought to a pressure of 100 Torr and a mixture of dicholorosilane and ammonia (NH3) is flowed into the process chamber with nitrogen carrier gas while the temperature is ramped to 750C. The target nitride thickness is achieved by controlling the duration of deposition, ranging between 50 and 100 seconds. The pressure and temperature remain constant during the deposition process.

3) 40 Angstroms oxide grown by partial steam oxidation of the RTCVD nitride, done in a conventional batch furnace at 950C.

The equivalent oxide thickness for the ONO layer on the experimental wafers as measured by CV tests ranges between 115 and 132 Angstroms.

A comparison between the Flash EPROM yield data for the control vs the experimental wafers shows comparable results for the two. There is no indication of lower yield for the experimental wafers with equivalent thickness at the thinner end of this range. It is believed that the improvement in results for the Flash EPROM devices fabricated using the inventive method are due to the large decrease in organic residue on the bottom oxide layer of the ONO. It is expected that a minimum of a monolayer of organic materials are adsorbed onto the bottom oxide surface in the conventionally prepared ONO structure, whereas the residual layer is less than a monolayer for the ONO structure prepared in the cluster chamber according to the inventive process.

By utilizing the inventive process for fabricating the ONO layer of a Flash EPROM device, an improved device is produced having essentially no measurable organic residue between the ONO layers. The resultant lowering of leakage current through the interpoly dielectric improves charge retention and allows the device yield to be maintained for thinner interpoly dielectric layers. Scaling of the ONO to smaller thickness improves capacitative coupling between the control gate and the floating gate, thereby improving the speed and performance of the Flash EPROM device.

It is not our intention that the invention be restricted to the exact embodiments described herein. For example, the exact parameters of the oxide and nitride layer depositions may differ, or the type of cluster deposition chamber may vary, without altering the inventive concept. The oxide and nitride depositions could also be performed in a nitrogen ambient introduced following evacuation of the cluster system deposition chamber. The scope of the invention should be construed in view of the claims.

Claims

WITH THIS IN MIND, WE CLAIM:

1. In an integrated circuit manufacturing method for fabricating an EPROM device on a silicon wafer, said EPROM device having an ONO interpoly dielectric layer therein formed by growing and/or depositing a first and a second oxide layer and by depositing a nitride layer, the improvement comprising: forming said first oxide layer and said nitride layer of said ONO interpoly layer in an apparatus providing an evacuated environment by retaining said silicon wafers in said apparatus in said evacuated environment or in a nitrogen ambient continuously throughout said forming of said first oxide and said nitride layers; wherein said formed ONO layer is substantially free of measurable organic residues between said first oxide layer and said nitride layer.

2. An integrated circuit manufacturing method for fabricating an interpoly dielectric for use in an EPROM device comprising the steps of: providing a silicon wafer having a floating gate memory device therein fabricated through formation of a first polysilicon gate atop a gate oxide; installing said silicon wafer into an apparatus for providing an evacuated environment, said apparatus having a process chamber having adjustable pressure and temperature, and establishing a vacuum therein; depositing a first layer of silicon dioxide atop said first polysilicon gate; without exposing said wafer to ambient atmospheric environment, depositing a layer of silicon nitride atop said first layer of silicon dioxide; forming a second layer of silicon dioxide atop said layer of silicon nitride; said silicon wafer remaining in said evacuated environment or in a nitrogen ambient continuously throughout said depositing of said first silicon dioxide layer and of said silicon nitride layer; said interpoly dielectric so formed being substantially free of measurable quantities of organic residues therein between said first oxide layer and said nitride layer.

3. The process of claim 2 wherein said evacuated environment is provided by a cluster deposition system.

4. The process of claim 3 wherein said first silicon dioxide layer is deposited to a thickness in the range between 40 and 60 Angstroms and said silicon nitride layer is formed to a thickness in the range between 80 and 100 Angstroms.

5. The process of claim 4 wherein said steps of depositing said first silicon dioxide layer and said silicon nitride layer comprise Rapid Thermal CVD (RTCVD) processes.

6. The process of claim 5 wherein: a) said step of depositing said first silicon dioxide layer comprises: flowing a mixture of dichlorosilane (DCS) and nitrous oxide (N20) into said process chamber with nitrogen carrier gas; adjusting the pressure in said process chamber to 50 Torr; rapidly ramping the temperature in said process chamber from room temperature to 750C; maintaining said wafer at said pressure of 50 Torr and said temperature of 750C for a time in the range between 20 and 60 seconds; ceasing said flowing of DCS and N20; rapidly lowering said temperature to room temperature; b) said step of depositing said silicon nitride layer comprises: flowing a mixture of dichlorosilane (DCS) and ammonia (NH3) into said process chamber with nitrogen carrier gas; adjusting the pressure in said process chamber to 100 Torr; rapidly ramping the temperature in said process chamber to

750C; maintaining said wafer at said pressure of 100 Torr and said temperature of 750C for a time in the range between 50 and 100 seconds; ceasing said flowing of DCS and NH3; rapidly lowering said temperature to room temperature; and; c) said step of forming a second layer of silicon dioxide atop said layer of silicon nitride comprises; growing 40 Angstroms oxide by partial steam oxidation of said silicon nitride layer in a conventional batch furnace at 950C.

7. A silicon wafer intermediate product comprising: a silicon substrate; a gate oxide grown thereon; a polysilicon layer deposited onto said gate oxide; an ONO interpoly dielectric layer comprising; a first deposited silicon dioxide layer; a silicon nitride layer deposited onto said first deposited silicon dioxide layer; a second silicon dioxide layer atop said second polysilicon layer; said first deposited silicon dioxide layer having substantially less than a monolayer of organic contaminants thereon.

8. The silicon wafer intermediate product of claim 7, wherein: said first deposited silicon dioxide layer has a thickness in the range between 40 and 60 Angstroms; and said silicon nitride layer has a thickness in the range between 80 and 100 Angstroms.

9. The silicon wafer intermediate product of claim 8, wherein said second silicon dioxide layer has a thickness in the range between 35 and 40 Angstroms.

10. A floating gate memory device having an interpoly dielectric therein, said interpoly dielectric being fabricated using the process of claim 4.