WO2000064215A1 - Atm adaptation layer type 1 integrated circuit between pcm and atm - Google Patents
Atm adaptation layer type 1 integrated circuit between pcm and atm Download PDFInfo
- Publication number
- WO2000064215A1 WO2000064215A1 PCT/TR2000/000021 TR0000021W WO0064215A1 WO 2000064215 A1 WO2000064215 A1 WO 2000064215A1 TR 0000021 W TR0000021 W TR 0000021W WO 0064215 A1 WO0064215 A1 WO 0064215A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- information
- pcm
- atm
- bit
- aal1
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
- H04L2012/5654—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL1
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5663—Support of N-ISDN
Definitions
- the present invention involves an integrated circuit used between Pulse Code Modulation (PCM) bus and Asynchronous Transmission Mode (ATM) bus in telecommunication systems.
- PCM Pulse Code Modulation
- ATM Asynchronous Transmission Mode
- the present invention especially involves the Convergence Sublayer in the AAL1 integrated circuit and the new methods implemented therein.
- the end user on the Transmitter Side can send information to the place where the information will be converted into a structure that is appropriate to be carried on ATM bus by using a bus called Pulse Code Modulation (PCM) before having sent the information it will send to the Receiver Side to the telecommunication system, or, the end user on the Receiver Side, shown in Figure 1 , can receive the information it will receive from the Transmitter Side via PCM bus from the place where the information will be converted from the structure which is appropriate to be carried on ATM bus into the structure which is appropriate to be carried on PCM bus.
- PCM Pulse Code Modulation
- each PCM bus the information of the 32 end users are carried in consecutive time slots, each time slot consists of 8 consecutive bits whici ⁇ carry the information of an end user, and each PCM bus consists of two buses which are the Transmitter bus and the Receiver bus.
- the information of the end users are carried with PCM buses to the node where those will be transferred to the ATM bus, and those will be transported with the ATM network to the node where it will be read through PCM buses by the other peer end user.
- AAL ATM Adaptation Layer
- AAL1 integrated circuits exist that support up to 16 PCM buses. All of those support 64 kbps connections (kilobits per second, number of 1000 bits per second) which is the maximum capacity of the information transfer that is defined for an end user on a PCM bus. But none of those support bit rates lower than 64 kbps and X.30/V.110 format.
- the present invention has been developed to overcome the restrictions covered above.
- AAL1 consists of CS (Convergence Sublayer) and SAR (Segmentation and Reassembly sublayer).
- the said CS quantizes information coming from the end user on the Transmitter Side into packets and passes to packet to the end users on the Receiver Side.
- the said SAR attaches etiquette to each packet sends on the Transmitter Side and analyzes etiquette of packets and sends CS on the Receiver Side.
- the CS part of the AAL1 integrated circuits in the market support the end users of 64 kbps rate only. Therefore the end users who will be have the benefit of this type of AAL1 must run in this bit rate.
- the integrated circuit described throughout this document has been designed in order that both the end user of the old systems and the end users on the new systems can be connected to the ATM network which supports ISDN services. According to that, the CS part of the AAL1 integrated circuit that has been designed supports more end user variety than the other products do in the market. Thanks to this new CS, connections of all types of transparent format up to 64 kbps and all types of X.30/V.110 formats, totally up to 128 end users are supported at the same time.
- the information of the end user on the Transmitter Side, which comes on its own PCM channel can be written in any place of the ATM cell payload; the information of the end user on the Transmitter Side, which comes on its own PCM channel, can be mapped into other sizes than the ATM cells have; the information of the end user on the Receiver Side, which will be sent on its own PCM channel, can be read from any place of the ATM cell payload; and the information of the end user on the Receiver Side, which will be sent on its own PCM channel, can be read from the packets of other sizes than the ATM cells have.
- the packet size can be from 1 byte up to 4096 bytes.
- This system which can handle 128 channels on the Transmitter Side loads the control infromation of the current state during the turn of the corresponding channel, writes back the information of the next state by generating the pointer which points to the location for the bit that comes from the PCM bus for the corresponding channel.
- PFSM Parametric Finite State Machine
- the Transmit Parametric Algorithm is capable of processing PCM information of any kind of X.30/V.1 10 format and any bit rate up to 64 kbps on the Transmitter Side.
- the Receive Parametric Algorithm operates with the control information called parameter, which programs itself according to the requests of the end users on the Receiver Side, who are connected to the AAL1 , and to the request of the microprocessor which controls the AAL1.
- Typical features of the Receive Parametric Algorithm of the present invention are following:
- This system which can handle 128 channels on the Receiver Side loads the control information of the current state during the turn of the corresponding channel, writes back the information of the next state by generating the pointer which points to the location for the bit that will go to the PCM bus for the corresponding channel.
- PFSM Parametric Finite State Machine
- Figure 1 is a view of the transformation of the information transferred between the end users according to the present invention
- Figure 2 is a view of the structure of the Convergence Sublayer (CS) on the Transmitter Side according to the present invention
- Figure 3 is a view of the information transformation in the CS on the Transmitter Side
- Figure 4 is a view of the usage of the Pointer Table on the Transmitter Side
- Figure 5 is a view of how the X.30/V.110 format is sent from a channel on PCM bus is acquired
- Figure 6 is a view of the Segmentation and Reassembly sublayer (SAR) on the Transmitter Side of the AAL1 integrated circuit
- Figure 7 is a view of the Receiver Side of the AAL1 integrated circuit
- Figure 8 is a view of the information transformation in the CS on the Receiver Side.
- Figure 9 is a view of the usage of the Pointer Table on the Receiver Side.
- A AAL1 Integrated Circuit Transmitter CS
- B AAL1 Integrated Circuit Transmitter SAR
- the integrated circuit described here is used as shown in Figure 1.
- the AAL1 on the Transmitter Node (3) receives the information coming from the PCM bus (2) of the end user (1) and drops it to the ATM network (4, 5).
- the AAL1 on the Receiver Node (6) passes th? information coming from ATM network (4') to the PCM bus (2') of the end user (1').
- the ATM buses (4, 4') and the ATM network (5) carry information between the Transmitter and the Receiver.
- On of the static parameters is a bit which tells if the corresponding end user (1) on the Transmitter Side is active or not. If this bit is active, the AAL1 on the Transmitter Node (3) processes the information coming from the PCM bus (2) of the end user (1 ) on the Transmitter Side. Whenever the end user on the Transmitter Side is active or inactive, the microprocessor (13) must inform the integrated circuit, i.e. it must update the corresponding region of the Transmit Static Parameter Table (14).
- the Transmit CS (A) can be seen in Figure 2, which connects the end users (1) on the Transmitter Side and the Transmit AAL1 (3) integrated circuit on the Transmitter Side.
- the information coming from the PCM bus (2) of the end user (1) on the Transmitter Side in the Transmit AAL1 are traced by the a block named the Transmit Parametric Algorithm (15), if it is informed by the microprocessor (13) by writing the Transmit Static Parameter Table (14), that the end user is active.
- the Transmit Parametric Algorithm (15) performs an individual execution for each bit coming from the PCM bus (2) of the end user (1) on the Transmitter Side. Firstly ft reads the state information of the channel that the bit belongs to, from a state memory named the Transmit Dynamic Parameter Table (16).
- the dynamic parameters. are state information that change during the time while the end user (1) is active and tell which bit is being processed at that time.
- the ATM cell belongs to AAL1 (6) If the information in the header matches one of the entries in the table, it is called "the ATM cell belongs to AAL1 (6)" and the AAL1 (6) performs executions for the corresponding ATM cell. These executions are well defined in the AAL1 (6) standards. If it is recognized that the ATM cell does not belong to the AAL1 (6), it is discarded.
- the ATM cell payload (11 ') which contains the information of the end user (1') in the ATM cells that recognized to belong to the AAL1 (6) will be placed into the Receive Payload RAM (19').
- the end users (1 ') on the Receiver Side receive information that belong to themselves, from the PCM channel (8) that belong to themselves.
- the PCM buses (2') which are made up of these PCM channels (8) are connected to the Receiver CS (C) of the AAL1.
- the end users (1') can receive their information from the AAL1 (6) only if they are active. Whether an end user is active or not, is dependent upon the control information in the Receive Static Parametric Table (14') that belong to that end user (1') are active or not. If an end user (1') is active, the Receive Parametric Algorithm (15') in the Receiver CS (C) places the information of end user (1 ') into its PCM channel (8) on the Receiver Side.
- the information to be placed into the PCM channel (8) is an ATM cell payload (11') of the corresponding end user (1'), which the Receiver SAR (D) has written into the Receive Payload RAM (19') and is kept temporarily un*i' the Receiver CS (C) reads.
- Dynamic parameters are state information that change during the time while the end user on the Receiver Side is active, and tells which bit in the ATM cell payload (11') is the bit to be placed in that time to the PCM bus (2').
- the Receive Parametric Algorithm (15') generates the address of the pointer (24') for the corresponding bit.
- This address is the address of a memory named the Receive Pointer Table (18').
- the information in this address tells that the bit to be placed into the PCM bus (2') of the end user (1') on the Receiver Side must be read from which position in the ATM cell payload (11') written into the Receive Payload RAM (19') by the Receiver SAR (D) before.
- This information is connected to the address input of the Receive Payload RAM (19').
- the Receive Payload RAM (19') is a memory where the ATM cell payload (11') is kept temporarily until it is sent to the end users (1').
- the bit that will be sent to the end users is read here and will be placed into the PCM bus (2').
- the Receive Parametric Algorithm (15') calculates the new state state information and writes it back into the Receive Dynamic Parameter Table (16'). In this way the bit of each channel is placed into the PCM channel (8) of the end user (1') on the Receiver Side by reading from 47 byte ATM cell payload (1 1 ') sequentially, bit by bit. .
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU49698/00A AU4969800A (en) | 1999-04-16 | 2000-04-14 | Atm adaptation layer type 1 integrated circuit between pcm and atm |
EP00931888A EP1169882A1 (en) | 1999-04-16 | 2000-04-14 | Atm adaptation layer type 1 integrated circuit between pcm and atm |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TR99/00855 | 1999-04-16 | ||
TR1999/00855A TR199900855A2 (en) | 1999-04-16 | 1999-04-16 | A new ATM alignment layer that provides a transition between PCM and ATM type: 1 integrated circuit. |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000064215A1 true WO2000064215A1 (en) | 2000-10-26 |
Family
ID=21621945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/TR2000/000021 WO2000064215A1 (en) | 1999-04-16 | 2000-04-14 | Atm adaptation layer type 1 integrated circuit between pcm and atm |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1169882A1 (en) |
AU (1) | AU4969800A (en) |
TR (1) | TR199900855A2 (en) |
WO (1) | WO2000064215A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5790552A (en) * | 1993-03-26 | 1998-08-04 | Gpt Limited | Statistical gain using ATM signalling |
US5850406A (en) * | 1995-06-02 | 1998-12-15 | Siemens Aktiengesellschaft | Method for detecting and compensating for missing and/or incorrectly inserted cells in the asynchronous transfer method (ATM) |
US5894477A (en) * | 1994-05-21 | 1999-04-13 | Northern Telecom Limited | Communications system |
-
1999
- 1999-04-16 TR TR1999/00855A patent/TR199900855A2/en unknown
-
2000
- 2000-04-14 WO PCT/TR2000/000021 patent/WO2000064215A1/en active Application Filing
- 2000-04-14 EP EP00931888A patent/EP1169882A1/en not_active Withdrawn
- 2000-04-14 AU AU49698/00A patent/AU4969800A/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5790552A (en) * | 1993-03-26 | 1998-08-04 | Gpt Limited | Statistical gain using ATM signalling |
US5894477A (en) * | 1994-05-21 | 1999-04-13 | Northern Telecom Limited | Communications system |
US5850406A (en) * | 1995-06-02 | 1998-12-15 | Siemens Aktiengesellschaft | Method for detecting and compensating for missing and/or incorrectly inserted cells in the asynchronous transfer method (ATM) |
Non-Patent Citations (1)
Title |
---|
LEE Y -C ET AL: "DESIGN OF ATM AAL1 SAR FOR CIRCUIT EMULATION", IEEE TRANSACTIONS ON COMMUNICATIONS,US,IEEE INC. NEW YORK, vol. 46, no. 9, 1 September 1998 (1998-09-01), pages 1117 - 1121, XP000782268, ISSN: 0090-6778 * |
Also Published As
Publication number | Publication date |
---|---|
AU4969800A (en) | 2000-11-02 |
EP1169882A1 (en) | 2002-01-09 |
TR199900855A2 (en) | 2000-11-21 |
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