WO2000068778B1 - Multiple-thread processor with single-thread interface shared among threads - Google Patents

Multiple-thread processor with single-thread interface shared among threads

Info

Publication number
WO2000068778B1
WO2000068778B1 PCT/US2000/012800 US0012800W WO0068778B1 WO 2000068778 B1 WO2000068778 B1 WO 2000068778B1 US 0012800 W US0012800 W US 0012800W WO 0068778 B1 WO0068778 B1 WO 0068778B1
Authority
WO
WIPO (PCT)
Prior art keywords
thread
cache
threads
execution
processor according
Prior art date
Application number
PCT/US2000/012800
Other languages
French (fr)
Other versions
WO2000068778A3 (en
WO2000068778A9 (en
WO2000068778A2 (en
Inventor
William N Joy
Marc Tremblay
Gary Lauterbach
Joseph I Chamdani
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of WO2000068778A2 publication Critical patent/WO2000068778A2/en
Publication of WO2000068778A3 publication Critical patent/WO2000068778A3/en
Publication of WO2000068778B1 publication Critical patent/WO2000068778B1/en
Publication of WO2000068778A9 publication Critical patent/WO2000068778A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Abstract

A processor includes logic (612) for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB) (1258, 1220), a load buffer asynchronous interface, an external memory management unit (MMU) interface (320, 330), and others. A processor (300) includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, 'pollution', or 'cross-talk' between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.

Claims

AMENDED CLAIMS[received by the International Bureau on 27 April 2001 (27.04.01 ), original claims 1 and 28 amended; remaining claims unchanged (6 pages)]
1. A processor comprising a multiple-thread execution pipeline (314) including a plurality of execution pathways respectively allocated to a plurality of independent execution threads (310, 312) extending to a plurality of pipeline registers, wherein functional properties of an independent execution thread state are stored throughout the pipeline extending to the pipeline registers to enable the processor to postpone execution of a stalling thread, relinquish the pipeline to a previously idle thread, later resuming execution of the postponed stalling thread at the precise state of the stalling thread immediately prior to switching of the thread; and a non-stallmg component coupled to the multiple-thread execution pathways so that the plurality of execution pathways converge into a single-pathway including the non-stalling component.
2. A processor according to Claim 1 wherein: the non-stallmg component is selected from non-stallmg components including caches (1256, 1212). translation look-aside buffers (TLBs) (1258, 1220),load buffer asynchronous interfaces, and external MMU interface.
3. A processor according to either Claim 1 or Claim 2 further comprising: thread tagging logic (610) coupled to the non-stall g component, the thread tagging logic for setting a thread identifier (TID) tag identifying threads m the non- stalling component.
4. A processor according to any of Claims 1-3 further comprising: a single-pathway component coupled to the multiple-thread execution pathways so that the plurality of execution pathways converge into the smgle-pathway of the smgle-pathway component, the smgle-pathway component being a non- stalling component
5. A processor according to Claim 4 wherein: the smgle-pathway component is shared among a plurality of threads, the single- pathway component maintaining compatibility among threads by physical duplication of structures and by verifying communication status after transfer of a thread.
6. A processor according to either Claim 4 or Claim 5 wherein: the multiple-thread execution pipeline includes a plurality of functional units (1232, 1234, 1236, 1238, 1240, 1242, 1244, 1246) allocated to an execution thread of a plurality of execution threads; the processor further comprising: a single-thread interface coupled to the plurality of processing units, the smgle-thread interface being shared among threads and maintaining thread compatibility by physical duplication of structures and by verifying communication status after thread transfer.
7. A processor according to any of Claims 1-6 further comprising: a smgle-thread cache (710, 712) coupled to the multiple-thread execution pipeline so that the plurality of execution pathways converge into the smgle-thread of the cache, the smgle-thread cache being shared among threads and maintaining thread compatibility by segregation of the cache into N parts.
8. A processor according to Claim 7 wherein: cache segregation separates the cache into N independent parts that are allocated to threads to avoid pollution, "cross-talk", and interference between threads.
9. A processor according to either Claim 7 or Claim 8 wherein the cache includes: a cache index (812) that allocates the threads into the N independent cache parts.
10. A processor according to Claim 9 wherein: the cache index includes a bit field allocated to received thread identification (TID) bits indicative of a part of the N parts of the segregated cache.
11. A processor according to any of Claims 7- 10 further comprising: a thread switch logic (612) coupled to the multiple-thread execution pipeline and coupled to the cache, the thread switch logic controlling thread selection and generating a thread identifier (TID) indicative of the selected thread.
12. A processor according to any of Claims 7-11 further comprising: a thread switch logic coupled to the multiple-thread execution pipeline and coupled to the cache, the thread switch logic controlling thread selection and generating a thread identifier (TID) indicative of the selected thread; and a thread control logic coupled to the thread switch logic and supporting lightweight processes and native threads, the thread control logic disabling thread ID tagging and disabling cache segregation for lightweight processes and native threads that share a single virtual tag space.
13. A processor according to any of Claims 1-12 wherein: the multiple-thread execution pipeline includes a plurality of pipelines respectively allocated to a plurality of execution threads, the multiple-thread execution pipeline including storage elements for holding the plurality of threads, the processor further comprising: a plurality of shared components coupled to the multiple-thread execution pipeline, the shared components being coupled in a sequence so that the plurality of pipelines converge into the sequence of shared components, the shared components being logic components that control but do not hold threads.
14. A processor according to Claim 13 wherein: the plurality of shared components are selected from among components including a memory management unit (MMU) (320, 330), a branch prediction unit, a next-fetch random access memory (RAM).
15. A processor according to either Claim 13 or Claim 14 further comprising: a cache control unit coupled to the multiple-thread execution pipeline; an LI cache coupled to the cache control unit; and anti-aliasing logic coupled to the LI cache so that the LI cache is shared among threads via anti-aliasing.
16. A processor according to Claim 15 wherein: the LI cache is a virtually-indexed, physically-tagged cache that is shared among threads; and the anti-aliasing logic avoids hazards that result from multiple virtual addresses mapping to one physical address, the anti-aliasing logic selectively invalidating or updating duplicate LI cache entries.
17. A processor according to Claim 15 wherein- the LI cache is a virtually-indexed, physically-tagged cache that is shared among threads; and the anti-aliasing logic includes logic supporting lightweight processes and native threads that disables thread ID tagging and disables cache segregation.
18. A processor according to Claim 15 wherein: the anti-aliasing logic avoids hazards that result from multiple virtual addresses mapping to one physical address.
19. A processor according to any of Claims 13-18 further comprising: a cache coupled to the multiple-thread execution pipeline, the cache including cache indexing logic; and a cache control unit coupled to the cache, the cache control unit segregating the cache segregation by separating the cache mto N independent parts that are allocated to threads to avoid pollution, "cross-talk", and interference between threads.
20. A processor according to any of Claims 1-19 wherein: the multiple-thread execution pipeline includes a plurality of pulse-based high-speed flip-flops (400), the pulse-based high-speed flip-flops having a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads.
21. A processor according to any of Claims 1-20 further comprising. a smgle-thread interface including a load buffer and a store buffer that maintain compatibility with multiple threads so that, on a thread switch, the smgle- thread interface receives a new thread and maintains the state of a shared structure m a manner that is compatible with the replaced thread.
22. A processor according to any of Claims 1-21 further comprising: a smgle-thread interface including a load buffer and a store buffer that maintain compatibility with multiple threads by checking read-after-write status of the load buffer and the store buffer.
23 A processor according to any of Claims 1-22 further comprising. a smgle-thread interface including a load buffer and a store buffer that maintain compatibility with multiple threads by checking load operations against contents of a store buffer m an alternative thread so that read-after-wπte status information is stored and augmented to store results of read-after-wπte checks against content of all store buffers.
24. A processor according to any of Claims 1-23 further comprising: a smgle-thread interface that identifies a tag using a thread identifier (TID) tag.
25. A processor according to any of Claims 1-24 further comprising: a smgle-thread interface that is selected from among devices including caches, translation look-aside buffers, load buffer asynchronous interfaces, store buffer asynchronous interfaces, and memory management units.
26. A processor according to any of Claims 1-24 further comprising: a smgle-thread interface that is selected from among non-stallmg devices including caches, translation look-aside buffers, load buffer asynchronous interfaces, store buffer asynchronous interfaces, and memory management units.
27. A processor according to any of Claims 1-26 further comprising. a plurality of multiple-thread execution pipelines and a smgle-thread interface integrated onto a single mtegrated-circuit chip
28. A method of operating a processor compπsmg: executing a plurality of execution threads (310, 312) in a multiple-thread execution pipeline (314); respectively allocating pathways of the multiple-thread execution pipeline to the plurality of execution threads, sharing a smgle-thread interface among threads, comprising. allocating a plurality of execution pathways respectively to a plurality of independent execution threads (310, 312) extending to a plurality of pipeline registers; stoπng functional properties of an independent execution thread state throughout the pipeline extending to the pipeline registers; postponing execution of a stalling thread; relinquishing the pipeline to a previously idle thread; and later resuming execution of the postponed stalling thread at the precise state of the stalling thread immediately prior to switching of the thread; and maintaining thread compatibility by: physically duplicating structures; and veπfying communication status after thread transfer.
29. A method of operating a processor according to Claim 28 further compπsmg: converging the plurality of execution pathways converge into the smgle-thread of a single-thread cache; sharing the smgle-thread cache among threads; and maintaining thread compatibility by segregation of the cache into N parts.
PCT/US2000/012800 1999-05-11 2000-05-09 Multiple-thread processor with single-thread interface shared among threads WO2000068778A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/309,734 1999-05-11
US09/309,734 US6542991B1 (en) 1999-05-11 1999-05-11 Multiple-thread processor with single-thread interface shared among threads

Publications (4)

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WO2000068778A2 WO2000068778A2 (en) 2000-11-16
WO2000068778A3 WO2000068778A3 (en) 2001-08-09
WO2000068778B1 true WO2000068778B1 (en) 2001-10-04
WO2000068778A9 WO2000068778A9 (en) 2002-04-04

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WO (1) WO2000068778A2 (en)

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