WO2000070446A3 - Method and apparatus for loose register encoding within a pipelined processor - Google Patents

Method and apparatus for loose register encoding within a pipelined processor Download PDF

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Publication number
WO2000070446A3
WO2000070446A3 PCT/US2000/013198 US0013198W WO0070446A3 WO 2000070446 A3 WO2000070446 A3 WO 2000070446A3 US 0013198 W US0013198 W US 0013198W WO 0070446 A3 WO0070446 A3 WO 0070446A3
Authority
WO
WIPO (PCT)
Prior art keywords
disclosed
encoding
register
aforementioned
operations
Prior art date
Application number
PCT/US2000/013198
Other languages
French (fr)
Other versions
WO2000070446A2 (en
Inventor
Peter Warnes
Carl Graham
Original Assignee
Arc Internat U S Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/418,663 external-priority patent/US6862563B1/en
Application filed by Arc Internat U S Holdings Inc filed Critical Arc Internat U S Holdings Inc
Priority to AU48481/00A priority Critical patent/AU4848100A/en
Priority to EP00930707A priority patent/EP1194835A2/en
Publication of WO2000070446A2 publication Critical patent/WO2000070446A2/en
Publication of WO2000070446A3 publication Critical patent/WO2000070446A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30156—Special purpose encoding of instructions, e.g. Gray coding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines

Abstract

An improved method and apparatus for implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of 'loosely' encoding register numbers to indicate register immediate data operand usage is disclosed. One embodiment comprises instruction words having multi-bit data fields defined therein which encode various types of immediate operands. Such multi-bit field definitions provide the programmer with additional flexibility in performing a variety of operations, including non-commutative operations. A method of synthesizing a processor design incorporating the aforementioned 'loose' register encoding is also disclosed. Exemplary gate logic synthesized using the aforementioned method, and a computer program and system capable of implementing these methods are further disclosed.
PCT/US2000/013198 1999-05-13 2000-05-12 Method and apparatus for loose register encoding within a pipelined processor WO2000070446A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU48481/00A AU4848100A (en) 1999-05-13 2000-05-12 Method and apparatus for loose register encoding within a pipelined processor
EP00930707A EP1194835A2 (en) 1999-05-13 2000-05-12 Method and apparatus for loose register encoding within a pipelined processor

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US13425399P 1999-05-13 1999-05-13
US60/134,253 1999-05-13
US09/418,663 US6862563B1 (en) 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design
US09/418,663 1999-10-14
US52417800A 2000-03-13 2000-03-13
US09/524,178 2000-03-13

Publications (2)

Publication Number Publication Date
WO2000070446A2 WO2000070446A2 (en) 2000-11-23
WO2000070446A3 true WO2000070446A3 (en) 2002-02-07

Family

ID=27384546

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/013198 WO2000070446A2 (en) 1999-05-13 2000-05-12 Method and apparatus for loose register encoding within a pipelined processor

Country Status (5)

Country Link
EP (1) EP1194835A2 (en)
CN (2) CN1198208C (en)
AU (1) AU4848100A (en)
TW (1) TW482978B (en)
WO (1) WO2000070446A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6862563B1 (en) 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
AU2001243463A1 (en) 2000-03-10 2001-09-24 Arc International Plc Memory interface and method of interfacing between functional entities
US7734898B2 (en) 2004-09-17 2010-06-08 Freescale Semiconductor, Inc. System and method for specifying an immediate value in an instruction
US8127117B2 (en) * 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
GB2461849A (en) * 2008-07-10 2010-01-20 Cambridge Consultants Push immediate instruction with several operands
CN106462214B (en) 2014-05-07 2019-07-12 马维尔国际贸易有限公司 Low-power distributed memory network
GB2569098B (en) * 2017-10-20 2020-01-08 Graphcore Ltd Combining states of multiple threads in a multi-threaded processor
CN113656071B (en) * 2021-10-18 2022-02-08 深圳市智想科技有限公司 RISC architecture based CPU instruction set system and CPU system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489266A2 (en) * 1990-11-07 1992-06-10 Kabushiki Kaisha Toshiba Computer and method for performing immediate calculation by utilizing the computer
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
GB2309803A (en) * 1996-02-01 1997-08-06 Advanced Risc Mach Ltd Processing cycle control in data processing apparatus
US5774687A (en) * 1994-09-26 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Central processing unit detecting and judging whether operation result executed by ALU in response to a first instruction code meets a predetermined condition
EP0871108A1 (en) * 1991-03-11 1998-10-14 Silicon Graphics, Inc. Backward-compatible computer architecture with extended word size and address space

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU5550194A (en) * 1993-09-27 1995-04-18 Giga Operations Corporation Implementation of a selected instruction set cpu in programmable hardware
CN1187255A (en) * 1995-06-07 1998-07-08 高级微型器件公司 Microprocessor using instruction field to specify expanded functionality
SE505783C2 (en) * 1995-10-03 1997-10-06 Ericsson Telefon Ab L M Method of manufacturing a digital signal processor
DE69723804T2 (en) * 1996-05-15 2004-05-27 Trimedia Technologies, Inc., Sunnyvale PROCESSOR WITH COMMAND Cache
GB2317464A (en) * 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Register addressing in a data processing apparatus
US5890008A (en) * 1997-06-25 1999-03-30 Sun Microsystems, Inc. Method for dynamically reconfiguring a processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489266A2 (en) * 1990-11-07 1992-06-10 Kabushiki Kaisha Toshiba Computer and method for performing immediate calculation by utilizing the computer
EP0871108A1 (en) * 1991-03-11 1998-10-14 Silicon Graphics, Inc. Backward-compatible computer architecture with extended word size and address space
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
US5774687A (en) * 1994-09-26 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Central processing unit detecting and judging whether operation result executed by ALU in response to a first instruction code meets a predetermined condition
GB2309803A (en) * 1996-02-01 1997-08-06 Advanced Risc Mach Ltd Processing cycle control in data processing apparatus

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HELBIG W ET AL: "A DCFL E/D-MESFET GAAS EXPERIMENTAL RISC MACHINE", IEEE TRANSACTIONS ON COMPUTERS,US,IEEE INC. NEW YORK, vol. 38, no. 2, 1 February 1989 (1989-02-01), pages 263 - 274, XP000069984, ISSN: 0018-9340 *
MAY D ET AL: "THE TRANSPUTER", NEURAL COMPUTERS. NEUSS, SEPT. 28 - OCT. 2, 1987, PROCEEDINGS OF THE NATO ADVANCED WORKSHOP ON NEURAL COMPUTERS, BERLIN, SPRINGER, DE, 28 September 1987 (1987-09-28), pages 477 - 486, XP000410440 *

Also Published As

Publication number Publication date
AU4848100A (en) 2000-12-05
CN1661547A (en) 2005-08-31
WO2000070446A2 (en) 2000-11-23
TW482978B (en) 2002-04-11
CN100351782C (en) 2007-11-28
EP1194835A2 (en) 2002-04-10
CN1198208C (en) 2005-04-20
CN1384934A (en) 2002-12-11

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