WO2000070671A1

WO2000070671A1 - Mounting arrangement for a semiconductor element

Info

Publication number: WO2000070671A1
Application number: PCT/SE2000/000977
Authority: WO
Inventors: Leif Bergstedt; Katarina Boustedt
Original assignee: Telefonaktiebolaget Lm Ericsson
Priority date: 1999-05-17
Filing date: 2000-05-17
Publication date: 2000-11-23
Also published as: SE9901781L; SE523164C2; AU4967500A; SE9901781D0

Abstract

A mounting arrangement is proposed wherein a semiconductor element (10, 50) containing integrated circuitry has solder bumps (20) for electrically coupling the IC to a PCB (40) also comprises a number of further raised members (30) of larger volume than the solder bumps, at least one of which is electrically insulated from the IC. The raised members are solder masses that when heated will reflow only onto designated locations on the PCB. During mounting, the raised member will pull the semiconductor element into correct alignment with the receiving surface, allowing easy automatic mounting of the chip using flip-chip techniques regardless of the arrangement of the connection bumps. The raised members also alleviate the effects of thermal expansion mismatch between the chip and PCB by absorbing the predominant proportion of the resulting stress. A chip scale package is further proposed wherein a carrier (60) is applied to the upper surface of the chip (50) and the raised members are applied to the underside of the carrier.

Description

Mounting arrangement for a semiconductor element

Field of invention

The invention relates to an arrangement for mounting a semiconductor element on a receiving surface, such as a printed circuit board. It has particular application to semiconductor chips that cannot easily be mounted automatically using flip-chip techniques because they dispose of too few solder bumps or have bumps that are unevenly distributed across the surface of the chip, and also to chips that are thin and fragile.

Background art

There are numerous conventional methods for mounting a semiconductor chip on a printed circuit board (PCB) or thin-film or thick-film circuit. Common techniques involve the encapsulation of the chip in a package with connections between the chip and the substrate of the package usually being performed by wirebonding, thermo-compression, soldering or a combination of these. An example of such a package is described in EP-A-0 724 290. The advantage of such packages is that the arrangement of pins or connection points on the package is independent of the disposition of the circuit on the chip. In other words, when the arrangement of a circuit on a chip constrains the various input and output connections to be disposed asymmetrically, the package pins can nevertheless be designed to have a regular arrangement. The package may thus be easily mounted automatically in conventional assembly lines, for example.

However, these packages are bulky, preventing miniaturisation of the circuit as a whole. They are also complex to manufacture, as electrical connections between the chip and the pins must be established. Small size packages, generally termed chip scale packages (CSP), also exist wherein a chip may be mounted on a circuitized substrate that is barely laiger than the chip itself. Examples of such CSP are described in JP-A-9199540 and JP-A-9129679. Such packages also serve as adapters by allowing substantially any circuit configuration to be mounted in conventional circuit board arrangements, and have the advantage that they take up considerably less room. However, these packages also share the disadvantage of a complex manufacturing process.

In order to mount IC chips directly on the receiving circuit, flip-chip techniques may be used. This generally involves solder balls being bonded directly to exposed or deposited connection pads on the chip. The chip is then flipped over for mounting on the PCB or other receiving surface. US 5,569,960 describes such an arrangement. According to this document, the solder balls may vary in shape from a so-called 'hand drum shape' which has a narrow waist to a rounder shape that is closer to a sphere. This is achieved by either varying the diameters of connection pads on the chip and the receiving surface or alternatively by varying the volume of solder utilised. However, when the connections on a chip are not symmetrical, for example when very few connections are present and these are arranged predominantly on one side of the chip, as is frequently the case for chips designed for microwave applications, for example, the positioning of the chip with all connections aligned is not easily accomplished. Consequently the mounting process is difficult and laborious and the resulting electrical connections often unreliable.

It is thus an object of the invention to provide a mounting arrangement that overcomes the disadvantages of prior art techniques.

It is a further object of the invention to provide a mounting arrangement that enables semiconductor elements to be mounted with ease using flip-chip techniques, that is simple to implement and provides reliable connections even when performed automatically.

SUMMARY OF INVENTION According to the present invention a mounting arrangement is proposed wherein a semiconductor element containing an integrated circuit and having at least one connection bump for directly electrically coupling the integrated circuit on said element with a receiving PCB or like surface has at least one further raised member of a larger volume than the connection bump that is adapted to bond mechanically with a corresponding predetermined location on receiving surface. At least one of these raised members is not electrically connected to the integrated circuitry, and is thus electrically insulated from the this integrated circuitry. The raised members are preferably a solder mass that when heated will reflow only onto designated locations on the receiving surface. As a result of the larger mass, the raised members will effectively pull the semiconductor element into correct alignment with the receiving surface, regardless of the position of the connection bump.

The increased volume of the raised members also alleviates the effects of any mismatch between the coefficients of thermal expansion of the semiconductor element and the receiving surface. Such a mismatch will subject the connection bumps to shearing forces as the circuit heats up during use. The larger volume of the raised members is able to take up most of this force thus preventing, or substantially alleviating, fatigue damage of the connecting bumps over time.

According to a further embodiment of the invention a package is proposed that comprises a semiconductor element having connection bumps on one surface for directly electrically coupling the circuitry integrated in the element with a receiving surface, and a substantially planar carrier applied to the opposite surface. The carrier is dimensioned to extend beyond the edge of the semiconductor element at least on one side. At least one raised member of larger volume than said connection bumps is coupled to this projecting portion of the carrier for coupling the carrier to the receiving surface. Preferably the earner extends beyond the semiconductor element on all sides and a raised member is disposed at each corner of the carrier. The carrier conveniently serves as a ground plane for the semiconductor element, with the raised members electrically coupling the ground plane to the receiving surface. The carrier may also serve as a heat sink. By virtue of the stiffening effect of the carrier and the automatic alignment attainable with the larger mass of solder provided by the raised members, this arrangement allows even thin or fragile semiconductor elements such as GaAs chips to be mounted reliably and easily using flip-chip techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages of the present invention will become apparent from the following description of the preferred embodiments that are given by way of example with reference to the accompanying drawings, in which:

Fig. 1 shows a plan view of the underside of a silicon chip incorporating the mounting arrangement in accordance with a first embodiment of the present invention;

Fig. 2 depicts a side view of the silicon chip of Fig. 1 mounted on a receiving surface in accordance with the present invention.

Fig. 3 shows a side view of a GaAs chip applied to a carrier, both being mounted on a receiving surface in accordance with a further embodiment of the present invention; Fig. 4 shows a plan view of the underside of the carrier of Fig. 3; and

Fig. 5 shows a GaAs chip with carrier mounted on a receiving surface in accordance with a still further embodiment of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

Fig. 1 shows the underside of a semiconductor element or chip 10 that carries some form of integrated circuit (IC). In this embodiment, the IC chip is structurally quite strong; a typically material for the IC chip is silicon.

Electrodes are provided on the surface of the chip for connecting the integrated circuit with external contacts such as on a printed circuit board. The electrodes consist of metallic conductive pads exposed, or deposited on, the surface of the chip and may comprise, but are not limited to gold, aluminium or copper. The techniques for fabricating these conductive pads are well known in the art and will not be described further here. The electrical connection between the electiodes and PCB is accomplished by means of soldering using raised solder projections, conventionally called bumps or balls 20. The arrangement of these bumps 20, or rather the conductive pads on the surface of the chip, is deteraiined by the configuration of the integrated circuit.

Thus while some effort may be made to distribute the bumps 20 uniformly over the surface of the chip 10, circuit design considerations may render this difficult, if not impossible. The bumps 20 are generally first bonded to the IC chip 10, and the chip 10 subsequently applied to the desired receiving surface 40, which may be a PCB or thick film or thin film circuit (see Fig. 2). The receiving surface carries corresponding conductive pads for establishing electrical contact with the solder bumps.

To facilitate the mounting of the IC chip 10 on the receiving surface 40, an arrangement of further projections 30 is also provided on the underside of the IC chip 10. In order to more easily distinguish these projections 30 from the connection bumps 20 the term "positioning bumps" will be used. However, as will become apparent from the subsequent description, the bumps 30 have more than just a positioning function. These positioning bumps 30 are preferably of a metallic solder material but are of larger volume than the connecting bumps 20 with the ratio of volume of positioning bumps 30 to connection bumps 20 preferably lying within the range of about 2 to 10. The positioning bumps 30 are bonded to metallic or other suitable pads provided on the IC chip. Corresponding well defined wetable areas also preferably in the form of metallic pads (not shown) are likewise provided on the receiving surface 40. Due to the larger volume of the positioning bumps 30, the metallic pads on the receiving surface 40 will be of correspondingly larger area than the conductive pads provided for the connecting bumps 20. The surface tension of metal-based solder allows it to melt only onto metal. Thus, when the IC chip is applied to the receiving surface 40, and the positioning bumps

30 heated until the solder reflows, the bumps 30 will automatically seek the corresponding metallic pads. As a result, the positioning bumps 30 will actively pull the IC chip into correct alignment with the conductive pads on the receiving surface. By virtue of the larger size of the metallic pads that mate with the positioning bumps, i.e. the larger contact area provided for the positioning bumps 30 on the receiving surface, the alignment is greatly facilitated and occurs practically automatically. In fact, the relatively large volume of solder provided by the positioning bumps create a greater alignment force than would be possible with the connection bumps alone.

In the embodiment shown in Figs. 1 and 2, the connection bumps 20 and positioning bumps 30 are substantially cylindrical in shape and of equal height when the IC chip is bonded to the receiving surface 40. Hence with the preferred volume ratio mentioned above, the contact surface between the positioning bumps 30 and the corresponding connection pads will be between about 2 and 10 times the area of the contact surface for the connection bumps 20. It should be mentioned that the solder bumps may initially be applied as spherical balls as is common in the art. They will then adopt a substantially cylindrical shape when the solder reflows on heating and providing that the metallic and conductive pads on the receiving PCB 40 are of the correct size.

It will be appreciated that a true cylindrical form cannot be achieved in practice. A more likely form for the positioning bumps 30 would be barrel- shaped.

The choice of solder for the connection and positioning bumps and any solder paste that may be used is determined in part by the material forming the metallic pads on the receiving surface 40 and underside of the chip 10. Preferred materials include gold, tin and indium, and alloys of these.

However while the preferred material for the positioning bumps 30 is metallic solder, the invention is not limited to this. Specifically, metals that are not good electrical conductors or a non-metallic conductive material, such as a polymer, could be utilised. Indeed, the positioning bumps could be made from a non-conducting material, such as a resin, for example. Naturally, for the alignment action of the positioning bumps 30 to be retained, the corresponding pads provided on the receiving surface should be of a material that can be readily wetted by the positioning bump material.

The positioning bumps 30 are located on the IC chip in such a manner that they provide a stable structure for supporting the IC chip 10. This is possible, since the location of the positioning bumps 30 is not dictated by the configuration of the integrated circuit on the IC chip 10. Unlike the connecting bumps 20, the positioning bumps 30 are not directly electrically connected to the circuitry integrated in the chip 10. The corresponding connecting pads may thus be disposed so as to obtain a uniform distribution of mechanical connecting points. In particular, the positioning bumps 30 serve as a platform to hold the IC chip substantially parallel to the receiving surface so that reliable connections may be established between all connection bumps 20 and the corresponding conductive pads provided on the receiving surface 40. PrefeiTed arrangements include a lattice (commonly referred to as an area array) or zig-zag arrangement. In a highly preferred embodiment, positioning bumps 30 are disposed at the edges of the chip 10, and more preferably at each corner. This allows excellent stability to be attained. However, it will be appreciated that in some circumstances a single positioning bump may be all that is required to accurately align the IC chip on the receiving surface.

Specifically, this might be the case when the existing connection bumps are disposed in an arrangement that provides an almost stable structure for supporting the chip 10.

While the alignment function of the positioning bumps 30 caused by the reflow of the positioning bump 30 material or solder paste is an important and desirable feature of the described arrangement, positioning bumps 30 may be utilised in applications where only the added stability is required. In such a case, the reflow of solder or solder paste can be dispensed with and the bonding between positioning bumps 30 and the receiving surface 40 be accomplished using thermo-compression. Such a technique would also allow metals or other materials to be used for the positioning bumps 30 which have a very high melting point.

When made of an electrically conducting material, one or more of the positioning bumps 30 may conveniently also be utilised as ground connections for the IC chip 10, providing the IC configuration permits this. In general, however, at least one positioning bump will not be electrically connected to the lC. The positioning bumps 30 serve a further puipose. In operation, the chip will heat up. The receiving surface, which generally will also contain at least passive ciicuit components, will also heat up. Both the IC chip and the receiving surface will undergo expansion on heating, with the coefficient of thermal expansion (CTE) depending on the respective materials. While the materials for both the IC chip and the receiving surface are preferably chosen to have similar CTEs, a degree of thermal expansion mismatch is inevitable. This will manifest itself in a shearing force experienced by the solder connections 20, 30. As a result of their larger volume and mass, the positioning bumps 30 are able to take up a greater proportion of this force, and in this way substantially reduce the thermal stress suffered by the connection bumps. The effects of a thermal expansion mismatch will inevitably be greater at the edges of the IC chip 10 than in the centre, and the greatest effects will be felt at the corners of the IC chip 10. It is thus preferred that the positioning bumps 30 be located substantially at the corners of the IC chip as shown in Figs. 1 and 2.

While the connection and positioning bumps 20, 30, shown in Figs. 1 and 2 are substantially cylindrical when bonded to the receiving surface 10, it will be appreciated that the solder bumps 20, 30 may be allowed to retain their spherical shape by utilising a solder paste which locks at a lower temperature than the reflow temperature of the solder bumps themselves. As mentioned above, this may also be accomplished by bonding the positioning bumps 30 to the receiving surface 40 by thermo-compression, although no alignment force is generated using this technique. It is further possible that solder paste could be utilised with the positioning bumps 30 to augment their volume for any particular application. When both connection and positioning bumps 20, 30 are bonded using solder paste, it is preferred that a paste be used for the positioning bumps that is less dispensed than that for the connection bumps 20, and therefore locks at a slightly higher temperature. This will ensure that the positioning bumps remain higher and retain the desired standoff of the chip 10 away from the receiving surface 40.

A further embodiment of the present invention is shown in Figs. 3 and 4. In these figures, those parts already described with reference to Figs. 1 and 2 are designated by like reference numerals.

Fig. 4 shows a further IC chip 50 that is mounted on a receiving surface 40 and electrically connected to the receiving surface using connecting solder bumps 30 bonded to the underside of the IC chip 50. A carrier 60 is joined to the top side of the IC chip 50 by a solder joint 51. The carrier 60 serves as a stiffener for the IC chip 50 and is substantially planar, at least on the major side joined to the IC chip 50; this arrangement is thus particularly well suited to highly fragile semiconductor components such as a GaAs chip, which can be particularly thin and susceptible to breakage. The carrier 60 may also serve to distribute heat generated by the chip 50, wherein it would be made of a suitable material. The carrier is slightly larger than the IC chip 50 and extends outwardly beyond the chip 50 at least on one side. In the arrangement depicted in Figs. 3 and 4 the carrier 60 extends beyond the chip 50 on all sides, but by a smaller margin on one pair of opposing sides than on the other. In this arrangement, the positioning bumps 30 are not provided on the IC chip but on the carrier 60. Specifically, the positioning bumps 30 are located on the underside of the carrier 60 essentially in the corner areas of the same. The underside of the carrier is shown in Fig. 4. This essentially consists of a mask 61 of insulating material through which metallic areas are visible. These metallic areas include a substantially rectangular exposed area 62 positioned centrally on the carrier 60 for receiving the IC chip 50, and roughly circular exposed metallic areas 63 for bonding with the positioning bumps 30 either with or without the intermediary of a suitable solder paste. In many applications it may be preferable that the carrier 60 carries no current. However for high speed applications, e.g. radio frequency applications, the carrier 60 may incoiporate, or serve as, a ground plane for the chip 50. The exposed areas 63 for bonding with the positioning bumps 30 will then be electrically connected to the ground plane so that the positioning bumps 30 also serves as ground connections.

In this embodiment, the positioning bumps 30 are not only of greater diameter than the connection bumps 20 but are also higher. The structure as a whole is effectively a chip scale package (CSP) with the IC chip 50 directly electrically connected to the receiving surface 40 by connection bumps 20. By virtue of the carrier 60, the structure is robust, but the IC chip is not encapsulated thus permitting mounting using flip-chip techniques. Accurate and reliable alignment of the chip on the receiving surface 40 is enabled by the positioning bumps 30 in the same manner as described with reference to the embodiment of Figs. 1 and 2.

When the chip 50 is thin compared to the carrier, the carrier 60 is selected to have essentially the same coefficient of thermal expansion (CTE) as the IC chip 50. If the chip 50 is thicker, and thus more robust, the CTE of the carrier 60 and the chip 50 may differ somewhat without the chip 50 suffering adverse effects. It will be appreciated that the effective CTE of the package relative to the receiving surface 40 will depend on the relative thickness of the carrier 60 and chip 50. Thus CTE of the package will be determined by the carrier material if the chip is thin compared to the carrier 60; the opposite is true if the carrier is relatively thin. As for the embodiment of Figs. 1 and 2, the positioning bumps 30 absorb the bulk of the shearing forces resulting from a CTE mismatch between package and receiving surface 40.

It is also possible in this arrangement that at least one positioning bump be provided on the IC chip 50 itself in an analogous manner to that shown in Figs. 1 and 2. Such a bump would naturally be dimensioned to hold the chip 50 from the receiving surface 40 by substantially the height of the connection bumps 20.

In the arrangement shown in Fig. 3, both the connection bumps 20 and positioning bumps 30 are essentially spherical when bonded to the receiving surface 40. As a result, the connection bumps 20 tend to exert an upward force on the IC chip 10. The positioning bumps counteract this force by pulling the carrier 60 downwards. This compression force is substantially increased by altering the shape of the bonded positioning bumps 30. This arrangement is shown in Fig. 5.

In Fig. 5 the positioning bumps 30 are essentially hour-glass shaped with the diameter in the centre of the bumps 30, i.e. midway between the receiving surface 40 and the carrier 60, being about 80% of the diameter at the metallic pads. This shape inherently comprises compressor forces and is designed to counteract the upward forces of the spherical connection bumps 20 by pulling the carrier 60 towards the receiving surface 40. This shape is formed by suitably dimensioning the metallic pads on receiving surface 40 and carrier underside 60 and providing the correct volume of solder, either as a solder ball or by supplementing the mass with solder paste. Since the solder will melt fully onto the metallized areas provided, the desired shape should form naturally.

While the balance of forces described above will hold true for lower temperatures, when the temperature is raised, the positioning bumps will expand. This is illustrated in the following example, which is given with reference to the structure shown in Fig. 5.

Example The positioning bumps 30 are considered to have a height of 247μm with an expansion value of 27 ppm.

The expansion of the positioning bumps must be compared with that of the connection bump chain, which is composed as follows:

In a worst case scenario it is assumed that the device has a cold start at -45 °C with all elements in balance. The initial tensioning effect is eliminated. It is further assumed that the connection bumps 20 will be about 20 °C wanner than the positioning bumps 50.

Thus a feasible working temperature would be about 80 °C for the connection bumps 20 and 60 °C for the positioning bumps 30.

At these temperatures, the positioning bumps will have expanded by 0.70 μm, and the connection bump chain will have expanded by 0.34 μm.

An excess expansion of 0.36 μm must therefore be absorbed by the gold connection bump 20 and its soldering. Since these together constitute a structure of 100 μm, an expansion of 0.36% must be absorbed which is considered entirely feasible.

In all the embodiments described above it, but particularly that shown in Fig. 5, it is conceivable that the connection bumps 20 are not soldered at all, but that a reliable dry connection can be adequately ensured by means of the compressor forces of the positioning bumps 30. The feasibility of such an arrangement will naturally depend on the application. For example, some high frequency applications may require a wet connection.

Claims

Claims:

1. A mounting anangement for a semiconductor element (10, 50) containing integrated circuitry and having on one surface at least one connection bump (20) for electrically coupling the integrated circuitry on said semiconductor element (10, 50) directly to a receiving surface (40), characterised by at least one raised member (30) having a larger volume than said connection bump (20) and being disposed to bond with predetermined locations on the receiving surface (40) for coupling said semiconductor element (10, 50) with said receiving surface (40), wherein at least one of said raised members (30) is electrically insulated from said integrated circuitry on said semiconductor element (30).

2. A mounting anangement as claimed in claim 1, characterised in that said at least one raised member (30) is disposed so as to enable accurate alignment of the semiconductor element (10, 50) on the receiving surface (40).

3. A mounting anangement as claimed in claim 1, characterised in that several raised members (30) are disposed in an anangement forming a stable platform for said semiconductor element (10, 50).

4. A mounting anangement as claimed in claim 3, characterised in that said raised members (30) are disposed in a lattice aπangement.

5. A mounting anangement as claimed in any one of claims 1 to 4, characterised in that said at least one raised member (30) includes a material adapted to flow at a predetermined temperature.

6. An anangement as claimed in any one of claims 1 to 5, characterised in that said at least one raised member (30) is disposed on the surface of said semiconductor element (10).

7. A mounting anangement as claimed in claim 6, characterised in that said at least one raised member (30) is disposed at an edge of said semiconductor element (10).

8. A mounting anangement as claimed in claim 6 or 7, characterised in that a raised member (30) is disposed at each corner of said semiconductor element (10).

9. An anangement as claimed in any previous claim, characterised in that a planar canier (60) of larger area than said semiconductor element (50) is mounted on said semiconductor element (50) on a surface opposite said one surface, and at least one raised member (30) is disposed on said canier (60) for coupling said canier to said receiving surface (40).

10. An anangement as claimed in claim 9, characterised in that said canier (50) serves as a ground plane for said semiconductor element (50), wherein said at least one raised member (30) electrically couples said ground plate to said receiving surface (40).

11. An anangement as claimed in claim 9 or 10, characterised in that a raised member (30) is disposed at each corner of said carrier (60).

12. An anangement as claimed in any one of claims 9 to 11, characterised in that said canier (60) is a heat distributing plate.

13. An aπangement as claimed in any previous claim, characterised in that said at least one raised member (30) is dimensioned to form an hour- glass shape when bonded with said receiving surface (40).

14. An aπangement as claimed in any previous claim, characterised in that said at least one connection bump (20) and said at least one raised member (30) are bonded to connection pads on said semiconductor element (10), wherein the connection pads for said connection bumps

(20) are of smaller diameter than the connection pads for said raised members (30).

15. An aπangement as claimed in any previous claim, chaiacterised in that the volume of said at least one raised member (30) is between 2 and 10 times the volume of said at least one connection bump (20).

16. A semiconductor package including a semiconductor element (50) containing integrated circuitry, connection bumps (20) disposed on one surface of said semiconductor element and electrically coupled to said integrated circuitry for establishing electrical contact with a receiving surface, chaiacterised by a substantially planar canier (60) disposed on, and bonded to, an opposite surface of said semiconductor element (50), and at least one raised member (30) of a larger volume than said connection bumps (20), said raised member (30) being disposed on said canier for coupling the canier (60) to the receiving surface (40).