WO2000070827A3 - Method and apparatus for a multi-gigabit ethernet architecture - Google Patents

Method and apparatus for a multi-gigabit ethernet architecture Download PDF

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Publication number
WO2000070827A3
WO2000070827A3 PCT/US2000/013584 US0013584W WO0070827A3 WO 2000070827 A3 WO2000070827 A3 WO 2000070827A3 US 0013584 W US0013584 W US 0013584W WO 0070827 A3 WO0070827 A3 WO 0070827A3
Authority
WO
WIPO (PCT)
Prior art keywords
frame
channels
channel
mini
collector
Prior art date
Application number
PCT/US2000/013584
Other languages
French (fr)
Other versions
WO2000070827A2 (en
Inventor
Shimon Muller
Ariel Hendel
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to EP00937585A priority Critical patent/EP1179248B1/en
Priority to DE60018559T priority patent/DE60018559T2/en
Priority to AU52733/00A priority patent/AU5273300A/en
Priority to JP2000619163A priority patent/JP4732594B2/en
Publication of WO2000070827A2 publication Critical patent/WO2000070827A2/en
Publication of WO2000070827A3 publication Critical patent/WO2000070827A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/14—Multichannel or multilink protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

An Ethernet architecture enables the transfer of data by striping individual frames across a plurality of logical channels, thus allowing operation at substantially the sum of the individual channel rates. A distributor within a sending entity's network interface distributes frame bytes in a round-robin fashion on the plurality of channels. Each mini-frame is separately framed and encoded for transmission across its channel. A receiving entity's network interface includes a collector for collecting multiple mini-frames and reconstructing the frame's byte stream. The first and last bytes of each frame and mini-frame are marked for ease of recognition. Multiple unique idle symbols may be employed for transmission during inter-frame gaps to facilitate the collector's synchronization of the multiple channels and/or enhance error detection. A maximum channel skew is specified, and each channel may be buffered with an elasticity proportional to the maximum skew so that propagation delay may be encountered between channels without disrupting communications.
PCT/US2000/013584 1999-05-19 2000-05-17 Method and apparatus for a multi-gigabit ethernet architecture WO2000070827A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP00937585A EP1179248B1 (en) 1999-05-19 2000-05-17 Method and apparatus for a multi-gigabit ethernet architecture
DE60018559T DE60018559T2 (en) 1999-05-19 2000-05-17 METHOD AND DEVICE FOR A MULTI-GIGABIT ETHERNET ARCHITECTURE
AU52733/00A AU5273300A (en) 1999-05-19 2000-05-17 Method and apparatus for a multi-gigabit ethernet architecture
JP2000619163A JP4732594B2 (en) 1999-05-19 2000-05-17 Method and apparatus for multiple gigabit ethernet architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/314,782 US6873630B1 (en) 1999-05-19 1999-05-19 Method and apparatus for a multi-gigabit ethernet architecture
US09/314,782 1999-05-19

Publications (2)

Publication Number Publication Date
WO2000070827A2 WO2000070827A2 (en) 2000-11-23
WO2000070827A3 true WO2000070827A3 (en) 2001-07-19

Family

ID=23221421

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/013584 WO2000070827A2 (en) 1999-05-19 2000-05-17 Method and apparatus for a multi-gigabit ethernet architecture

Country Status (6)

Country Link
US (1) US6873630B1 (en)
EP (1) EP1179248B1 (en)
JP (2) JP4732594B2 (en)
AU (1) AU5273300A (en)
DE (1) DE60018559T2 (en)
WO (1) WO2000070827A2 (en)

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Also Published As

Publication number Publication date
JP4732594B2 (en) 2011-07-27
AU5273300A (en) 2000-12-05
EP1179248A2 (en) 2002-02-13
JP5111591B2 (en) 2013-01-09
US6873630B1 (en) 2005-03-29
DE60018559T2 (en) 2006-04-13
WO2000070827A2 (en) 2000-11-23
JP2003500899A (en) 2003-01-07
DE60018559D1 (en) 2005-04-14
JP2011050099A (en) 2011-03-10
EP1179248B1 (en) 2005-03-09

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