WO2000079369A1

WO2000079369A1 - Clock distribution by radio waves

Info

Publication number: WO2000079369A1
Application number: PCT/US2000/016907
Authority: WO
Inventors: Jose M. Cruz; Hans Eberle
Original assignee: Sun Microsystems, Inc.
Priority date: 1999-06-22
Filing date: 2000-06-19
Publication date: 2000-12-28
Also published as: AU5625400A

Abstract

A clock distribution circuit for distributing a clock signal to a plurality of clocked circuits transmits a clock signal by radiating the clock signal through a medium, such as a gas, vacuum or transmissive solid or liquid. A plurality of clock receivers is positioned such that each of the plurality of clock receivers is coupled to one of the plurality of clocked circuits and the clock receiver receives the transmitted clock signal. The clocked circuits are circuits that typically require clock signals within a threshold range of offsets to operate as designed and the plurality of clock receivers are each positioned relative to the transmitter such that the range of times of flight for the radiated clock signal is within the threshold range. In some embodiments, the plurality of clocked circuits are on one integrated circuit substrate, while in other embodiments, the plurality of clocked circuits are distributed over a plurality of integrated circuit substrates. The plurality of clock circuits might be arranged along a plane with the transmitter positioned at a point off of the plane and separated by the plane by a transmitter distance greater than a largest distance between any two of the plurality of clocked circuits. To reduce the radiation of the clock signal beyond the clocked circuits, the clocked circuits and the transmitter could be mounted within a shielding enclosure.

Description

CLOCK DISTRIBUTION BY RADIO WAVES

BACKGROUND OF THE INVENTION

The present invention relates in general to clock distribution and in particular to high-speed clock distribution over a set of circuits requiring small skews in clocking from circuit to circuit in the set of circuits.

Clock distribution is a common design problem in high-speed circuits. The clock is a signal that controls the timing of various elements of a circuit. For example, a register might be configured to provide an output result at the falling edge of its local clock applied to a clock input of the register. If another circuit, such as an arithmetic logic unit (ALU) is connected to the register such that the ALU receives the output of the register and clocks the output of the register into the ALU according to a clock signal input at the ALU's local clock input, the local clock of the ALU and the local clock of the register should bear some known relationship, so that the ALU is not clocking in data when the register is changing its output.

If the clock being used by the register and the ALU are slow enough; say 30 MHz, then it is a simple matter to just connect the register clock input and the ALU clock input to a common clock signal. However, when the clock is much faster, such as 1 GHz, or higher, the relative distances between the clock signal source and the local clock inputs need to be taken into account. One way of handling clock distribution issues is to distribute the clock in such a way that the distance and loading of the lines from the clock source to each local clock input is the same. One such solution is shown in Fig. 1. In Fig. 1, a chip 10 having various clocked circuit elements (not shown) is clocked by a clock distribution system that distributes a clock signal generated by clock generator 12. As shown, the clock is derived from a crystal oscillator including crystal 14. A reference clock signal (at a low frequency, such as 30 MHz) is transmitted via a clock line 16 to a clock synthesizer 20. Clock synthesizer 20 generates a higher frequency clock signal and that clock signal is buffered through buffers 21 and distributed to local buffers 22 via distribution lines 24. The construction of clock synthesizer 20 is shown in Fig. 2, with a feedforward path comprising a phase detector 26, a low pass filter 27, a voltage controlled oscillator (NCO) 28 and a number of output buffers A feedback path is also provided, with a divider 29 coupled between the output of VCO 28 and a second input to phase detector 26 Using a suitable divider number m divider 29, the output frequency of clock synthesizer 20 is its input frequency times the divider number If a large number of loads need to be dπven by the clock signal, a network resembling a tree uses a hierarchy of dπvers to incrementally increase the fan-out If each signal passes through many dπvers, the skew between two clock signals due to differences in delays in the individual dπvers and differences in delays m the lines connecting the dπvers m the hierarchy might cause circuit problems, if the skew is large enough Even if clock skew does not cause a clocking error m a circuit, it does adversely affect a circuit because the circuit needs to be designed with the possible skew m mind and clock skew is time that could otherwise be used for computation or processing

Note that, as shown in Fig 1, the length of the distπbution line 24 to a local buffer 22 and the number of other loads on that distπbution line are the same for each local buffer 22 Because of this symmetry, the timing of the clock signal at the output of each local buffer 22 is the same. Of course, in practice, the lengths of the distπbution lines and the total load on the distπbution lines is not exactly equal for all local buffers 22, so there is some vaπation m the phase of the clock signal from local buffer to local buffer Also, in practice, local buffers 22 add some delay to the clock signals and this delay is not exactly equal for all local buffers 22, further increasing vaπations in the phase of the clock signals Such vaπations limit the speed at which a circuit could operate Another disadvantage of this approach to clock distribution is the amount of chip real estate that is needed for distπbution lines 24 Yet another disadvantage of this clock distπbution system is that it constrains the layout of the circuit elements on the chip, since each element that is clocked needs to be located near a local buffer

SUMMARY OF THE INVENTION A clock distπbution circuit according to one embodiment of the present invention overcomes the disadvantages of pπor art clock distπbution systems by distπbutmg a clock signal by radiating a clock signal from a transmitter to a plurality of local receivers, where a local receiver is relatively local to the circuit element or elements being clocked by that local receiver The transmitter transmits the clock signal to the receivers through a transmission medium, such as a gas. vacuum or transmissive solid or liquid

The clocked circuits are circuits that typically require clock signals within a threshold range of offsets to operate as designed and the plurality of clock receivers are each positioned relative to the transmitter such that the range of times of flight for the radiated clock signal is within the threshold range In some embodiments, the plurality of clocked circuits are on one integrated circuit substrate, while in other embodiments, the plurality of clocked circuits are distπbuted over a plurality of integrated circuit substrates The plurality of clock circuits might be arranged along a plane with the transmitter positioned at a point off of the plane and separated by the plane by a transmitter distance greater than a largest distance between any two of the plurality of clocked circuits To reduce the radiation of the clock signal beyond the clocked circuits, the clocked circuits and the transmitter could be mounted withm a shielding enclosure

A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawin 'Sgs^J

BRIEF DESCRIPTION OF THE DRAWINGS Fig 1 is a block diagram of a pπor art clock distπbution circuit Fig 2 is a schematic diagram of a pπor art clock synthesizer circuit Fig 3 is a block diagram of a clock distπbution circuit according to one embodiment of the present invention

Fig 4 is an illustration of one example of the placement of a transmitter relative to circuits being clocked by a clock signal transmitted by the transmitter

Fig 5 is a schematic diagram of one embodiment of a clock receiver accordmg to the present invention.

Fig 6 is a schematic diagram of another embodiment of a clock receiver accordmg to the present invention.

Fig 7 is an illustration of several antenna vaπations, Fig 7(a) shows a surface linear antenna, Fig 7(b) shows a surface loop antenna, Fig 7(c) shows bonding wire antennas, and Fig 7(d) shows standing wire antennas

Fig 8 is a schematic diagram of a specific implementation of a receiver for use m receiving a clock signal according to one embodiment of the present invention DESCRIPTION OF THE SPECIFIC EMBODIMENTS The following detailed descπption of specific embodiments including the preferred embodiments reference the accompanying drawings which form part of this disclosure The drawmgs illustrate examples of the embodiments and how the invention is practiced Without departing from the scope of the present invention, other embodiments may be used in place of those shown and descπbed, and such substitutions should be apparent to one of ordinary skill m the art upon reading this disclosure

In the prefeπed embodiment, a clock signal is distπbuted from a transmitter to a plurality of receivers with at least a portion of the distπbution path being the radiation of an electromagnetic signal from the transmitter to the receivers

Fig 3 illustrates a basic example of such a clock distπbution system for a chip 100 In that system, the clock to be distπbuted is generated by a clock generator circuit 102 and provided to a clock synthesizer 104, which outputs the clock signal to a transmitting antenna 106 In the specific example shown, the output of clock generator circuit 102 is about 100 MHz and the output of clock synthesizer 104 is about 2 GHz, as a result of the dιvιde-by-20 element of clock synthesizer 104 In other embodiments, the two frequencies could be different, so long as the transmitted frequency is a frequency that can be transmitted through the medium separating transmitting antenna 106 from chip 100 In a typical embodiment, the medium is air or vacuum m which electromagnetic wave can propagate. In other embodiments, the medium is a substance other than air that the waves propagate through The transmitted clock signal can be either evenly emanating from transmitting antenna 106 or it can be guided or limited, as is well known m the art of electromagnetic radiation transmission. Preferably, the transmitter and chip 100 are within an electromagnetic Faraday shield to keep the transmitted clock signal from interfering with circuitry external to chip 100

As illustrated m Fig. 3, the clock signal radiates from transmitting antenna 106 and is received at a plurality of receiving antennas 110 located on chip 100 near circrnt elements that are clocked by the transmitted clock As shown, a receiving antenna 110 receives the clock signal, processes it at a receiver 112 coupled to the receiving antenna 110 and provides the clock signal to a buffer 114, which in turn provides the clock signal to local circuit elements (not shown). In many cases, nothing special is needed for the transmitting antenna For example, at 2 GHz, most circuits radiate some signal, albeit as an undesired side effect of circuit operation. However, here that side effect is used as a benefit

Fig 4 shows a physical arrangement of the circuit elements of Fig 3 As shown there, transmitting antenna 106 is positioned above the plane of chip 100, with the width of chip 100 indicated by the distance dl and the distance between transmitting antenna 106 and chip 100 indicated by the distance d2 Preferably, the ratio of d2 to dl is high enough that the time -of- flight of the clock signal from transmitting antenna 106 to the center of chip 100 is not so much different from the time-of- flight of the clock signal from transmitting antenna 106 to the edge of chip 100 that timing problems occur in the circuit elements of chip 100 One example places transmitting antenna 106 10 cm above chip 100 when the width of the active area of chip 100 is 1 cm If the chip and antenna are centered relative to each other, then the ratio of the distance from the antenna to the center of the chip to the distance from the antenna to the edge of the chip is [(10^"2 + 0 5~2) ~(l/2)]/10 or about 1 0012 The maximum change in distance between antenna 06 and any point on the surface of chip 100 would be (1 0012-1) x 10 cm or about 120 μm This coπesponds to a maximum skew in the time of flight of the electromagnetic wave of 120 μm/(300 x 10⁶m/s) or about 0 3 ps, when the medium between the antenna and the chip is air or vacuum

Fig 5 is a schematic diagram of one embodiment for a receiver circuit 150 used for receiver 112 m the schematic of Fig 3 In that receiver circuit 150, a low noise amplifier (LNA) 151 receives the clock signal from the receiving antenna 110 and amplifies the clock signal. The amplified clock signal is applied to a chain of buffers 152, resulting m the local clock output to local circuit elements. In receiver circuit 150, the received clock is used directly, after amplification With direct use, the output of receiver circuit 150 might include some jitter introduced in each buffer 152 due to Vdd vaπations Fig 6 is a schematic diagram of another embodiment of a receiver circuit There, receiver circuit 160 uses the received clock signal as a phase reference for an internal oscillator Receiver circuit 160 compπses a phase detector, a low pass filter and a VCO The output of the VCO could be a 2 GHz, 1 V peak-to-peak clock signal, needing no amplification. This 1 V output clock is fed back to the phase detector that detects the phase difference between the input, unamplified clock and the output of the VCO One possible VCO that could be used as the VCO m receiver circuit 160 is the VCO shown in U.S Patent Application Seπal No 09/023,360, filed February 13, 1998 entitled "Low Phase Noise LC Oscillator for Microprocessor Clock Distπbution" That application is incorporated by reference herein for all purposes

Fig 7 illustrates several vaπations of receiver antennas that could be used as antenna 1 10 m Figs 3 and 5-6 Fig 7(a) illustrates the use of a surface linear antenna on the surface of a chip 170 The energy radiated from the transmitting antenna is induced on the two lines of the surface linear antenna, which could be two traces in a metal layer fabπcated on chip 170 Depending on the placement of the transmitting antenna and the voltage differential that needs to be induced between points SI and S2, the length (d3) of each line could be about 1 millimeter

For standard CMOS processes, the top metal layer (M3) would be typically used to make the planar antenna This reduces the parasitic capacitance between the antenna and the substrate For "sιlιcon-on-msulator" processes, all metal layers could be used simultaneously to reduce the parasitic resistance of the antenna Fig 7(b) illustrates a surface loop antenna, which might be used instead of the surface linear antenna where more signal power is needed or less chip real estate is available There, instead of two lines of an antenna, a trace 174 is looped to form the receiving antenna. To avoid a short, the inside of the loop connects to a point outside the loop by passing over an insulator 176 insulating the connector from the loop Fig. 7(c) illustrates another vaπation, the bonding wire antenna There, a bonding wire 178 is attached between two bonding pads 180 Bonding pads 180 are connected to the receiver (not shown) on a die surface 170, and can be connected using conventional pad-to-circuit trace techniques.

Fig. 7(d) illustrates the use of standing wire antennas 182 The standing wire antennas can be bonded over small mtemal pads. The standing wires can be vertical or tilted and can be straight or bent. One advantage of standing wire antennas over the bonding wire antennas shown m Fig. 7(c) is that half as many bonding pads are needed for a given number of antennas One advantage of nonplanar antennas such as those shown in Figs. 7(c)-(d) is that regardless of their wire length, they only use a small area of the surface of the chip (i.e the internal bonding pad, typically 20 μm x 20 μm). They also have lower losses due to lower wire resistance and lower capacitance to the substrate Fig 7(d) shows several vaπations of the basic standing wire antenna 182, such as a tilted standing wire antenna 191 or a bent standing wire antenna 192 Two bent standing wire antennas could be used as an elevated dipole antenna. Other vaπations will be apparent from this disclosure

Fig 8 is a schematic diagram of a specific implementation of a receiver for receiving a clock signal As shown there, an antenna structure 184 receives the radiated clock signal and provides it to an LNA 186, which provides one input for the phase detector The receiver output is coupled to a phase detector, low pass filter (LPF), a VCO and a comparator on the output of the VCO that converts the analog output of the VCO to a digital output suitable for use as the local clock A level shifter is also provided between the LPF and the VCO The input from LNA 186 is by way of a differential pair The digital output of the VCO, another differential pair, provides the other input to the phase detector

In summary, a novel clock distπbution apparatus and method has been invented and is descπbed herein. That clock distπbution approach eliminates the need for clock distπbution wires, reduces the number of dπver stages and eliminates clock fan-out Since the mam contπbutor of unwanted clock skew is the multiple stages of dnvers m a fan-out tree and the associated clock distπbution wires, clock skew is reduced by the clock distπbution approach descπbed here. Additionally, the present approach eliminates the need for most clock transmission lines with controlled impedances and it eliminates the need for chip pins devoted to clock transmission.

The clock distribution descπbed herein can be used to distπbute a clock on a single chip, on a substrate or board holding several chips or m a multi-board system The scheme descπbed above shows the transmission and reception of a single signal (a clock signal). Simultaneous reception of several other signals at different frequencies can be achieved by msertmg a band-pass filter between the antenna and the

The above descπption is illustrative and not restrictive. Many vaπations of the invention will become apparent to those of skill m the art upon review of this disclosure. For example, the basic embodiment descπbed a transmitter used with one chip and the circuitry thereon. However, one transmitter could be arranged so that it transmits a clock signal to more than one chip The scope of the invention should, therefore, be determined not with reference to the above descπption, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

Claims

WHAT IS CLAIMED IS

1 A clock distπbution circuit for distributing a clock signal to a plurality of clocked circuits, wherein each of the plurality of clocked circuits is clocked by the clock signal or a signal deπved from the clock signal, the clock distribution circuit compπsing a clock generator, a transmitter, coupled to the clock generator, for radiating the clock signal, a plurality of clock receivers coupled such that each of the plurality of clock receivers is coupled to one of the plurality of clocked circuits, wherein each of the plurality of clocked receivers is positioned within a field of radiation of the transmitter and is adapted to receive the radiated clock signal

2 The clock distπbution circuit of claim 1, wherein the plurality of clocked circuits require clock signals within a threshold range of offsets to operate as designed and the plurality of clock receivers are each positioned relative to the transmitter such that the range of times of flight for the radiated clock signal is within the threshold range

3 The clock distribution circuit of claim 1, wherein the plurality of clocked circuits is a plurality of circuits on one integrated circuit substrate

4 The clock distribution circuit of claim 1, wherein the plurality of clocked circuits is distπbuted over a plurality of integrated circuit substrates

5 The clock distribution circuit of claim 1, wherein the plurality of clock circuits are arranged along a plane and the transmitter is positioned at a point off of the plane and separated by the plane by a transmitter distance

6 The clock distribution circuit of claim 5, wherein the transmitter distance is greater than a largest distance between any two of the plurality of clocked circuits

7 The clock distπbution circuit of claim 1, further compπsing a circuit enclosure enclosing the transmitter and the plurality of clock receivers, wherein the circuit enclosure is configured to reduce the amount of radiation radiated by the transmitter directions other than m the direction of a clocked receiver of the plurality of clock receiver

8 The clock distπbution circuit of claim 1 , wherein the plurality of clocked circuits are arranged along a plane and the transmitter is positioned within an enclosure enclosing the transmitter and the plurality of clock circuits at a transmitter distance that is greater than a separation distance, wherein the separation distance is the largest distance between any two of the plurality of clock circuits

9 The clock distribution circuit of claim 8, wherein the transmitter distance is 10 cm and the separation distance is 1 cm and the plurality of circuits are circuits on a common substrate and the clock frequency is from between 1 GHz and 20 GHz

10 The clock distπbution circuit of claim 1 , wherein each clock receiver of the plurality of clock receivers compπses: an antenna positioned withm a radiative field of the transmitter; a low noise amplifier coupled to the antenna to receive the radiated clock signal; and a buffer coupled to the low noise amplifier, wherein an output of the buffer is an output of the clock receiver

11 The clock distπbution circuit of claim 1, wherein each clock receiver of the plurality of clock receivers compπses: an antenna positioned withm a radiative field of the transmitter; a low noise amplifier coupled to the antenna to receive the radiated clock signal; and a phase locked loop coupled to the low noise amplifier, wherein an output of the phase locked loop is an output of the clock receiver

12. The clock distπbution circuit of claim 1 1, wherein the antenna is a surface linear antenna.

13 The clock distribution circuit of claim 1 1 , wherein the antenna is a surface loop antenna.

14 The clock distπbution circuit of claim 1 1 , wherein the antenna is a bonding wire antenna

15 The clock distπbution circuit of claim 1 1 , wherein the antenna is a standing wire antenna

16 The clock distπbution circuit of claim 1 1 , wherein the antenna is either a straight wire or a bent wire

17 The clock distπbution circuit of claim 1 , wherein each clock receiver of the plurality of clock receivers compπses an antenna positioned with a radiative field of the transmitter, a low noise amplifier coupled to the antenna to receive the radiated clock signal, a phase detector, coupled to an output of the clock receiver and an output of the low noise amplifier, wherein the phase detector outputs a signal representing a phase compaπson between the output of the clock receiver and the output of the low noise amplifier, a low pass filter, coupled to receive the signal from the phase detector, and a voltage controlled oscillator, coupled to the low pass filter

18 The clock distπbution circuit of claim 1, further compπsing a plura tv of clock generators wherein each of the plurality of clock generators operates at a unique frequency

19 A clock distπbution circuit for distributing a clock signal to a plurality of circuits, the clock distribution circuit compπsing a clock generator; a transmitter, coupled to the clock generator, for radiating the clock signal, a plurality of clock receivers coupled such that each of the plurality of clock receivers is coupled to one of the plurality of circuits, wherein each of the plurality of clocked receivers is positioned withm a field of radiation of the transmitter and is adapted to receive the radiated clock signal

20. A transmitter for radiating a clock signal to a plurality of clocked circuits, the transmitter including an antenna for radiating a clock signal through a nonmetal medium separating the antenna and a plurality of clock receivers.