WO2001001422A1

WO2001001422A1 - Built-in self test schemes and testing algorithms for random access memories

Info

Publication number: WO2001001422A1
Application number: PCT/GR2000/000022
Authority: WO
Inventors: George Tsiatouhas; Themistoklis Haniotakis
Original assignee: Isd Lisis Olokliromenon Sistimaton S.A.
Priority date: 1999-06-23
Filing date: 2000-06-23
Publication date: 2001-01-04
Also published as: EP1112577A1; JP2003503813A; GR990100210A

Abstract

A Built-in Self Test (BIST) scheme for testing Random Access Memories (RAMs) is disclosed. This scheme is capable of testing either stand-alone or embedded RAMs. Furthermore testing algorithms to exploit this scheme in order to detect all Neighborhood Pattern Sensitive Faults (NPSFs) as well as all cell stuck-at and transition faults in the memory array, and also all single stuck-at faults in the address decoding or the sensing/writing circuitry, are given. The BIST circuitry includes a BIST Controller, a Test Pattern Generation (TPG) unit, a register (RWR) to read and write test data from/to the memory array and a BIST I/O circuitry. The BIST Controller controls the RAM during the test mode of operation while TPG generates the proper test patterns to test the RAM. Test patterns are used to fulfill the RWR register. Since, in the proposed scheme the cells of RWR are connected directly to the sense amplifiers and write buffers of the sensing/writing circuitry, test data can be written to the cells of a word line in parallel while multiple word lines can be written with the same test data in successive write sessions. In addition various methods are given to evaluate the data retrieved in RWR from the memory array, in order to detect and locate possible faults. Finally, the BIST I/O is capable of storing test information concerning the location of a malfunction in the RAM and outputting this information to the external environment via an integrated circuit I/O port or in collaboration with a TAP controller.

Description

Built-in Self Test Schemes and Testing Algorithms for Random

Access Memories

FIELD OF THE INVENTION This invention relates to the field of solid-state devices for data storage. In particular relates to the testing of semiconductor memory devices and especially to testing RAMs (Random Access Memories).

BACKGROUND OF THE INVENTION I. Introduction

With a continuous increase in memory capacitance RAMs have found widely use in modern integrated circuits (ICs). Applications such as portable equipment, computers, printers etc lead to a growing demand for RAMs, either as a stand alone component or embedded within IC logic. The wide use of RAMs makes them a common test target. A plurality of fault models along with testing algorithms is already available. The major drawback of memory testing is the time needed to complete an appropriate test. The actual test time may be up to 300 seconds, thus contributing a considerable portion of the overall cost. Test application time reduction is of great importance. Such reduction can be accomplished with the use of extra test hardware. The cost of that extra hardware must be compared against the benefits of test time reduction. With the increase of memory sizes the relative cost of that extra hardware is reduced while the test becomes more complex. Thus such a solution is increasingly attractive. In case of embedded memories the reduced accessibility has made in practice the use of extra test hardware a necessity and not only an attractive approach. In modern test environments, test algorithms with time complexity equal to O( n^{3 2}), O(n²) or greater are unacceptable (n refers to the number of the memory elements). March algorithms have found extensively use since they offer acceptable fault coverage with a low complexity of O(n). On the other side, March algorithms do not cover the faults of the pattern sensitive fault model, which offers a more realistic approach for modeling the actual physical failures. The main obstacle for the use of pattern sensitive fault model is the great number of possible faults it covers. In practice the neighborhood pattern sensitive fault model is used since it also offers high fault coverage with a low complexity of O(n). Control of the extra test logic can be achieved with the use of extra pins. Since this practice is most probably unacceptable, other approaches have to be utilized. A simple solution is multiplexing these pins with pins not in use during the test phase. Another attractive approach is the use of test support facilities already employed in ICs such as the IEEE 1149.1 standard.

II. The neighborhood pattern sensitive fault model

An important category of faults in DRAMs is pattern sensitive faults. According to this fault model, the content of a cell or the ability to apply a desired value at that cell is affected by the values or transitions on the values of other cells in the memory. In practice the cells (called deleted neighborhood) affecting the operation of a cell (called base cell) are those with proximity to that particular cell. The combination of the base cell and the deleted neighborhood is called neighborhood. The corresponding faults are Neighborhood Pattern Sensitive Faults (NPSF).

Various types cf neighborhoods have been proposed. A common one is Type-1 neighborhood that consists of the base cell and its four adjacent cells, see Fig 1.

Another neighborhood is Type-2 neighborhood, which consists of cells within mi columns to the west, rr> rows to the north, rch columns to the east and n rows to the south of a base cell. Commonly mι=m₂=m₃=m₄=l and the neighborhood contains 9 cells, see Fig 2. Other proposed neighborhoods are the row or the column of the base cell.

Three types of NPSFs can be distinguished:

Active NPSF (ANPSF) or Dynamic NPSF, where the base cell changes its contents due to a change in the deleted neighborhood pattern.

Passive NPSF (PNPSF), where the contents of a cell cannot be changed due to a certain neighborhood pattern.

Static NPSF (SNPSF), where the contents of a base cell are forced to a certain state due to certain deleted neighborhood pattern. In the following the number of test patterns required to test NPSFs of a neighborhood with k elements will be calculated. Initially we examine the case of ANPSFs. The base cell may have two of the following values 0 or 1. Any of the remaining k-1 cells may have a 0->l or l->0 transition. Thus up to now we have 2(k- 1)2 cases and for each of these cases the remaining (k-2) cells may have 2^k"2 combinations thus in total 2(k-l)22^k"2=(k-l)2^k different test pairs exist. For PNPSF the base case may have either a 0->l or a l->0 transition. For each of these two cases the remaining (k-1) cells may take 2 ^~1 combinations. Thus we have 2^k different test pairs. The sum of test pairs for ANPSFs and PNPSFs cases is (k-l)2^k + 2^k = k2 . Furthermore, there are 2^k different test patterns for the SPNSFs case. Lets now see a few methodologies to reduce test application time. Assume that we need to apply the following test pairs (00000,00001) and (10000,00000). A possible sequence will be the (00000,00001,10000,00000). Another possible sequence is (10000,00000,00001). Obviously the second sequence demands a reduced number of test patterns and thus leads to a reduction in the test application time. This is due to the fact that the last pattern of the first pair is the same with the first pattern of the second pair. Appropriate test pattern sequences for memory testing have been proposed in the open literature. A reduction of test time can also be accomplished if we apply test pairs that test more than one fault simultaneously. Note here that a pair that test a PNPSF in a neighborhood A also tests an ANPSF in a neighborhood B if the base cell of A belongs to the deleted neighborhood of B. Thus we can speed up test if we can exploit the above mentioning observation. A method used to accomplish that is the tiling method. According to this method the memory is fully covered by a group of neighborhoods which do not overlap. In FIG. 1 the Type-1 tiling is shown while in FIG. 2 the Type-2 tiling for

is given. As group j of neighborhoods is defined this group that includes all neighborhoods with base cell the cell j. In FIG. 1 and FIG. 2 the group 2 and group 4 are presented, respectively.

Considering Type-1 tiling method, it has been shown that testing all ANPSFs, PNPSFs and SNPSFs for all neighborhoods with base cell either the cell 0 or 1 or 2 or 3 or 4, then all ANPSFs, PNPSFs and SNPSFs (APSNPSFs) of the memory are tested. For example if we test all APSNPSFs for all neighborhoods with base cell 0, then all APSNPSFs for the rest of neighborhoods are also tested. Furthermore testing NPSFs, all cell stuck-at and transition faults are also tested, while inserting proper delays among the read operations retention faults can be covered.

In order to apply a certain test sequence to every neighborhood of group j, an appropriate test sequence must be applied to the whole memory. This sequence applies the same test pattern to every neighborhood. For every pattern of the sequence all the corresponding cells of a group have the same value.

In this invention we propose the use of a read/write register RWR such that every pair of a sense amplifier and a write buffer is connected to a single cell of RWR. If a proper word line is selected the contents of RWR can be written to cells of this word line (or the contents of cells of this word line can be written to the register RWR). Thus whenever the same pattern is to be written to a sequence of word lines the process is considerably speed up. The same applies if a new pattern to be written to another sequence cf word lines is a shifted version of the old pattern. Optional hardware is proposed to detect possible errors in the data retrieved into RWR due to faults in the memory. Furthermore testing algorithms are proposed to exploit the presented BIST scheme in order to detect and locate all APSNPSF, cell stuck-at and transition faults in the memory array and single stuck-at faults in the address decoding circuitry (address faults- AF) or the sensing/writing circuitry.

III. Prior art

The increased density of RAMs has raised the reduction of test time to a dominant design consideration. The ratio of test cost to chip cost is expected to be more than 85% for the 1Gbit DRAMs generation. Furthermore, the great demand for extensive testing of enhanced fault models, as well as the existence of non controllable/observable address and data lines in embedded memories, have set additional limitations to the conventional testing techniques. These issues are making BIST to be more and more attractive from the design and manufacturing perspective.

You and Hayes in the IEEE J. of Solid-State 1985, proposed a BIST scheme that reconfigures the memory array to a circular shift register in order to test it. This reconfiguration is achieved by incorporating pass transistors 30 on the bit lines as shown in FIG. 3. Moreover, a specific design for the shift operation is given using modified sense amplifiers 31. This way a read operation is followed by a write operation in order to transfer test data between adjacent cells in the memory array. Nadeau-Dostie et. al. in the US Patent #4969148 11/1990, presented a BIST architecture for embedded memories which are word-wide. This scheme, as it is given in FIG. 4, uses a serial data input 40 to apply test data to the memory array and a serial data output 41 to observe the test response. A shift register is used for the serial-to- parallel conversion for write operations and the parallel-to-serial conversion for read operations. As shift register the standard data output latches 42 are used along with a set of extra multiplexers 43.

Mazumder and Patel in the EEE Trans, on Computers 1989, proposed an architecture for parallel testing of RAMs. This architecture is illustrated in the block diagram of FIG 5. According to this design, the column decoder 50 is modified to select multiple bit lines 51 during testing. Thus multiple write and read operations can be performed. Furthermore, a parallel comparator 52 is given which determines whether the content of all the multiple accessed cells are either all 0 or 1.

DETAILED DESCRIPTION

I. The built-in self test (BIST) scheme

The standard RAMs configuration along with the proposed BIST circuitry is presented in the block diagram of FIG. 6. Notice that in the figures we refer from now and on, modules that are given in addition to the standard design are shaded while modified modules of the standard design are spotted. The RAM consists of the cells memory array 60, the row address buffers 61 and the row decoder 62, the column address buffers 63 and the column decoder 64 as well as the sense amplifiers (SA) and write buffers (WB) 65 (sensing/writing circuitry). The BIST circuitry consists of the BIST Controller 66, the Test Pattern Generation (TPG) unit 67, a register RWR 68 (read/write register), a multiplexer (MUX) 69. a comparator (COMP) 70 and optionally a Built-in Current Sensor (BICS) 71.

In FIG. 7 the signals associated with the BIST Controller 72 are given. It receives from the external environment the Test_Mode enable signal 73 to enter the test mode of operation and also a Test_CLK clock signal 74 to support this operation. Optionally there exist a Test_RST signal 75 that clears (reset) all BIST circuitry registers during the initialization phase. The controller 72 provides to the external environment the End_Test signal 76 to indicate the end of test operation and the Test_RSL signal 77 to notify the result of the test (pass/fail). Furthermore the controller 72 provides the address signals T_Address 78 to the memory array during the test mode of operarion and redirects the MUX 69 of FIG. 6 with the Test_Mode signal. Also it provides the RWR_Load signal 79 in order the test data patterns generated by the TPG unit 67 in FIG. 6 to be loaded in the RWR register 68. Optionally, the BICS_Enb signal 80 can be available to activate the BICS sensor 71. Finally, the controller receives the error indication signals Err_Ind-l 81 from the comparator (COMP) 70 and optionally the Err_Ind-2 82 from the BICS sensor 71.

The RWR register 68 of FIG. 6, is a parallel in, parallel out register with tri- state outputs. Every cell of RWR feeds a write buffer (WB) of the sensing/writing circuitry 65 and is fed from the corresponding sensor amplifier (SA).

A Test_Mode signal 73 initializes the BIST circuitry at the beginning of a memory test. Optionally a Test_RST signal 74 can be used to clear the BIST registers. Next the TPG unit start to generate test data for the RAM. The proposed BIST scheme tests a RAM in successive test sessions. During each test session there is a write phase where test data are written to the memory cells and a read phase where the stored data are retrieved from the memory cells and compared against the expected (original) data.

In a write phase the test data generated by the TPG unit 67 in FIG. 6, are loaded serially or in parallel to the register RWR 68. In the first case the RWR is constructed to be also a serial input serial output shift register. The test data of RWR forms a test pattern. Then a memory write operation is performed and the test data of RWR are written to specified cells of a word line (row) in parallel. Obviously, rows that should be fed with the same test data patterns forms a group and can be written in sequence. Then a new pattern is loaded into RWR and written to the next group of rows and so on until the proper test data are written to a predetermined number of rows (that may be all)

In a read phase memory read operations are performed to the rows of the memory array. In ever, read operation the data at the output of each sense amplifier (SA) of the sensing/wiring circuitry 65 are captured to the corresponding cell of RWR 68. The retrieved data are used to determine if a fault exists in the memory array 60, the address decoding crcuitry 61, 62, 63, 64, as well as the sensing/writing circuitry 65. The detection of a fault from the retrieved data is accomplished exploiting the existence of the comparator COMP 70, in FIG. 6, which compares the retrieved data with the original test data provided by the TPG unit 67. Any error in these two patterns activates the error indication signal Err_Ind-l 80, which notifies the detection of a fault to the BIST Controller 66. Optionally, the BICS sensor 71 can be used as an error indicator. In that case one of the power supply lines (V_DD or V_Ss) of groups of sense amplifiers expected to provide the same value during a read operation or groups of cells in register RWR expected to store the same value after a read operation, are connected to the BICS, while their outputs are shorted. In either of these two instances an erroneous, due to a fault, read value (which differs compared to the expected one) will cause excess quiescent power supply current to be drawn. This will activate the BICS sensor and the Err_Ind-2 signal will indicate to the BIST Controller the detection of the fault. Shorts between the proper module outputs during testing can be achieved with modifications to the column decoding scheme. In case where a fault is detected a fault indication signal is made available to the outside world via the Test_RSL line.

II. A test algorithm to exploit the proposed BIST scheme

In this section we present new testing algorithms which exploit the proposed in the previous section BIST architecture in order to test a RAM, mainly considering the 5-NPSF fault model and the Type-1 tiling method. These algorithms not only detect but also locate all APSNPSF faults, cell stuck-at and transition faults in the memory array, as well as single stuck-at faults in the address decoding circuitry (row/column address buffers and decoders) and the sensing/writing circuitry. To achieve this the BIST circuitry is organized as it is given in FIG. 8. The RWR register 100 is constructed as a seriaL parallel in serial/parallel out shift register, consisting of b cells, where b is the number of bit lines (BL). Each cell of the register drives a write buffer (WB) 101 and is fed by a sense amplifier (SA) 102 of the sensing/writing circuitry 103. The TPG unit 104 is a 5-bit pattern generator. Every pattern of the TPG is loaded in parallel to a 5-bit serial/parallel in serial out feedback shift register SR 105. The data of SR can be circulated from its serial output to its serial input.

In FIG. 9 a more detailed description of the BIST Controller 1 14 is given. The signals discussed in FIG. 7 also exist with the same functionality while few other signals have been considered serving various additional operations. Initially, the Scan_Mode signal 115 is used to enter the scan mode of operation in order proper test information to be available to the outside world via a scan out type process. The Scan_CLK 116 signal provides the clock signal to support this operation. Furthermore, signal RΛV 118 controls the scan out flow of test information as we will discuss later while the C_Test signals 117 are optionally used to control the Column Decoder during testing. Finally, the BIST Controller provides Controls signals 119, to control the memory operation in the test mode.

The proposed test algorithm tests a RAM in successive test sessions. During each test session there is a write phase where all memory cells are written with specific test data and a read phase that follows where each memory row is read in order the stored data to be retrieved and compared against the original one. The flow diagram of the algorithm is given in FIG. 10.

According to the 5-NPSF fault model, the Type-1 tiling method and FIG. 1 it is obvious that the same test vector is applied during a session to a number of rows, for example first, fifth. ... , etc row. Furthermore each row is written with a repeat of a simple pattern. The first row for example is constructed from a repetition of the following pattern 34012. The second row is constructed from a repetition of the pattern 01234 and so on. Note here that every row is a horizontally shifted version of the first row.

In a write phase proper test data are written to all cells of a word line (row) in parallel. This is achieved using the shift register RWR 100 to store the corresponding test pattern. Every cell cf RWR feeds the write buffer (WB) 101 of a bit line and is fed from the corresponding sensor amplifier (SA) 102. According to FIG 10(c), the write phase of a test session starts with a shift in operation of the test pattern into RWR. Then a memory write operation is performed, so that the test pattern is written from RWR to the cells of a specified row. Obviously, rows that should be fed with the same test data patterns form a group and can be written in sequence. Then the pattern in RWR is shifted one position and the new pattern is written to the next group of rows and so on until the proper test data are written in all memory cells. Thus during the write phase only the row address is needed to be specified to the row decoder and so the column decoder is inactive. In a read phase a memory read operation is performed to every row of the memory array. The data at the output of each sense amplifier (SA) is captured to the corresponding cell of RWR. Once again the column decoder is inactive. The retrieved data are used to determine if a fault exists in the memory array or the address decoding circuitry. In case where a fault is detected a fault indication signal is made available to the outside word via the Test_RSL line of the BIST Controller. Optionally, in that case a fault location mechanism can also be activated. Thus, after the detection of the malfunction in the RAM, the corresponding address, the used test data pattern and optionally other useful control signal information are stored in a scan register (RSCAN). This information can be used by a Built-in Self-Repair (BISR) circuitry in order to replace the malfunctioning part. Furthermore, for repair or failure analysis purposes, the contents of RSCAN can be scanned out to the external environment through a Scan_Out line under the control of the Scan_CLK signal.

In more details, as we have mention the TPG unit generates test data for the RAM. These test data consist of 5-bit patterns. There is a total of 160 test patterns for the 5-NPSF model under consideration that forms an Eulerian sequence and thus there is a total of 160 test sessions.

The generation of a test pattern follows a write phase. The test pattern is loaded in parallel to the register SR 105 and forms the active test pattern. Then the active test pattern is shifted out from SR and shifted in RWR 100. This process requires b shift operations to fulfill RWR with b/5 copies of the 5-bit test pattern, where b is the number of bit lines. The pattern in RWR is called bit line pattern. Now there are two methods to fulfill the memory array with the proper test data using the bit line pattern in RWR. According to the first one, the BIST Controller generates successively the proper row addresses where the pattern of RWR should be written and activates the appropriate control signals to perform write operations. All these addresses have a distance between them equal to 5 and the corresponding word lines forms a group with cardinality w/5, where w is the number of word lines (WL). At that point the contents of RWR are shifted one position and the new bit line pattern is written to another group of w/5 rows. There is a total of five groups of word lines, since the active test pattern has 5-bits, and thus the above operation is executed three more times (a total of five shift and group write operations) until the memory array is fulfilled with test data. Considering the second method, the initial bit line pattern of RWR is written to the cells of the first word line. Then RWR is shifted one position and the new bit line pattern is written to the second word line and so on until the memory array is fulfilled. This method needs a total of w shift and write operations. Using anyone of the above methods the memory array is tiled with the same pattern of non-overlapping neighborhoods.

Next follows the read phase. This time the BIST Controller generates successively the proper row addresses and control signals to perform a total of w read operations so that the data stored in the cells of each row to be captured in RWR. After a read operation the data in RWR are used to determine if there exist a fault in the memory array or the row decoding circuitry (Row Address Buffers 106 and Row Decoders 107). An error in the expected data captured in RWR indicates the existence of a fault.

Two possible ways to detect an error in the data of RWR are proposed in this invention. The first one is to shift out the data from RWR and compare each bit with the corresponding bit cf the original active test pattern held in SR 105 using a XOR gate 108 (see FIG. 8 This process can be achieved by shifting SR and RWR in parallel and requires a total of b shift operations and comparisons. A possible error activates the Err_Ind-l signal. If the comparison always indicates an error in the same bit position of SR then the fault is located in the row decoder circuitry. The flow diagram of this operation is presented in FIG. 10(d). A second method is to use a Built-in Current Sensor (BICS) 109 at the

V_DD(V_SS) power line of RWR. This sensor can detect any abnormal current in the steady state of the circuit. During a read operation in test mode, the data of a row are captured in RWR. Considering the bit line pattern that is written to the cells of each row in the write phase, it is obvious that all cells j of RWR with (j mod 5)=m are expected to have the same values, where me[l, 5]. Thus in test mode after a read operation the Column Decoder 1 10 enables each one of these groups of cells to drive the DataJL/O line. This operation demands a modification of the Column Decoder and the proper activation of the control signals C_Test from the BIST Controller. Then the sensor is enabled with the BICS_Enb signal. In case where one or more cells have a different value from the rest in the group, then a conducting path between the two power supplies (from Y_DD to V_Ss) is established and an unexpectedly large amount of current is drawn. The BICS can detect this current and the Err_Ind-2 signal is activated which indicates the presence of an error in the retrieved data and consequently the presence of a fault in the memory array. Now, in case where no error is detected, a shift out operation is performed in order to compare a proper 5 -bit sequence in RWR with the active test pattern in SR. This step is needed to ensure that there is not any stuck-at fault in the row decoding circuitry. If these two patterns differ then a fault in the row decoding circuitry has been detected. The flow diagram of the second error detection method is given in FIG. 10(e). The above errcr detection methods provide a complete single stuck-at fault coverage for the row decoding circuitry, since in the presence of such faults an incorrect word line with a different pattern than the right one is always activated. This is true considering the way the test data are written to the word lines. Whenever an error is detected, due to a fault in the memory array, information to locate the corresponding malfunctioning cell can be provided to the external environment using the following technique. The data of RWR are shifted out and compared, with the use of a XOR gate 108, with the corresponding bits of SR. Notice that the shift operation is already part of these error detection methods. A log₂b bit counter (shift-out counter - SOC) inside BIST Controller is used to count the number of shift operations until an error is detected. In case where an error is detected, the XOR gate activates the error indication signal Err_Ind-l and the shift operation is terminated. Obviously, the current value of SOC determines the column address of the malfunctioning cell in the memory array. The row address of this cell is the current address held in the Row Address Buffer 106. Now, in case where the fault is in the row decoding circuitry the address held in the Row Address Buffer is adequate in order to locate it.

The next step is to detect and locate possible single stuck-at faults in the column decoding circuitry (Column Address Buffer 111 and Column Decoder 110).

The process is as follows. The five test patterns of Table 1 are loaded in SR in sequence. Note that these patterns have only one ace bit and the position of this bit is marked as q. For each cne of them a b shift operation is taking place in order to fulfill

RWR as in the previous cases. Then a write operation to a freely selected row is performed. The write operation follows a read operation to this specific row in order to retrieve the stored data and capture them in the RWR. Then the Column Decoder is fed with the proper addresses so that all cells RWRj of the shift register RWR, with (j mod 5)=q, are read the one after the other at the Data_I O line. A zero value at the

Data_I/O line indicates the presence of a stuck-at fault in the column decoding circuitry. Since the cok-mn address is known (this held in the Column Address Buffer

111) the fault has been located. The flow diagram of the column decoding circuitry testing algorithm is given in FIG. 10(f).

A scan register RSCAN is formed in order to store the proper information that can be used to locate a fault. This register 120 is constructed using the SR register 121, the SOC counter 122 and the Row Address Buffer 123 or the Column Address Buffer 124, in a scan chain, as it is presented in FIG. 11. In case of a detected fault in the memory array or the row decoding circuitry, the RSCAN is constructed to incorporate the Row Address Buffer 123, instead of the Column Address Buffer 124, with the use of signal R C that drives the selected input of the multiplexer MUX 125. Else, in case of a fault in the column decoding circuitry, the RSCAN is constructed to incorporate in the chain the Column Address Buffer 124. Furthermore, the RSCAN also incorporates a 2-bit register (GLR) 126, which is written by the BIST Controller and indicates in general the location of a possible detected fault. A feasible coding scheme for the contents of GLR could be as follows: "00" for the fault free case, "01" for a fault in the row decoding circuitry, "10" for a fault in the column decoding circuitry, and "11" in case of a fault in the memory array.

III. Connecting the BIST circuitry with the external environment Obviously there is a great demand to transfer test results and useful test information from the internal BIST circuitry to the external environment during testing, due to memory repair or failure analysis purposes. The communication of these two worlds can be achieved as follows.

According to FIG. 9, the BIST circuitry receives from the external environment a Test_Mode enable signal to initialize the BIST Controller to enter the test mode of operation and also a Test_CLK signal to support this operation.

Furthermore the BIST Controller also receives the ScanJVlode enable signal 116 to initialize the scan-out process in order to transmit test data through a Scan_Out line.

In addition a Scan_CLK signal 115 provides the clock signals for the scan operations. Optionally there exist a Test_RST signal that clears all BIST circuitry registers during initialization phases. Finally the End_Test and Test_RSL signals are provided from the

BIST Controller to the outside world to indicate the end of test operation as well as its result. Another approach to the communication of the BIST circuitry with the external environment is through the use of IEEE 1149.1 standard TAP controller. The BIST circuit receives the Test_Mode, Test_CLK, Scan_Mode, Scan_CLK and Test_RST signals from the TAP controller and outputs End_ Test, Test_RSL and Scan_Out signals to the TAP interface. In case of system-on-a-chip solutions, where the RAM is embedded with logic in a single chip the TAP controller can serve both the memory BIST and the logic BIST circuitry.

Table 1

Test Patterns Used to Detect Column Decoder's Stuck-at Faults

00001

00010

00100

01000

10000

Claims

CLAIMSWe claim

1. A built-in parallel in - parallel out register, characterized in that: - it is connected directly to the sensing/writing circuitry of the memory bit-lines

- it is used to read/write in parallel test data from/to the memory array, for use in the testing of RAMs.

2. A built-in parallel in - parallel out register according to the previous claim wherein, in case of a test algorithm demanding same test data to be written to various memory cells said data are loaded only once to the register.

3. A built-in parallel in - parallel out register according to the previous claims characterized in that, the register can optionally be implemented so that it additionally is a serial in- serial out shift register, wherein the new test data can be created either by shifting the current test data of the register or in any other known way, in which case, appropriate test data are shifted in or loaded to a limited number of the register's memory elements.

4. A built-in parallel in - parallel out register according to the previous claims wherein the memory response to a test is stored into same wherein the verification of this response can be achieved by shifting out (of the register) the response data and by comparing them with the expected data.

5. A built-in parallel in - parallel out register according to the previous claims wherein the verification of the memory response to a test is accelerated by monitoring the supply current, b pre-forming electrical connections (shorts) between selected response lines, which hi the fault free case have the same value, while in the presence of a fault may present erroneous response values, thus resulting to the sensing of excess power dissipation.

6. A test algorithm for use in combination with the register according to the previous claims, which is intended to be used for the exploitation of the proposed BIST scheme in order to detect and locate all possible neighborhood pattern sensitive, cell stuck-at and transition faults in the memory array as well as all single stuck-at faults in the address decoding and sensing/writing circuitry.