WO2001001450A3 - Dram cell fabrication process and method for operating same - Google Patents

Dram cell fabrication process and method for operating same Download PDF

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Publication number
WO2001001450A3
WO2001001450A3 PCT/US2000/015119 US0015119W WO0101450A3 WO 2001001450 A3 WO2001001450 A3 WO 2001001450A3 US 0015119 W US0015119 W US 0015119W WO 0101450 A3 WO0101450 A3 WO 0101450A3
Authority
WO
WIPO (PCT)
Prior art keywords
thermal cycles
boosted voltage
dram cell
less
shallow
Prior art date
Application number
PCT/US2000/015119
Other languages
French (fr)
Other versions
WO2001001450A2 (en
Inventor
Wingyu Leung
Fu-Chieh Hsu
Original Assignee
Monolithic System Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/332,757 external-priority patent/US6147914A/en
Application filed by Monolithic System Tech Inc filed Critical Monolithic System Tech Inc
Publication of WO2001001450A2 publication Critical patent/WO2001001450A2/en
Publication of WO2001001450A3 publication Critical patent/WO2001001450A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Abstract

A memory system that includes a dynamic random access memory (DRAM) cell that includes an access transistor and a storage capacitor. The storage capacitor of the DRAM cell is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. After the first set of thermal cycles are complete, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide. The DRAM cell is operated in response to a word line driver that is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell. The positive boosted voltage is greater than Vdd but less than Vdd plus the absolute value of a transistor threshold voltage Vt. Similarly, the negative boosted voltage generator is less than VSS by an amount less than Vt.
PCT/US2000/015119 1999-06-14 2000-06-02 Dram cell fabrication process and method for operating same WO2001001450A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/332,757 US6147914A (en) 1998-08-14 1999-06-14 On-chip word line voltage generation for DRAM embedded in logic process
US09/332,757 1999-06-14
US09/427,383 1999-10-25
US09/427,383 US6509595B1 (en) 1999-06-14 1999-10-25 DRAM cell fabricated using a modified logic process and method for operating same

Publications (2)

Publication Number Publication Date
WO2001001450A2 WO2001001450A2 (en) 2001-01-04
WO2001001450A3 true WO2001001450A3 (en) 2001-07-26

Family

ID=26988369

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/015119 WO2001001450A2 (en) 1999-06-14 2000-06-02 Dram cell fabrication process and method for operating same

Country Status (3)

Country Link
US (1) US6509595B1 (en)
TW (1) TW434839B (en)
WO (1) WO2001001450A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573548B2 (en) * 1998-08-14 2003-06-03 Monolithic System Technology, Inc. DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
US6468855B2 (en) 1998-08-14 2002-10-22 Monolithic System Technology, Inc. Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
US7253047B2 (en) * 1999-09-01 2007-08-07 Micron Technology, Inc. Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry
US6236617B1 (en) * 1999-12-10 2001-05-22 International Business Machines Corporation High performance CMOS word-line driver
US6902975B2 (en) * 2003-10-15 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory technology compatible with 1T-RAM process
US7019348B2 (en) * 2004-02-26 2006-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded semiconductor product with dual depth isolation regions
US7195970B2 (en) * 2004-03-26 2007-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insulator-metal capacitors
US7323379B2 (en) 2005-02-03 2008-01-29 Mosys, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
CN101741354A (en) * 2009-11-25 2010-06-16 天津南大强芯半导体芯片设计有限公司 Oscillator circuit with low frequency and low power consumption and working method thereof
US9209167B2 (en) * 2014-03-25 2015-12-08 International Business Machines Corporation Determining threshold voltage variations in field effect transistors

Citations (7)

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Publication number Priority date Publication date Assignee Title
DE4034169A1 (en) * 1989-10-26 1991-05-02 Mitsubishi Electric Corp DRAM memory cell field with numerous cells for unit signals - has specified foreign atom. concentration in section coupled to capacitor
JPH03259566A (en) * 1990-02-02 1991-11-19 Sony Corp Manufacture of memory device
EP0460694A2 (en) * 1990-06-08 1991-12-11 Nec Corporation Semiconductor memory device having a driver unit for boosting a word line twice
EP0493659A2 (en) * 1991-01-02 1992-07-08 International Business Machines Corporation PMOS wordline boost circuit for dram
EP0632462A2 (en) * 1993-06-30 1995-01-04 International Business Machines Corporation DRAM cell
JPH0794596A (en) * 1993-09-20 1995-04-07 Nec Corp Semiconductor integrated circuit device and fabrication thereof
US5789291A (en) * 1995-08-07 1998-08-04 Vanguard International Semiconductor Corporation Dram cell capacitor fabrication method

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US5198995A (en) 1990-10-30 1993-03-30 International Business Machines Corporation Trench-capacitor-one-transistor storage cell and array for dynamic random access memories
KR940002859B1 (en) 1991-03-14 1994-04-04 삼성전자 주식회사 Wordline driver circuit in semiconductor memory device
JP2771729B2 (en) 1992-04-16 1998-07-02 三菱電機株式会社 Charge pump circuit
JP2905666B2 (en) 1992-05-25 1999-06-14 三菱電機株式会社 Internal voltage generation circuit in semiconductor device and nonvolatile semiconductor memory device
US5377139A (en) * 1992-12-11 1994-12-27 Motorola, Inc. Process forming an integrated circuit
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Patent Citations (7)

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Publication number Priority date Publication date Assignee Title
DE4034169A1 (en) * 1989-10-26 1991-05-02 Mitsubishi Electric Corp DRAM memory cell field with numerous cells for unit signals - has specified foreign atom. concentration in section coupled to capacitor
JPH03259566A (en) * 1990-02-02 1991-11-19 Sony Corp Manufacture of memory device
EP0460694A2 (en) * 1990-06-08 1991-12-11 Nec Corporation Semiconductor memory device having a driver unit for boosting a word line twice
EP0493659A2 (en) * 1991-01-02 1992-07-08 International Business Machines Corporation PMOS wordline boost circuit for dram
EP0632462A2 (en) * 1993-06-30 1995-01-04 International Business Machines Corporation DRAM cell
JPH0794596A (en) * 1993-09-20 1995-04-07 Nec Corp Semiconductor integrated circuit device and fabrication thereof
US5789291A (en) * 1995-08-07 1998-08-04 Vanguard International Semiconductor Corporation Dram cell capacitor fabrication method

Non-Patent Citations (2)

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PATENT ABSTRACTS OF JAPAN vol. 1995, no. 07 31 August 1995 (1995-08-31) *

Also Published As

Publication number Publication date
TW434839B (en) 2001-05-16
WO2001001450A2 (en) 2001-01-04
US6509595B1 (en) 2003-01-21

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