WO2001003200A1 - Insulation of gate electrodes and production method - Google Patents
Insulation of gate electrodes and production method Download PDFInfo
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- WO2001003200A1 WO2001003200A1 PCT/DE2000/002101 DE0002101W WO0103200A1 WO 2001003200 A1 WO2001003200 A1 WO 2001003200A1 DE 0002101 W DE0002101 W DE 0002101W WO 0103200 A1 WO0103200 A1 WO 0103200A1
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- WIPO (PCT)
- Prior art keywords
- gate electrode
- spacers
- nitride
- source
- edge
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009413 insulation Methods 0.000 title description 2
- 125000006850 spacer group Chemical group 0.000 claims abstract description 33
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 238000010292 electrical insulation Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 12
- 229910021332 silicide Inorganic materials 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004886 process control Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Definitions
- the present invention relates to electrical insulation of gate electrodes with respect to the source / dram contacts and an associated manufacturing method.
- silicide bridges between the gate electrode and the source / dram contacts should be avoided. It has been shown that pure silicon oxide spacers do not ensure sufficient blocking properties with regard to silicide bridges between the gate and source or drain. The blocking properties of silicon nitride are therefore used. It is possible to produce a pure nitride spacer or a multilayer spacer from oxide and nitride.
- the thick nitride layer required for a pure nitride spacer may have sufficient blocking properties, but depending on the reoxidation layer of the gate electrode leads to mechanical stresses in the silicon underneath, which induces undesired leakage currents.
- the very strong trapping properties of the nitride with regard to hot charge carriers are also disadvantageous.
- a multilayer spacer can be produced, for example, before the source / drain implantation by means of an oxide-nitride or a nitnd-oxide layer sequence, which, however, is associated with complex process control. In ESD structures, there are so-called blocked transistors, that is, non-siliconized transistors.
- Nitride usually serves as a blocking material. However, if the nitride only remains at the base of the spacer after the etching, the blocking property may be insufficient.
- the object of the present invention is to provide an electrical insulation of a gate electrode from source / dram contacts which can be produced in the course of a salicide process and which has a sufficient blocking property with regard to silicide bridges between gate and source or
- the idea of the invention is to use a suitable process control not only to produce a nitride layer at the foot of an oxide spacer, but to encapsulate the oxide spacer completely or partially with nitride, so that an additional blocking effect is also produced on the top of the oxide spacer.
- the spacers produced on the flanks of the gate electrode preferably made of oxide, are limited in height so that they leave an upper part of the flanks of the gate electrode free. These upper portions of the flanks of the gate electrode are covered with nitride as further spacers.
- Figures 1 and 2 show cross sections of the gate electrode with the blocking spacers after various steps of the manufacturing method according to the invention.
- Figures 3 and 4 show the cross sections according to Figures 1 and 2 in an alternative embodiment.
- FIG. 1 shows in cross section on a silicon substrate 1 a gate electrode 2 over a gate oxide 3.
- the gate electrode is covered on the top with a thin oxide layer 4.
- the surface of this structure is then preferably isotropically covered with a nitride layer 7.
- This nitride layer 7 is then etched back in such a way that further spacers 8 made of nitride remain, which cover the upper portions 11 of the flanks of the gate electrode 2 (FIG. 2). There are also further spacers 9 on each foot of the spacers 5, so that the blocking effect is also further improved.
- FIG. 3 shows the cross section corresponding to FIG. 1 with the difference that in the exemplary embodiment shown in FIG. 3 the nitride layer 7 is deposited much thicker. The result of this is that after this nitride layer 7 has been scratched away, somewhat larger further spacers 10 made of nitride remain, which completely encapsulate the spacers 5. As can be seen in FIG. 4, these further spacers 10 cover the entire outside of the
- Spacer 5 including the base of these spacers and the upper portions 11 of the flanks of the gate electrode.
- the structure according to the invention therefore, depending on the process control, enables only a partial encapsulation of the spacers 5 by means of a thinly deposited nitride layer and corresponding recessing, or, after deposition of a thicker nitride layer, complete encapsulation of the spacers 5.
- a pure nitride spacer or the use of multiple depositions which simplifies production considerably. At the same time, the desired sufficient blocking effect is achieved.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Oxide spacers (5) are produced on the edges of a gate electrode (2). The oxide spacers terminate underneath the upper side of the gate electrode such that a portion (11) of the edge is not covered. A nitride layer is deposited and is etched back so that additional spacers (8) comprised of nitride remain which cover these upper portions (11) of the edges of the gate electrode. This results in a blocking effect that is adequate for preventing the formation of silicide bridges between the gate and source or the drain.
Description
Beschreibungdescription
Isolation von Gate-Elektroden und HerstellungsverfahrenIsolation of gate electrodes and manufacturing processes
Die vorliegende Erfindung betrifft eine elektrische Isolation von Gate-Elektroden gegenüber den Source-/Dram-Kontaktιerun- gen und ein zugehöriges Herstellungsver ahren.The present invention relates to electrical insulation of gate electrodes with respect to the source / dram contacts and an associated manufacturing method.
Bei der Herstellung der Kontakte für Source/Drain-Gebiete von Transistoren im Rahmen eines Salizid-Prozesses sollen Sili- zidbrucken zwischen der Gate-Elektrode und den Source-/Dram- Kontakten vermieden werden. Es hat sich gezeigt, daß reine Siliziumoxid-Spacer keine ausreichenden Blockiereigenschaften hinsichtlich Silizidbrucken zwischen Gate und Source bzw. Drain gewährleisten. Daher werden die Blockiereigenschaften von Siliziumnitrid genutzt. Es besteht die Möglichkeit, einen reinen Nitridspacer oder einen Mehrschichtspacer aus Oxid und Nitrid herzustellen.When producing the contacts for source / drain regions of transistors in the context of a salicide process, silicide bridges between the gate electrode and the source / dram contacts should be avoided. It has been shown that pure silicon oxide spacers do not ensure sufficient blocking properties with regard to silicide bridges between the gate and source or drain. The blocking properties of silicon nitride are therefore used. It is possible to produce a pure nitride spacer or a multilayer spacer from oxide and nitride.
Die für einen reinen Nitridspacer erforderliche dicke Nitridschicht kann zwar ausreichenden Blockiereigenschaften besitzen, fuhrt jedoch abhangig von der Reoxidationsschicht der Gate-Elektrode zu mechanischen Verspannungen des darunter liegenden Siliziums, was ungewunschte Leckstrome induziert. Auch sind die sehr starken Trapping-Eigenschaften des Nitrids hinsichtlich heißer Ladungsträger nachteilig. Ein Mehrschichtspacer laßt sich zum Beispiel vor der Source-/Draιn- Implantation durch eine Oxid-Nitrid- oder eine Nitnd-Oxid- Schichtfolge erzeugen, was allerdings mit einer komplexen Prozeßfuhrung verbunden ist. Bei ESD-Strukturen gibt es sogenannte geblockte Transistoren, das heißt nicht silizierte Transistoren. Zu deren Herstellung wird eine zusatzliche Abscheidung von Oxid oder Nitrid vor der selbstjustierten Sili- zierung durchgeführt, mit Hilfe einer Fotomaske die zu blok- kenden Transistoren abgedeckt und die zu silizierenden Transistoren wieder freigeatzt. Mit diesen zusätzlichen Prozeßschritten kann der Fuß des Spacers verbreitert werden und auf
diese Weise die Blockiereigenschaft des Spacers erhöht werden. Üblicherweise dient Nitrid als Blockiermateπal . Wenn das Nitrid nach der Atzung nur am Fuß des Spacers verbleibt, kann aber die Blockiereigenschaft unzureichend sein.The thick nitride layer required for a pure nitride spacer may have sufficient blocking properties, but depending on the reoxidation layer of the gate electrode leads to mechanical stresses in the silicon underneath, which induces undesired leakage currents. The very strong trapping properties of the nitride with regard to hot charge carriers are also disadvantageous. A multilayer spacer can be produced, for example, before the source / drain implantation by means of an oxide-nitride or a nitnd-oxide layer sequence, which, however, is associated with complex process control. In ESD structures, there are so-called blocked transistors, that is, non-siliconized transistors. To produce them, an additional deposition of oxide or nitride is carried out before the self-adjusted siliconization, the transistors to be blocked are covered with a photomask and the transistors to be siliconized are exposed again. With these additional process steps, the foot of the spacer can be widened and opened the blocking property of the spacer can be increased in this way. Nitride usually serves as a blocking material. However, if the nitride only remains at the base of the spacer after the etching, the blocking property may be insufficient.
Aufgabe der vorliegenden Erfindung ist es, eine elektrische Isolation einer Gate-Elektrode von Source-/Dram-Kontaktιe- rungen anzugeben, die im Rahmen eines Salizidprozesses hergestellt werden kann und eine ausreichende Blockiereigenschaft hinsichtlich Silizidbrucken zwischen Gate und Source bzw.The object of the present invention is to provide an electrical insulation of a gate electrode from source / dram contacts which can be produced in the course of a salicide process and which has a sufficient blocking property with regard to silicide bridges between gate and source or
Drain garantiert. Außerdem soll ein zugehöriges Herstellungsverfahren angegeben werden.Drain guaranteed. In addition, an associated manufacturing process should be specified.
Diese Aufgabe wird mit der Isolation mit den Merkmalen des Anspruches 1 bzw. mit dem Verfahren mit den Merkmalen des Anspruches 2 gelost.This problem is solved with the isolation with the features of claim 1 or with the method with the features of claim 2.
Die Idee der Erfindung ist es, durch eine geeignete Prozeß- fuhrung eine Nitridschicht nicht nur am Fuß eines Oxidspacers herzustellen, sondern den Oxidspacer vollständig bzw. partiell mit Nitrid einzukapseln, so daß auch an der Oberseite des Oxidspacers eine zusätzliche Blockierwirkung hervorgerufen wird. Zu diesem Zweck werden die an den Flanken der Gate- Elektrode hergestellten Spacer, vorzugsweise aus Oxid, so m ihrer Hohe begrenzt, daß sie einen oberen Teil der Flanken der Gate-Elektrode frei lassen. Diese oberen Anteile der Flanken der Gate-Elektrode werden mit Nitrid als weiteren Spacern bedeckt.The idea of the invention is to use a suitable process control not only to produce a nitride layer at the foot of an oxide spacer, but to encapsulate the oxide spacer completely or partially with nitride, so that an additional blocking effect is also produced on the top of the oxide spacer. For this purpose, the spacers produced on the flanks of the gate electrode, preferably made of oxide, are limited in height so that they leave an upper part of the flanks of the gate electrode free. These upper portions of the flanks of the gate electrode are covered with nitride as further spacers.
Es folgt eine genauere Beschreibung der erfmdungsgemaßen Isolation und deren Herstellung anhand der m den Figuren dargestellten Beispiele:The following is a more detailed description of the insulation according to the invention and its production using the examples shown in the figures:
Figuren 1 und 2 zeigen Querschnitte der Gate-Elektrode mit den Blockierspacern nach verschiedenen Schritten des erfmdungsgemaßen Herstellungsverfahrens .
Figuren 3 und 4 zeigen die Querschnitte gemäß Figuren 1 und 2 in einer alternativen Ausfuhrungsform.Figures 1 and 2 show cross sections of the gate electrode with the blocking spacers after various steps of the manufacturing method according to the invention. Figures 3 and 4 show the cross sections according to Figures 1 and 2 in an alternative embodiment.
Figur 1 zeigt im Querschnitt auf einem Siliziumsubstrat 1 ei- ne Gate-Elektrode 2 über einem Gateoxid 3. Die Gate-Elektrode ist auf der Oberseite mit einer dünnen Oxidschicht 4 bedeckt. An beiden Flanken der Gate-Elektrode befinden sich Spacer 5, die vorzugsweise aus Oxid, zum Beispiel aus TEOS (Tetraethyl- orthosilikat) gebildet sind. Auch diese Spacer 5 sind m die- sem Beispiel mit einer Oxidschicht 6 bedeckt. Wesentlich f r die erfmdungsgemaße Struktur ist, daß die Spacer 5 bereits unterhalb einer eweils oberen Kante 12 der Gate-Elektrode 2 enden, so daß sie einen oberen Anteil 11 der Flanke nicht bedecken. Bei einem bevorzugten Herstellungsverfahren wird so- dann die Oberflache dieser Struktur vorzugsweise isotrop mit einer Nitridschicht 7 bedeckt. Diese Nitridschicht 7 wird dann derart ruckgeatzt, daß weitere Spacer 8 aus Nitrid zurück bleiben, die die oberen Anteile 11 der Flanken der Gate- Elektrode 2 bedecken (Figur 2). Es verbleiben ebenfalls wei- tere Spacer 9 an jedem Fuß der Spacer 5, so daß dadurch die Blocklerwirkung ebenfalls weiter verbessert wird.1 shows in cross section on a silicon substrate 1 a gate electrode 2 over a gate oxide 3. The gate electrode is covered on the top with a thin oxide layer 4. Spacers 5, which are preferably formed from oxide, for example from TEOS (tetraethyl orthosilicate), are located on both flanks of the gate electrode. In this example, these spacers 5 are also covered with an oxide layer 6. It is essential for the structure according to the invention that the spacers 5 already end below an upper edge 12 of the gate electrode 2, so that they do not cover an upper portion 11 of the flank. In a preferred production method, the surface of this structure is then preferably isotropically covered with a nitride layer 7. This nitride layer 7 is then etched back in such a way that further spacers 8 made of nitride remain, which cover the upper portions 11 of the flanks of the gate electrode 2 (FIG. 2). There are also further spacers 9 on each foot of the spacers 5, so that the blocking effect is also further improved.
Figur 3 zeigt den der Figur 1 entsprechenden Querschnitt mit dem Unterschied, daß bei dem m Figur 3 dargestellten Ausfuh- rungsbeispiel die Nitridschicht 7 wesentlich dicker abgeschieden wird. Damit wird erreicht, daß nach dem Ruckatzen dieser Nitridschicht 7 etwas größere weitere Spacer 10 aus Nitrid verbleiben, die die Spacer 5 vollständig einkapseln. Wie m Figur 4 zu erkennen ist, bedecken diese weiteren Spacer 10 also zusammenhangend die gesamte Außenseite derFIG. 3 shows the cross section corresponding to FIG. 1 with the difference that in the exemplary embodiment shown in FIG. 3 the nitride layer 7 is deposited much thicker. The result of this is that after this nitride layer 7 has been scratched away, somewhat larger further spacers 10 made of nitride remain, which completely encapsulate the spacers 5. As can be seen in FIG. 4, these further spacers 10 cover the entire outside of the
Spacer 5 einschließlich des Fußes dieser Spacer und der oberen Anteile 11 der Flanken der Gate-Elektrode. Die erfm- dungsgemaße Struktur ermöglicht daher je nach Prozeßfuhrung mittels einer dünn abgeschiedenen Nitridschicht und entspre- chender Ruckatzung eine nur partielle Emkapselung der Spacer 5 oder nach Abscheiden einer dickeren Nitridschicht eine vollständige Emkapselung der Spacer 5. Dadurch kann auf ei-
nen reinen Nitridspacer oder die Verwendung von Mehrfachab- scheidungen verzichtet werden, was die Herstellung wesentlich vereinfacht. Gleichzeitig wird die gewünschte ausreichende Blockierwirkung erreicht.
Spacer 5 including the base of these spacers and the upper portions 11 of the flanks of the gate electrode. The structure according to the invention therefore, depending on the process control, enables only a partial encapsulation of the spacers 5 by means of a thinly deposited nitride layer and corresponding recessing, or, after deposition of a thicker nitride layer, complete encapsulation of the spacers 5. a pure nitride spacer or the use of multiple depositions, which simplifies production considerably. At the same time, the desired sufficient blocking effect is achieved.
Claims
1. Elektrische Isolation einer Gate-Elektrode von Source- /Drain-Kontaktierungen , bei der source- und drainseitige Flanken einer Gate-Elektrode (2) mit Spacern (5) versehen sind, dadurch gekennzeichnet, daß die Spacer (5) unterhalb einer oberen Kante (12) der Gate- Elektrode enden und ein an diese Kante anschließender Anteil (11) der Flanke von einem weiteren Spacer (8, 10) aus Nitrid bedeckt ist.1. Electrical isolation of a gate electrode from source / drain contacts, in which the source and drain flanks of a gate electrode (2) are provided with spacers (5), characterized in that the spacers (5) below an upper one Edge (12) of the gate electrode ends and a portion (11) of the flank adjoining this edge is covered by a further spacer (8, 10) made of nitride.
2. Verfahren zur Herstellung einer elektrischen Isolation einer Gate-Elektrode von Source-/Drain-Kontaktierungen, bei dem source- und drainseitige Flanken einer Gate-Elektrode (2) mit Spacern (5) versehen werden, dadurch gekennzeichnet, daß die Spacer (5) so geätzt werden, daß sie jeweils unterhalb einer oberen Kante (12) der Gate-Elektrode (2) enden und jeweils auf einen Bereich zwischen der betreffenden Kante2. A method for producing an electrical insulation of a gate electrode from source / drain contacts, in which the source and drain side flanks of a gate electrode (2) are provided with spacers (5), characterized in that the spacers (5 ) are etched so that they each end below an upper edge (12) of the gate electrode (2) and in each case on an area between the relevant edge
(12) und dem Spacer (5) eine Nitridschicht (7) abgeschieden und so geätzt wird, daß ein an die Kante anschließender Anteil (11) der Flanke von Nitrid bedeckt bleibt. (12) and the spacer (5), a nitride layer (7) is deposited and etched in such a way that a portion (11) of the flank adjoining the edge remains covered by nitride.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19930115.8 | 1999-06-30 | ||
| DE19930115 | 1999-06-30 |
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| Publication Number | Publication Date |
|---|---|
| WO2001003200A1 true WO2001003200A1 (en) | 2001-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE2000/002101 WO2001003200A1 (en) | 1999-06-30 | 2000-06-28 | Insulation of gate electrodes and production method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10775863B2 (en) | 2003-08-15 | 2020-09-15 | Apple Inc. | Methods and apparatuses for controlling the temperature of a data processing system |
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|---|---|---|---|---|
| US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
| US5739573A (en) * | 1994-07-22 | 1998-04-14 | Nec Corporation | Semiconductor device with improved salicide structure and a method of manufacturing the same |
| US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
| US5783479A (en) * | 1997-06-23 | 1998-07-21 | National Science Council | Structure and method for manufacturing improved FETs having T-shaped gates |
| WO1999030361A1 (en) * | 1997-12-09 | 1999-06-17 | Advanced Micro Devices, Inc. | Spacer formation for precise salicide formation |
-
2000
- 2000-06-28 WO PCT/DE2000/002101 patent/WO2001003200A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5739573A (en) * | 1994-07-22 | 1998-04-14 | Nec Corporation | Semiconductor device with improved salicide structure and a method of manufacturing the same |
| US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
| US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
| US5783479A (en) * | 1997-06-23 | 1998-07-21 | National Science Council | Structure and method for manufacturing improved FETs having T-shaped gates |
| WO1999030361A1 (en) * | 1997-12-09 | 1999-06-17 | Advanced Micro Devices, Inc. | Spacer formation for precise salicide formation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10775863B2 (en) | 2003-08-15 | 2020-09-15 | Apple Inc. | Methods and apparatuses for controlling the temperature of a data processing system |
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