WO2001004770A3 - Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list - Google Patents

Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list Download PDF

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Publication number
WO2001004770A3
WO2001004770A3 PCT/US2000/018939 US0018939W WO0104770A3 WO 2001004770 A3 WO2001004770 A3 WO 2001004770A3 US 0018939 W US0018939 W US 0018939W WO 0104770 A3 WO0104770 A3 WO 0104770A3
Authority
WO
WIPO (PCT)
Prior art keywords
linked list
ram
index fifo
architecture
data throughput
Prior art date
Application number
PCT/US2000/018939
Other languages
French (fr)
Other versions
WO2001004770A2 (en
Inventor
Keith Lee
Dean Schmaltz
Original Assignee
Alteon Web Systems Inc
Keith Lee
Dean Schmaltz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alteon Web Systems Inc, Keith Lee, Dean Schmaltz filed Critical Alteon Web Systems Inc
Priority to AU59297/00A priority Critical patent/AU5929700A/en
Publication of WO2001004770A2 publication Critical patent/WO2001004770A2/en
Publication of WO2001004770A3 publication Critical patent/WO2001004770A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues

Abstract

A method and architecture for optimizing data throughput in a multiprocessor environment makes use of a RAM-based, shared index FIFO linked list, in which data to be processed is written to a central buffer and the index FIFO, constituting a linked list of indexes to the buffered data is passed between processing units within the system, providing a substantial reduction in the gate count required for processing the data. Messages are written to a central buffer; a linked list of indexes to the messages is created, and then pipelined to a processing unit as an index FIFO, so that the processor reads the entries of the linked list in sequence; as the entries are read, a message indicated by the entry is processed. Entries are enqueued and dequeued in an index FIFO RAM, so that enqueuing and dequeuing are performed in a single cycle with a single write operation.
PCT/US2000/018939 1999-07-13 2000-07-11 Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list WO2001004770A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU59297/00A AU5929700A (en) 1999-07-13 2000-07-11 Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14344599P 1999-07-13 1999-07-13
US60/143,445 1999-07-13

Publications (2)

Publication Number Publication Date
WO2001004770A2 WO2001004770A2 (en) 2001-01-18
WO2001004770A3 true WO2001004770A3 (en) 2001-08-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/018939 WO2001004770A2 (en) 1999-07-13 2000-07-11 Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list

Country Status (2)

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AU (1) AU5929700A (en)
WO (1) WO2001004770A2 (en)

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US6427171B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6226680B1 (en) 1997-10-14 2001-05-01 Alacritech, Inc. Intelligent network interface system method for protocol processing
US6434620B1 (en) 1998-08-27 2002-08-13 Alacritech, Inc. TCP/IP offload network interface device
US6427173B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Intelligent network interfaced device and system for accelerated communication
US6807581B1 (en) 2000-09-29 2004-10-19 Alacritech, Inc. Intelligent network storage interface system
US6697868B2 (en) 2000-02-28 2004-02-24 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US6687758B2 (en) 2001-03-07 2004-02-03 Alacritech, Inc. Port aggregation for network connections that are offloaded to network interface devices
US6389479B1 (en) 1997-10-14 2002-05-14 Alacritech, Inc. Intelligent network interface device and system for accelerated communication
US8782199B2 (en) 1997-10-14 2014-07-15 A-Tech Llc Parsing a packet header
US7042898B2 (en) 1997-10-14 2006-05-09 Alacritech, Inc. Reducing delays associated with inserting a checksum into a network message
US7237036B2 (en) 1997-10-14 2007-06-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding a TCP connection
US7284070B2 (en) 1997-10-14 2007-10-16 Alacritech, Inc. TCP offload network interface device
US6658480B2 (en) 1997-10-14 2003-12-02 Alacritech, Inc. Intelligent network interface system and method for accelerated protocol processing
US6757746B2 (en) 1997-10-14 2004-06-29 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US8019901B2 (en) 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
US7543087B2 (en) 2002-04-22 2009-06-02 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device
DE10360637B4 (en) * 2003-12-19 2010-10-07 Infineon Technologies Ag Program controlled unit
US8539513B1 (en) 2008-04-01 2013-09-17 Alacritech, Inc. Accelerating data transfer in a virtual computer system with tightly coupled TCP connections
US8341286B1 (en) 2008-07-31 2012-12-25 Alacritech, Inc. TCP offload send optimization
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies
EP2282264A1 (en) 2009-07-24 2011-02-09 ProximusDA GmbH Scheduling and communication in computing systems
CN109558107B (en) * 2018-12-04 2023-06-30 中国航空工业集团公司西安航空计算技术研究所 FC message receiving management method for shared buffer area

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Publication number Publication date
AU5929700A (en) 2001-01-30
WO2001004770A2 (en) 2001-01-18

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