WO2001008001A1

WO2001008001A1 - Integer discrete cosine transform using integer operations

Info

Publication number: WO2001008001A1
Application number: PCT/US2000/020126
Authority: WO
Inventors: Truong Q. Nguyen; Ying-Jui Chen; Soontorn Oraintara
Original assignee: Trustees Of Boston University
Priority date: 1999-07-23
Filing date: 2000-07-24
Publication date: 2001-02-01
Also published as: AU6118700A

Abstract

A method and apparatus (102) for performing a Discrete Cosine Tranform (DCT) using only integer multipliers is disclosed. Input data is coupled to a Walsh-Hadamard transform (202) and the transformed data is then reordered by a bit-reverse transform (204) and passed to the T-kernel (206), in which a plurality of integer lifting stages are utilized to perform the necesserary rotations of various pairs of re-ordered tranformed data. Each of the integer lifting stages includes three internal lifting steps that include an integer multiplier or multiplying an input by a predetermined constant and a bit shifting means. The predetermined constant is quantized to a predetermined level, and the bit shifting means shift the product of integer multiplier an equivalent number of bits to the right.

Description

TITLE OF THE INVENTION INTEGER DISCRETE COSINE TRANSFORM USING INTEGER OPERATIONS

CROSS REFERENCE TO RELATED APPLICATIONS

N/A

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR

DEVELOPMENT N/A

BACKGROUND OF THE INVENTION The Discrete Cosine Transform (DCT) is widely used in image coding, and the DCT is currently part of the JPEG and MPEG industry standards used for still image and video image coding and compression. The DCT uses deterministic cosine basis functions independent of the input signals, and since each of the cosine basis functions has linear phase, the DCT is a preferred alternative to the optimum Karhunan Loeve transform. As a result of the real-valued cosine basis the conventional DCT uses floating-point operations and therefore maps integer input data into floating-point output data. To avoid floating-point output data, a non-linear operation such as ROUND or FLOOR may be used to truncate the floating-point output into integers. However, this operation is not invertible and therefore lossless compression is not possible using such non-linear operations .

The use of floating-point operations in a conventional DCT image processor chip may consume too much power for certain devices. A conventional DCT image processor chip that utilizes internal floating-point operations will need at least five (5) floating-point multipliers for efficient operation, which may require large areas of silicon within the image processor chip. The power consumption of a DCT image processor chip is, in general, proportional to the area of silicon used by the chip. Thus, the larger the area of silicon an image processing chip contains, the more power it will consume and dissipate. Therefore, the power consumption and dissipation of a conventional DCT image processor chip that uses floating-point multiplications may be unacceptably high when used in mobile and portable devices such as portable computers, laptop computers, or personal digital assistants (PDA's).

Prior art solutions to this problem of excess power consumption have involved proprietary algorithms that while possibly having lower power consumption than the conventional DCTs, often are not compliant with the standards (JPEG or MPEG) . This non-compliance may, under some circumstances, lead to a noticeable degradation in the image quality.

It would, therefore, be desirable to provide a DCT that reduces the number of floating-point multiplications and can be used within a standard-compliant compression scheme (JPEG or MPEG) without a degradation of picture quality.

BRIEF SUMMARY OF THE INVENTION A method and apparatus for performing a discrete cosine transform using only integer operations on a plurality of integer input data is disclosed. The method and apparatus include a plurality of predetermined integer coefficients. These coefficients are used in integer operations operating on the plurality of integer input data to provide an integer-to-integer mapping from the input data to a plurality of discrete cosine transform coefficients.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which:

Fig.l is a block diagram of a DCT encoder/decoder system;

Fig. 2 is a block diagram of further illustrating the DCT transform block shown in Fig. 1;

Fig. 3 is a block diagram further illustrating the T- kernel block shown in Fig. 2; Figs 4A and 4B show an lifting stage using floatingpoint multipliers;

Fig. 5 shows an integer lifting stage including three lifting steps using only integer multipliers;

Fig. 6 is a block diagram of a preferred embodiment of a T-kernel block shown in Fig. 2;

Fig. 7 is a block diagram of a butterfly rotator for a Givens rotation to rotate a 2-tuple vector on a plane;

Fig. 8 is a block diagram of a preferred embodiment of an inverse T-kernel.

DETAILED DESCRIPTION OF THE INVENTION

A method and system in accordance with the present invention for computing Discrete Cosine Transform (DCT) coefficients using only integer multipliers and bit-shifting operations is disclosed. Referring to Fig. 1, a block diagram of a typical transform based image/video coder/decoder is shown. The input data 101 is transformed by the Discrete Cosine Transform (DCT) 102 into a plurality of DCT coefficients, in order to compact the energy of the time-spatial samples into a number of DCT transform coefficients These DCT coefficients may be compressed using known techniques such that the compressed coefficients contain substantially the same information as the original video-image or still-image data. A quantizer 104 is used to remove statistical redundancies within the DCT coefficients and to reduce the dynamic range of the DCT coefficients as well. The quantizer 104 is inherently lossy since some data must be removed or changed to accomplish the above criteria. Finally, a lossless entropy encoder 106 is used to code the quantized-transformed-coefficients into a bit-stream of data. The bit-stream data is transmitted over a channel 108 or stored in a memory (not shown) .

The image/video decoder receives the transmitted bit- stream data or retrieves the bit-stream data from the memory and performs the inverse mathematical operations of the image/video encoder. A lossless entropy decoder 110 is used to convert the bit-stream data into data for the processing that follows. An inverse quantizer 112 reverses the quantization of the data and an inverse DCT transform 114 is performed to create the data necessary to display an image or video frame.

The DCT transform block 102 and the inverse DCT transform block 114 mathematically are the inverse operations of one another. The DCT transform is used to transform the time domain spatial data into spatial frequency domain data, and the inverse DCT transform is used to transform the spatial frequency domain data into time domain spatial data.

In the presently disclosed DCT encoder/decoder, the transform block 102 may be further illustrated by the block diagram illustrated in Fig. 2. In this embodiment the DCT transform is comprised of four (4) stages of processing. The input data 101 is coupled to the Walsh-Hadamard transformer 202. TABLE 1 illustrates a matrix representation of the Walsh-Hadamard transform (WHT) 202 for an 8-point input. The WHT is an orthogonal transformation in which the matrix entries are either 1 or -1 and, therefore, only additions are required for matrix operations. Any form of the WHT including a version of the fast-WHT may be used as this transform.

TABLE 1

The transformed data is then re-ordered by bit-reverse transform 304. TABLE 2 illustrates a bit-reverse matrix that can be used to rearrange the input data into the necessary bit-reversed order in accordance with the present invention. The bit-reverse matrix (B) , 304 as illustrated in TABLE 2 is such that 6 = 8 T' a„„nd_] Jt-ha-,t- DBiBli

TABLE 2

The T-kernel 206 performs the transformation of the data 101 that has been transformed' and rearranged by the preceding two stages. The DCT is defined as

where x(n) is the input sequence of length N, and X(k) is one of the N DCT coefficients. Based on equation (1), the kernel C for an 8-point DCT, i.e., N = 8, is given by TABLE 3. TABLE 3

where CQ = Cos (θ) and - _> = -Cos(θ). This is an orthogonal matrix and, in general, an NxN orthogonal matrix may be decomposed into N(N-l) rotations. Thus, an 8 x 8 orthogonal matrix could be decomposed to 28 rotation angles. The direct implementation of an 8-point DCT that uses 28 rotation angles could be implemented effeciently using the WHT and the T-kernel matrix described in TABLE 4. However, because of the underlying symmetry of the T-kernel matrix above, only 5 rotation angles are needed. As such, the T-kernel matrix in TABLE 4 can be implemented using only 5 rotation angles. TABLE 4

Each of the rotation angles may be represented by the orthogonal rotation matrix:

where Cø = Cos (θ) and Sø = Sin(#) and the subscript R indicates a rotated coordinate. This matrix structure can be implemented as a single dual butterfly rotator as illustrated in Fig. 7. Fig. 7 illustrates a single butterfly rotator for rotating a two-tuple vector according to equation (2) . First and second input data, 701 and 702 respectively, are provided, and the first input data 701 is multiplied by Cos (θ) 704 and Sin(θ) 706. The second input data 702 is multiplied by Cos(θ) 710 and -Sin(θ) 708. The products from multipliers 704 and 708 are added together in adder 712 to provide first output data 716. Similarly, the products from multipliers 706 and 710 are added together in adder 714 to provide second output data 718. Fig. 3 illustrates one embodiment of a signal flow structure that implements the T-kernel in TABLE 4. Input data 301 is coupled to a WHT transform stage 302 that performs a Walsh-Hadamard transform. In one embodiment the above described WHT matrix illustrated in TABLE 1 may be used. Alternatively, a known fast form of the WHT may be used. The WHT-transformed data 303 is coupled to a bit- reverse matrix 304. The bit-reversed-WHT-transformed data is then coupled to a T-kernel 306 such that the combination of the WHT and bit-reversal along with the T-kernel matrix and another bit-reversal 320 performs of the eight (8) -point DCT illustrated in TABLE 3. As illustrated in Fig. 3, the butterfly rotators are depicted without internal detail, however, it should be understood that the internal operations of each of the butterfly rotators is similar to that of Fig. 7 and uses as a rotation angle the respective rotation angles given below. Rotation 314 is a -π/8 rotation between the third and fourth data lines 324 and 326. Rotation 308 is a 3π/8 rotation of data lines 328 and 332, and rotation 310 is also a 3π/8 rotation of data lines 330 and 334. The data is then re-ordered and sign flipped as appropriate in section 313 and a 7π/16 rotation 316 is performed on data lines 336 and 342, and a 3π/16 rotation 318 of data lines 338 and 340, completes the T-kernel calculation. The multipliers 348, 346, and 344 are used to change the sign of the resulting coefficient data is again re-ordered by a bit-reverse matrix 320 and the correctly ordered DCT coefficients 322 are output.

Figure 4A illustrates an alternative architecture for implementing a rotation matrix (2) . In Figs. 4A and 4B, ^λC" is to be understood as Cos (θ) and S is to be understood as Sin(θ). In this embodiment, the rotation is achieved using three (3) lifting steps 406, 408, and 410 in which a single- wing butterfly architecture is used. Data is provided as first and second inputs 402 and 404. The second input data 404 is multiplied by the constant 412, which is given by:

Cos(θ) -\ Sin(θ) where θ is the rotation angle between the input and output data. This product 430 is added, in adder 414, to the first input data 402 and this sum 428 is multiplied by the constant 416 which is given by:

Sin(θ) ( 4 ) where θ is the rotation angle between the input and output data. This product 432 is added, in adder 418, to the second input data 404, and this sum, which is the second output data 426, is multiplied by the constant 420 which is provided by equation (3) above. This product 434 is added, in adder 422 to the sum 428 from adder 414 to provide the first output data 424. The inverse of the rotation shown in Fig. 4A is accomplished by subtracting, instead of adding, the products 430, 432, and 434 in the adders 414, 418, and 422 respectively in the reverse order. As illustrated in Fig. 4A, each of the multipliers used in the three (3) lifting steps will be a floating-point multiplier.

Fig. 4B illustrates a variation of the architecture illustrated in Fig. 4A in which a non-linear operator Q 434, has been inserted in the lifting steps 406, 408, and 410 between the multipliers 412, 416, and 420 and the adders 414, 418, and 422 respectively. The non-linear operator Q 434 may be a non-linear function such as FLOOR or ROUND and may be used to quantize the products 430, 432, and 434 to provide integer values. Similarly, each of the multipliers used in the three (3) lifting steps illustrated in Fig. 4B will be a floating-point multiplier.

In an alternative architecture, which is a preferred embodiment of the present invention, as illustrated in Fig. 5, the three (3) lifting steps described above are shown in which only integer values are used in all internal operations. Thus, in this preferred embodiment, no floating-point multiplications are used, with the concomitant decrease in the silicon area used by an image processor chip. Input data is provided as first and second input data 501 and 503 respectively. The structure of the lifting steps is the same as in Fig. 4A with the floatingpoint multipliers 412, 416, and 420 replaced by integer constant multipliers 504, 508, and 512 and respective right shift means 502, 506, and 510. The integer constant multipliers 504, 508, and 512 multiply their respective integer inputs by a predetermined integer constant, which in one embodiment is the quantized value of the predetermined constants 412, 416, and 420 respectively. The predetermined integer constants are calculated by multiplying the value of the floating-point constants 412, 416, and 420 respectively by a power of 2, i.e., 2¹, 2², 2³, . . ,2⁸, and truncating the result to an integer value. The power of two used to quantize the floating-point constants is also known as the quantization level. After the integer multiplication is complete, the products 532, 534, and 536 are right shifted by right-shift eans 502,^' 508, and 510 respectively. The »a and »b notation indicates that the input is shifted a or b bits to the right. The values a and b, i.e., the number of bits the product are shifted to the right, is equivalent to the quantization level used to quantize the floating-point constants as described above. Because the multiplicands are integers and the multipliers 504, 508, and 512 are integer as well, as is known in the art, the multiplications 504, 508, and 512 can be carried out using only bit shifts and adds. Using only bit shifts and adds in the integer multipliers obviates the need for floating-point multipliers, reducing the area of the silicon required in an image processing chip and thereby reducing the power required by the image processing chip as well. Exemplary values for the predetermined constants and the number of bits to be shifted are given in TABLE 5 for a number of bits, i.e., of quantization levels, from 1-8. It should be understood that other values greater than 8 may be used depending upon the system characteristics and capabilities. The values are generated by computing the values for each of the three lifting stage coefficients for a given rotation angle and multiplying the lifting stage coefficient by a power of two, or a sum of two or more powers of two, and truncating or rounding the result. This quantization level, i.e., the exponent of the power of two used to quantize the lifting stage coefficients is the number of bits the output product from each integer multiplier will shifted to the right. TABLE 5

The choice of the quantization level of the predetermined constants can determine one aspect of the overall level of complexity of the DCT transform stage. Quantization using a larger number of bits may increase the quality of the image; however, a larger quantization level may also increase the number of additions and bit-shifting operations needed to carry out the integer multiplications. However, using a quantization level that is too small can lead to a degradation of the image quality.

A preferred embodiment of an integer DCT in accordance with the present invention is illustrated in Fig. 6. In this embodiment, the input data 602 is transformed by WHT 604 to provide transformed data 606 to the bit-reversing stage 608. The bit-reversing stage 608 provides the bit- reversed-WHT-transformed input data to the T-kernel 610, along with the subsequent bit-reversing stage 624, calculates the DCT coefficients using the integer lifting steps described above. Each multiplier in Fig. 6 is shown as a triangle with the constant value in it. These multipliers multiply their respective inputs, and the resultant products are coupled to the respective bit-shift means. The bit-shift means shift the results from the multiplier to the right by an appropriate number of bits. As discussed above, the notation "»a" and "»b" indicates the number of bits that the integer data is to be shifted to the right. Rotation 612, which is a -π/8 rotation, utilizes a two-bit quantization level for each of the first and third lifting steps, and a one-bit quantization level for the second lifting step. Rotation 614, which is a 3π/8 rotation, includes a three bit quantization level for the first and third lifting steps, and a zero-bit quantization level for the second lifting step. Rotation 616, which is a 3π/8 rotation, includes a three bit quantization level for the first and third lifting steps, and a zero-bit quantization level for the second lifting step. Rotation 618, which is a 7π/16 rotation, includes a two-bit quantization level for the first and third lifting steps, and a zero-bit quantization level for the second lifting step. Rotation 620, which is a 3π/16 rotation, includes a two-bit quantization level for the first and third lifting steps, and a one-bit quantization level for the second lifting step. All of the addition modules 628-656 perform integer additions between their respective inputs. In a preferred embodiment in which only bit-shifts and adds are used for the integer multipliers, a multiplierless DCT is illustrated in Fig. 6 that uses 45 adds and 18 bit-shifts. As will be discussed in greater detail below, the inverse DCT of the embodiment illustrated in Fig.6 may be obtained by using subtraction modules instead of the addition modules and reordering the various lifting stages. Thus a similar architecture may be used for a multiplierless Inverse DCT.

Fig. 8 illustrates one embodiment of an inverse DCT according to the present invention. As discussed with respect to Fig. 6, each multiplier in Fig. 8 is shown as a triangle with its constant value within it. These multipliers multiply their respective inputs and the resultant products are coupled to the respective bit-shift means. The bit-shift means shift the results from the multiplier to the right by an appropriate number of bits. As discussed above, the notation "»a" and "»b" indicates the number of bits that the integer data is to be shifted to the right.

As illustrated in Fig. 8, DCT coefficient data 801 is reordered by the transpose bit-reverse matrix 802. The bit- reverse data is provided to the inverse T-kernel 804. The inverse T-kernel 804 includes the five (5) rotations discussed above; however, the rotations are in a different order. Rotation 806, which is a -π/8 rotation, utilizes a two-bit quantization level for the first and third lifting steps and a one-bit quantization level for the second lifting step. Rotation 810, which is a 3π/16 rotation, utilizes a two-bit quantization level for the first and third lifting steps and a one bit quantization level for the second lifting step. Rotation 812, which is a 7π/16 rotation, utilizes a two-bit quantization level for the first and third lifting steps and a zero-bit quantization level for the second lifting step. Rotations 814 and 816, which are 3π/8 rotations, utilize a three-bit quantization level for the first and third lifting steps and a zero-bit quantization level for the second lifting step. All of the subtraction modules 826-854 subtract the lifting step outputs from the other inputs to the subtraction modules. In addition, all the subtraction modules 826-854 perform integer subtraction between the two inputs. In a preferred embodiment all of the integer multipliers are implemented using left-shift and integer addition operations.

Those skilled in the art should readily appreciate that computer programs operative to perform the functions herein described can be delivered to an image processor in many forms including, but not limited to: (a) information permanently stored in a non-volati'le storage media (e.g. Read Only Memory Device) devices within a computer such as a ROM or CD-ROM disks readable by a computer I/O Attachment; (b) information alterably stored on a erasable storage media (e.g. floppy disks, tapes, read-write optical media and hard drives) ; or (c) information conveyed to a computer through a communication media, for example, using baseband or broad band signaling techniques, such as over computer or telephone networks via a modem. Alternatively, the presently described functions may be embodied in whole or in part using hardware components such as Application Specific Integrated Circuits (ASIC) , state machines, programmable logic devices, controllers or other hardware components or other devices, or a combination of hardware components and software processes without departing from the inventive concepts herein described. Those of ordinary skill in the art should further appreciate that variations to and modification of the above-described methods and apparatus for an integer DCT using only integer multipliers may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should be viewed as limited solely by the scope spirit of the appended claims.

Claims

1. A method for performing a discrete cosine transform using only integer operations on a plurality of integer input data, the method comprising the steps of: providing a plurality of predetermined integer coefficients; operating on the plurality of integer input data with integer operations using said plurality of predetermined integer coefficients to provide an integer-to-integer mapping from said input data to said discrete cosine transform coefficients

2. The method of claim 1 wherein said operating step includes: using a plurality of lifting stages, each of said plurality of lifting stages being operative to rotate a pair of two distinct data by a given angle.

3. The method of claim 2 further including the steps of: receiving at each of said lifting stages a first and second input data; integer-multiplying said second input data by a first one of said plurality of predetermined constants to provide a first product; right shifting said first product a first predetermined number of bits; adding said right-shifted first product to said first input data to provide a first sum data; integer-multiplying said first sum data by a second one of said plurality of predetermined constants to provide a second product data; right shifting said second product a second predetermined number of bits; adding said right-shifted second product to said second input data to provide a second sum data, which is the second output data; integer-multiplying said second sum data by said first one of said plurality of predetermined constants to provide a third product data; right shifting said third product said first predetermined number of bits; adding said right-shifted third product to said first sum data to provide the first output data.

4. The method of claim 3 wherein the steps of integer-multiplying include using appropriate left-shifting of the integer multiplicands based on the integer multipliers and performing integer additions between the shifted and the non-shifted multiplicands.

5. The method of claim 3 wherein the step of integer multiplying includes using a quantized lifting coefficient

6. The method of claim 1 further including the steps prior to the operating step of: transforming the plurality of input data using a Walsh- Hadamard transform to provide a plurality of transformed input data; reordering using bit-reversal the plurality of transformed input data.

7. The method of claim 6 further including the step subsequent to the operating step of: reordering using bit-reversal the plurality of discrete cosine transform coefficients.

8. A method for performing an inverse discrete cosine transform using only integer operations on a plurality of integer input data, the method comprising the steps of: providing a plurality of predetermined integer coefficients; operating on a plurality of integer input data using integer operations using said plurality of predetermined integer coefficients to provide an integer-to-integer mapping from said input data to said inverse discrete cosine transform coefficients

9. The method of claim 8 wherein said operating step includes: using a plurality of inverse lifting stages, each of said plurality of lifting stages being operative to rotate a pair of two distinct data by a given angle.

10. The method of claim 9 further including the steps of: receiving at each of said lifting stages a first and second input data; integer-multiplying said second input data by a first one of said plurality of predetermined constants to provide a first product; right shifting said first product a first predetermined number of bits; subtracting said right-shifted first product from said first input data to provide a first sum data; integer-multiplying said first sum data by a second one of said plurality of predetermined constants to provide a second product data; right shifting said second product a second predetermined number of bits; subtracting said right-shifted second product from said second input data to provide a second sum data, which is the second output data; integer-multiplying said second sum data by said first one of said plurality of predetermined constants to provide a third product data; right shifting said third product a first predetermined number of bits; subtracting said right-shifted third product from said first sum data to provide the first output data.

11. The method of claim 10 wherein the steps of integer-multiplying include using appropriate left-shifting of the integer multiplicands based on the integer multipliers and performing integer additions between the shifted and the non-shifted multiplicands.

12. The method of claim 8 further including the step prior to the operating step of reordering, using a transpose of a bit-reversal matrix, the plurality of integer input data.

13. The method of claim 12 further including, subsequent to the operating step, the steps of: reordering, using a transpose of a bit-reversal matrix, using said plurality of inverse lifting stages; and transforming the plurality of reordered data using a transpose of a Walsh-Hadamard transform to provide a plurality of inverse discrete cosine transform coefficients.

14. An apparatus for computing the discrete cosine transform of a plurality of input data, the apparatus comprising: a WHT transformation stage coupled to said plurality of input data and operative to provide a plurality of first transformed data; a first data re-ordering stage coupled to said first transformation stage and operative to re-order said plurality of first transformed data to provide a plurality of re-ordered data in bit-reversed order; a T-kernel stage coupled to said data re-ordering stage, said T-kernel comprising a plurality of integer lifting stages, each of said plurality of integer lifting stages operative to rotate a pair of said plurality of reordered data, to provide a plurality of DCT data; and a second data re-ordering stage coupled to said T- kernel stage and operative to re-order using bit-reversal said plurality of DCT data into a plurality of ordered DCT coefficients.

15. The apparatus of claim 14 wherein each of said plurality of integer lifting stages includes: first and second inputs coupled to a first and second input data; a first multiplier having an input coupled to said second input data for multiplying a said input by a first predetermined integer constant, said first multiplier having an output coupled to an input of a first shifting module for shifting said data at said input by a first predetermined number of bits, said shifting module having an output coupled to a first input of a first adder, said first adder having a second input coupled to said first input data, said first adder having a first output sum data; a second multiplier having an input coupled to said first output sum data, for multiplying said input by a second predetermined integer constant, said second multiplier having an output coupled to an input of a second shifting module for shifting said data at said input by a second predetermined number of bits, said second shifting module having an output coupled to a first input of a second adder, said second adder having a second input coupled to said second input data, said second adder having a second output sum data; a third multiplier having an input coupled to said second output sum data, for multiplying said input by a third predetermined integer constant, said third multiplier having an output coupled to an input of a third shifting module for shifting said data at said input by a third predetermined number of bits, said third shifting module having an output coupled to a first input of a third adder, said third adder having a second input coupled to said first output sum data, said third adder having a first output sum data;

16. The apparatus of claim 15 wherein the predetermined constants are a quantized lifting stage coefficient.

17. The apparatus of claim 16 wherein the quantized lifting stage coefficients are a function of a rotation angle divided by the quantizaiton level.

18. The apparatus of claim 17 wherein the quantization level is a power of two.

19. The apparatus of claim 17 wherein the quantization level is the sum of two or more powers of two.

20. The apparatus of claim 15 wherein the first and third number of predetermined bits are equal.

21. The apparatus of claim 20 wherein the first and second number of predetermined bits are equal to a power of 2.

22. The apparatus of claim 19 wherein the third predetermined integer constant is equal to the first predetermined integer constant.

23. The apparatus of claim 22 wherein the first and second predetermined integer constants are a function of quantized lifting multipliers.

24. The apparatus of claim 23 wherein the function of quantized lifting multipliers is equal to the truncated product of the lifting multiplier and a quantization value.

25. The apparatus of claim 24 wherein the quantization value is a power of 2.

26. An apparatus for computing the inverse discrete cosine transform of a plurality of input data, the apparatus comprising: a transposed first bit-reversing stage coupled to said input data and operative to re-order using bit-reversal said plurality of input data into a plurality of bit-reversed data a transposed T-kernel stage coupled to said bit- reversing stage, said T-kernel comprising a plurality of integer lifting stages, each of said plurality of integer lifting stages operative to rotate a pair of said plurality of bit-reversed data, to provide a plurality of output data; a transposed second bit reversing stage coupled to said T-kernel stage and operative to re-order in a bit-reverse order a plurality of output transpose T kernel data; and a transposed WHT stage coupled to said transposed second bit reversing stage and operative to provide a plurality of inverse DCT coefficients.

27. The apparatus of claim 26 wherein each of said plurality of integer lifting stages includes: first and second inputs coupled to a first and second input data; a first multiplier having an input coupled to said second input data for multiplying a said input by a first predetermined integer constant, said first multiplier having an output coupled to an input of a first shifting module for shifting said data at said input by a first predetermined number of bits, said shifting module having an output coupled to an input of a first subtraction module, said first subtraction module having an input coupled to said first input data, said first subtraction module having a first sum data; a second multiplier having an input coupled to said first sum data, for multiplying said input by a second predetermined integer constant, said second multiplier having an output coupled to an input of a second shifting module for shifting said data at said input by a second predetermined number of bits, said second shifting module having an output coupled to a first input of a second subtraction module, said second subtraction module having a input coupled to said second input data, said second subtraction module having a second sum data, and wherein the second sum data is the second output data; a third multiplier having an input coupled to said second sum data, for multiplying said input by a third predetermined integer constant, said third multiplier having an output coupled to an input of a third shifting module for shifting said data at said input by a third predetermined number of bits, said third shifting module having an output coupled to an input of a third subtraction module, said third adder having an input coupled to said first output sum data, said third subtraction module having a first output data.

28. The apparatus of claim 27 wherein the predetermined constants are a quantized lifting stage coefficient .

29. The apparatus of claim 28 wherein the quantized lifting stage coefficients are a function of a rotation angle divided by the quantizaiton level.

30. The apparatus of claim 28 wherein the quantization level is a power of two.

31. The apparatus of claim 28 wherein the quantization level is the sum of two or more powers of two.

32. The apparatus of claim 27 wherein the first and third number of predetermined bits are equal.

33. The apparatus of claim 32 wherein the first and second number of predetermined bits are equal to a power of

2.

34. The apparatus of claim 31 wherein the third predetermined integer constant is equal to the first predetermined integer constant.

35. The apparatus of claim 34 wherein the first and second predetermined integer constants are a quantized lifting stage coefficient.

36. The apparatus of claim 35 wherein the quantized rotation angle is equal to the truncated product of the lifting stage coefficient and a quantization value.

37. The apparatus of claim 36 wherein the quantization value is a power of 2.