WO2001009943A1 - Process for the forming of isolation layers of a predetermined thickness in semiconductor wafers for the manufacturing of integrated circuits - Google Patents

Abstract

A process for forming insulating layers of predetermined thickness in semiconductor wafer for manufacturing integrated circuits by means of Ζ/N?+(+)/N(-)¿-type structures comprises the steps of: forming one or more regions of N+(+) semiconducting material inside a N(-) semiconducting material substrate; growing an epitaxial layer on the semiconducting material; defining an island structure by removing part of the epitaxial layer; selectively anodizing these regions for forming porous silicon and performing oxidation of the formed porous silicon regions.

Description

PROCESS FOR THE FORMING OF ISOLATION LAYERS OF A

PREDETERMINED THICKNESS IN SEMICONDUCTOR WAFERS FOR THE

MANUFACTURING OF INTEGRATED CIRCUITS

DESCRIPTION The present invention refers to a process for forming insulating layers of predetermined thickness in semiconductor wafer for manufacturing integrated circuits.

In particular this invention refers to a process for forming Φ N⁺⁽⁺⁾ N^(")-type structures for semiconductor integrated circuits, preferably showing a hyperfine transition region between the Φ semiconducting material layer and the N^"1^ semiconducting material layer, with the possibility of modulating the thickness of the

N⁺⁽⁺⁾ layer for forming porous silicon and then for the oxidation thereof to obtain buried insulated layers with possible different thickness and furthermore with the possibility of obtaining even Φ islands with thicknesses different between them. The Φ symbol designates silicon which can be N-type, or N^"-type, or P-type, or P^~-type or, at last, Sii-type. Under Sii silicon, intrinsic silicon that is non-doped silicon will be meant.

Since a uniform definition of doping levels does not exist in literature, in the following description: • under P^"silicon, silicon showing a dopant (e.g. Boron) atom concentration lower than 10¹⁵ atoms/cm³ will be meant;

• under P-silicon, silicon showing a dopant (e.g. Boron) atom concentration between 10¹⁵ and 10¹⁷ atoms/cm³ will be meant;

• under N^"-silicon, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration lower than 10¹⁵ atoms/cm³ will be meant;

• under N-silicon, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration between 10¹⁵ and 10¹⁷ atoms/cm³ will be meant;

• under N^-silicon, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration between 10¹⁷ and 10¹⁹ atoms/cm³ will be meant; and • under N^-silicon, at last, silicon showing a dopant (e.g. Phosphorus, Antimony,

Arsenic) atom concentration greater than 10¹⁹ atoms/cm³ will be meant.

In the following description and in the drawings, under the N⁹ symbol, silicon which can be N-type or N^"-type will be meant. Likewise, under the N^ symbol, silicon which can be N^-type or N^-type will be meant. Under the P^("} symbol, silicon which can be P-type or P^"-type will be meant.

The field of the invention refers to the manufacturing of silicon-on-insulator structures (SOI), that is semiconductor structures showing silicon regions electrically isolated from the substrate by an oxidized porous silicon. This manufacturing process is known under the FIPOS term (Full Isolation by Porous Oxidized Silicon).

The present invention in particular refers to processes for manufacturing FIPOS structures wherein it is possible modulating the oxide thickness based upon the selective anodization of the N⁺⁽⁺⁾ layer inside a Φ/N⁺⁽⁺⁾/N^(") structure and subsequent oxidation. In fact, these processes provide a first step wherein doped silicon is transformed into porous silicon (anodization step) and a second step wherein porous silicon is transformed into silicon dioxide (oxidation step). The formation of these structures is obtained by exploiting the high chemical reactivity of porous silicon. The easiness in oxidizing of porous silicon compared to "bulk" silicon allows oxidizing a porous silicon layer buried between two layers of silicon.

The semiconductor devices manufactured by means of SOI technology offer several advantages compared to the conventional technology of silicon ("bulk silicon"). Among the main advantages of SOI technology, the power consumption decrease, the elimination of the "latch-up" effect in CMOS circuits, a faster device operation thanks to the decrease in parasitic capacitance's and a higher immunity to ionizing radiations may be found.

SOI devices may be classified both according to the thickness of silicon layer over the oxide and to the thickness of buried oxide. This kind of classifications are mentioned for example in the book "Physical and technical problems of SOI structures and devices" published by J. P. Colinge, V.S. Lysenko and A. N. Nazarov, NATO ASI, series High Technology, v. 4 or in Dataquest market analysis of 24 April 1998 "SOI wafer market trends: application perspectives" written by Clark Fuhs and Takashi Ogawa. A current disadvantage of SOI technology is that SOI structures cannot be manufactured wherein thickness' different between them of the buried insulating silicon dioxide layer and of the silicon layer over the oxide inside the same chip (thickness modulation) may be manufactured. In fact, by means of BESOI (Bonded and Etch back Silicon On Insulator) technology or the variations thereof such as SMART CUT technique, it is impossible to modulate thickness since two wafer must perfectly match to weld together and obtain a SOI-type wafer.

SLMOX technique which enables manufacturing SOI wafer by implanting oxygen could in principle provide a thickness modulation by means of a masking procedure during the implantation step, but, up to now, it apparently has not been performed. In fact, in order to obtain high thickness' of buried oxide, doses have to be quite high and this causes damage to the silicon over it. For this reason with SLMOX technique structures with buried oxide lower than one micron tend to be manufactured and thin oxide layers of about hundreds of nm tend to be obtained for reducing damage of the silicon layer over the oxide and reducing time of thermal treatment. However, insulator discontinuous structures have been manufactured by SLMOX technique, see for example H. Vogt " Advantages and potential of SOI structures for smart sensors" SOI Technology and Devices. Pennington:

Electrochem. Soc. p. 430, 1994.

This limitation is in conflict with the important need of integrating analogous and/or digital devices and/or low, medium and high power and/or voltage devices on the same integrated circuit, which would provide a high flexibility, an increase in reliability and a cost reduction for the electronic system compared to "bulk silicon" devices.

The present invention overcomes the above illustrated problems since it provides a process for forming insulating layers, of predetermined thickness, in semiconductor wafer for manufacturing integrated circuits by means of Φ/N⁺⁽⁺VN^(')- type structures, characterized in that it comprises the steps of: a) forming one or more regions of N^ semiconducting material inside a N^H semiconducting material substrate; b) growing a Φ-type epitaxial layer on said substrate of N^(_) semiconducting material, said growing being performed so as to obtain a predetermined layer of the Φ-type epitaxial layer; c) defining an island structure by removing part of said Φ-type epitaxial layer; d) selectively anodizing the regions of N⁺⁽⁺⁾ semiconducting material, for forming porous silicon; and e) performing oxidation of the formed porous silicon regions.

Furthermore a process for manufacturing FIPOS structures based upon the selective anodization of one or more regions of N^ semiconducting material is also provided, for forming porous silicon inside Φ/N⁺⁽⁺VN^(":>-type structures for semiconductor integrated circuits, as well as based upon the subsequent oxidation of said porous silicon, characterized in that said regions of ^' ^ semiconducting material are manufactured by the above-mentioned process for forming one or more regions of N^ semiconducting material.

Advantageous features of the present invention are provided in the dependent claims thereof. The process according to the present invention is so as to allow the manufacturing of SOI structures (FIPOS structures in particular) wherein it is possible manufacturing thicknesses of the buried insulating silicon dioxide layer and of the silicon layer over the oxide different between them inside the same chip (thickness modulation). In this way, the integration of different devices inside the same chip is made much easier.

An additional advantage of the present invention is to form a hyperfme transition region between the Φ semiconducting material layer (and that is Sii or P^(_) or N^w) and the INP^"^ semiconducting material layer for the transformation of the latter into porous silicon.

The presence of a hyperfme transition region means that there is an abrupt variation in the dopant concentration between a N^"1"^-¹ buried layer and the Sii or P^(*} or N^H adjacent interface in the Φ N⁺⁽⁺⁾/N^(") structure.

The main advantage of the presence of this abrupt variation is that the selective anodization of N^ layer transformed into porous silicon without undesired changes of the Sii or P^(_) or N^ layer is made easier in this way.

By means of the present invention both the position of the buried insulating silicon dioxide layer and the thickness of this buried layer may be freely determined.

Application modes of the present invention for example provide manufacturing of CMOS integrated circuits wholly by SOI technology, or CMOS- type circuits the pMOS portion thereof is manufactured by SOI technology and the nMOS portion thereof is in bulk silicon and/or viceversa. BiCMOS (Bipolar/CMOS) structures showing CMOS portion manufactured by SOI technology and Bipolar portion in bulk silicon could also be provided.

An additional advantage provided by the possibility of modulating the buried oxide thickness is given by the possibility of integrating devices for different application modes in the same integrated circuit. By way of example, circuits can be mentioned wherein a thin oxide layer for the devices of the digital portion of the integrated circuit and a thick layer of buried oxide for the devices of the analogic portion of the integrated circuit are provided. This because the analogical part, should it require medium and/or high voltages, if placed over thin oxide thicknesses, can perforate the oxide layer when voltage peaks occur, with consequent destruction of the integrated circuit.

Other advantages, features and application modes will be evident from the following detailed description of the invention, provided by embodiments by way of example and not for limitative purposes. The figures of the enclosed drawings will be referred to, which in a schematic way illustrate the situation of the performed technological steps, to allow a greater comprehension of the inventive core of the present invention, wherein:

Figs. 1 to 9 show subsequent steps of the process according to the invention so as to obtain one or more regions of silicon dioxide (SiO ) underneath single- crystal silicon islands, in particular:

Fig. 1 shows a partial cross-sectional view of a single-crystal silicon wafer showing a N^(_) layer and a N⁺⁽⁺⁾ layer; Fig. 2 shows the wafer after the deposition of a protective mask and the opening thereof by means of photolitographic process;

Fig. 3 shows in particular a lST¹^ region obtained by exploiting the opening in the mask of the preceding figure;

Fig. 4 shows the structure of Fig. 3 after deposition of a protective mask and corresponding opening by means of photolitographic process;

Fig. 5 shows in particular a second N⁺⁽⁺⁾ region obtained by exploiting the opening in the mask of Fig. 4;

Fig. 6 shows a subsequent deposition of an epitaxial silicon layer; Fig. 7 A shows the wafer after a partial removal of the epitaxial layer; Fig. 7B shows the wafer of Fig. 7 A after a decrease in thickness of one of the silicon island;

Fig. 7C shows the wafer of Fig. 7 A wherein one of the ^⁽⁺⁾ areas is protected by a mask;

Fig. 8 A shows the structure of Fig. 7 A later obtained after anodization; Fig. 8B shows the structure of Fig. 7B later obtained after anodization;

Fig. 8C shows the wafer of Fig. 7C wherein only one of the N^ areas is transformed into porous silicon after anodization;

Fig. 9A shows the structure of Fig. 8A later obtained after oxidation and removal of the protective mask; Fig. 9B shows the structure of Fig. 8B later obtained after oxidation and removal of the protective mask;

Fig. 9C shows the structure of Fig. 8C later obtained after oxidation and removal of the protective mask;

Fig. 9D shows the structure of Fig. 9C with a protective mask for the oxidized layer and the surfaces of silicon islands;

Fig. 9E shows the structure of Fig. 9D later obtained after anodization of the previously protected N*⁽⁺⁾ area (see Figs. 7C and 8C);

Fig. 9F shows the structure of Fig. 9E after oxidation and removal of the masks; Fig. 10 shows the variation of porosity of porous silicon in terms of current density and kind of electrolyte chosen for a fixed dopant concentration; Fig 11 shows the variation of porosity of porous silicon in terms of current density and dopant concentration for a fixed electrolytic solution;

Figs. 12 A and 12B show voltage and current variation in terms of time during anodization process; Fig. 13 shows some of the features of the obtained oxide layer;

Fig. 14 shows a diagram of electrolytic cell utilized in the silicon anodization step;

Fig. 15A shows the doping profile variation in terms of a particular implantation; Fig. 15B shows the doping profile shown in Fig. 15A after an epitaxial growth at high temperature; and

Fig. 15B shows the doping profile shown in Fig. 15A after an epitaxial growth at low temperature.

By firstly referring to Fig. 1, a partial cross-sectional view of the structure to be utilized in the present invention is shown. The semiconducting substrate 101, N or

N^~-type, is chosen preferably with a resistivity between 4 and 400 Ohm-cm, whereas the region designated with 100 is of N⁺⁽⁺-⁾ material. The presence of the region 100 placed on the lower surface of the wafer is advantageous, since it aims at providing a good electrical contact during anodization step. In the figures 2 to 7 herebelow described, the operating steps apt to define the areas in which creating N⁺⁽⁺⁾ regions to be transformed into porous silicon and then into silicon dioxide (Si0₂) will be illustrated. According to circuit requirements, different time by time, the manufacturing of several oxide thicknesses, different between them, could be necessary. In the following figures an example of two regions with different thickness will be illustrated.

By referring to Fig. 2, the wafer of Fig. 1 is treated in order to manufacture a protective mask and by means of the photolitographic process the area is defined whereon a heavily doped ϊsT^ region is manufactured. This region does not result to be protected by the layer 103. By way of example and not for limitative purposes, the layer 103 can be a polymeric material such as the photoresist, should the heavily doped ^^"1"-* region be manufactured by the known technique of ion implantation. Alternatively, the layer 103 could be an oxide such as the silicon dioxide, should the heavily doped N⁺⁽⁺⁾ region be manufactured according to the known technique of diffusion. After this treatment the regions will show as in Fig. 3. In particular, a ^ layer 104 beneath the upper surface of the region 101 is formed. An exemplary and not limitative thickness of the layer 104 can be equal to 1.2 μm obtained by Antimony implantation with 60 keV energy with 250 μC/cm² and with a thermal treatment in dry oxygen ambient of 1220 °C for about 40 minutes.

The following Figs. 4 and 5 show the operating steps performed to manufacture in the substrate 101 a second N^ region with the thickness, for example, lower than that of the region 104 of Fig. 3.

By referring to Fig. 4, the substrate 101 is covered with a new photoresist layer 106, deposited on the upper surface thereof.

By means of photolitographic process an additional area is defined whereon the new N*^ region is manufactured. This area does not result to be protected by the layer 106. In this case too, by way of example and not for limitative purposes, the layer 106 can be a polymeric material such as the photoresist, should the heavily doped N⁺⁽⁺⁾ region be manufactured by the known technique of ion implantation. Alternatively, the layer 106 could be an oxide such as the silicon dioxide, should the heavily doped N⁺⁽⁺⁾ region be manufactured according to the known technique of diffusion.

After this treatment an additional N⁺⁽⁺⁾ layer 107 will be obtained, shown in Fig. 5, placed beneath the upper surface of the substrate 101 as well.

The kind of thicknesses and doping levels of ^ regions 104 and 107 is determined by the parameters utilized during ion implantation or diffusion step and by performed thermal treatment and therefore it can be controlled so as to predetermine, at time of planning, the thickness which is desired to be obtained.

By way of example, Fig. 15A shows a probable variation of doping profile, that is net doping (atoms/cm³, on y-axis) of the N⁺⁽⁺⁾ layer 104 or 107 in terms of depth inside the substrate 101 (μm, on x-axis).

The variation of Fig. 15A in particular has been obtained by an amorphization pre-implantation with silicon ions for obtaining an amorphous surface layer with a thickness of about 2500 Angstrom and by a double implantation of Antimony or

Arsenic atoms. By using Antimony the first implantation dose has been about 5 10¹² - 1 10¹³ atoms/cm² with 30keV energy, whereas the second implantation dose has been about 1 10¹³ -2 10¹³ atoms/cm² with 160 keV energy. By using Arsenic the first implantation dose is about 5 10¹² - 1 10¹³ atoms/cm² with 20keV energy, whereas the second implantation energy is about 1 10¹³ - 2 10¹³ atoms/cm² with 110 keV energy.

The layers 104 and 107 are the layers to be converted into porous silicon by means of anodization and the thicknesses thereof determine the thicknesses of final oxide layers. In the embodiment shown in Fig. 5, wherein regions with different thickness are namely present, it is preferable that the dopant surface concentrations differ no more by 40% between one region and the other, because in this way it will be possible to transform both regions of N⁺⁽⁺⁾ semiconducting material into porous silicon by a single anodization process (and not by a first anodization step for the region 104 and a second anodization step for the region 107) and subsequently transform both regions of porous silicon into silicon dioxide by a single oxidation step. In fact, later it will be emphasized how the porous silicon porosity depends on the dopant surface concentration, once electrolyte and current density utilized during the subsequent anodization process are fixed. Then, in order that both layers 104 and 107 may be transformed into porous silicon with the same process and with predetermined porosity in the 50%-60% range, it is preferable that these layers have a dopant surface concentration differing no more by above mentioned 40%.

The thickness of the layers 104 and 107 usually varies between 0.20 and 5.00 μm, whereas the surface concentration varies between 1 10¹⁸ and 4 10¹⁹ cm^"2.

By referring to Fig. 6, a Sii or P^(_) or N^H, lightly doped epitaxial layer 108 is shown, grown on the upper surface of the substrate 101 and therefore on the upper surface of the regions 104 and 107. This epitaxial layer 108 represents the layer wherein electronic devices will be manufactured and has a thickness usually varying between 0.05 and 5 μm.

This epitaxial layer is grown so as to perform an abrupt (also called hyperfme) transition between the heavily doped regions 104 and 107 and the epitaxial layer 108. This abrupt transition aims at making easier the complete transformation of the layers 104 and 107 into porous silicon, without altering the structure of the layer 108 over them. In fact, greater is the dopant concentration gradient between the Sii or P^H or N^(_:) material and the N⁺⁽⁺⁾ material, greater will be the possibility of obtaining a transformation of the N⁺⁽⁺⁾ layer into porous silicon without undesired consequences on the Sii or P^(_) or N^-type epitaxial layer 108.

The epitaxial layer 108 may be grown with any method for growing single- crystal silicon.

The main difficulty in performing an abrupt transition is represented by auto- diffusion, which must be limited as much as possible. The present invention, in a preferred embodiment thereof, utilizes an epitaxial growth process of the layer 108 at low temperature (lower than about 900°C, preferably 700-850°C or firstly by means of a deposition at about 600°C and then at higher temperature between about 700 and about 900°C). Fig. 15B shows the doping profile for an epitaxial layer grown at a 1 100°C temperature on a substrate having as initial doping profile the profile shown in Fig. 15 A. The Fig. 15C shows the doping profile for an epitaxial layer grown at low temperature (lower than 900°C) on a substrate having as initial doping profile the profile shown in Fig. 15 A.

In both figures net doping (atoms/cm³) is on y-axis whereas doping depth (with μm) is on x-axis. In particular, the negative values of doping depth show the grown epitaxial layer.

During the following process of conversion into porous silicon (anodization) of the N⁺⁽⁺⁾ layers inside the Φ/N⁺⁽⁺⁾ N^{') structure 108/104(107)/101, all the silicon having a concentration higher or equal to 10¹⁷ atoms/cm³ is converted into porous silicon.

From the comparative analysis between Figs. 15B and 15C it can then be noted how the slope at curve in the parabolic region thereof is greater in Fig. 15C rather than in Fig. 15B. By referring to Fig. 15B, it can be noted in particular that there is a transition equal to approx. 0.2 μm between the layer 104 (or 107) and the layer 108 wherein doping varies between 10¹⁷ and 10¹⁵ atoms/cm³. This transition has been designated with the dβ symbol in Fig. 15B. By referring to Fig. 15C instead, it can be noted that the transition is highly reduced, equal to approx. 0.05 μm. This transition has been designated with the dc symbol in Fig. 15C.

This reduced (hyperfme) transition is advantageous, since it denotes the presence of an abrupt transition, useful for improving the performance of subsequent anodization and oxidation operations.

Growing the epitaxial layer at a temperature of 600 °C can slow down the growing process as the growth rate of the epitaxial layer is low at this temperature.

This fact could be inconvenient in case of manufacturing layers 108 with high thickness, that is equal to 0.5 μm or more. Thicknesses with these sizes are sometimes necessary for manufacturing SOI devices.

A first possibility of overcoming this problem is given by the material choice. In fact, by utilizing dichlorosilane (SiH₂Cl₂) a growing rate of the epitaxial layer of about 0.5 nm/min. is obtained, whereas by using silane (SiH₄) this growth rate may be even of 10 nm/min.

A second possibility, instead, is given by performing an epitaxial growth at non-constant temperature. In particular, a first step will have to provide growing a thin layer (0.05 - 0.1 μm) at low temperature (about 600°C) according what has been so far described, whereas a second step will have to provide growing of a layer at a higher temperature (700-900°C). In this second step, although temperature is higher, the auto-diffusion will be greatly reduced thanks to the presence of the thin layer previously grown at the temperature of about 600°C. The growth at low temperature can be performed for example by UHCVD (Ultra-High Vacuum Chemical Vapour Deposition), that is by means of a high vacuum chemical vapour deposition. A generic example of using this method is described in the article by B. S. Meyeron "Low Temperature Silicon Epitaxy by Ultrahigh Vacuum Chemical Vapor Deposition" published on Applied Physics

Letter, V.48 (12), 1986, p.797-799.

After growing the layer 108, a protective layer, preferably silicon nitride (Si₃N₄) is deposited over it. The deposition can be performed by LPCVD (Low Pressure Chemical Vapour Deposition), that is low pressure chemical vapour deposition.

By means of lithographic processes, the desired island structure is obtained, by removing part of the layer 108.

A process which can be advantageously utilized is the chemical etching, anisotropic plasma etching in particular, as it allows obtaining islands with vertical side walls. This is advantageous, since the presence of islands with vertical side walls, i.e. substantially parallelepiped-shaped islands, is preferred to the presence of islands with oblique side walls, i.e. substantially frustopyramid-shaped islands. In the first case, in fact, islands occupy a well-defined space, and therefore distances between islands could be defined by a lithographic process. On the contrary, in case of frustopyramid-shaped islands they will have to be well spaced between them so as to prevent any dangerous mutual contact.

This protective layer aims at protecting the epitaxial layer 108 against possible effects of subsequent anodization and oxidation processes.

After the photoresist removal and a chemical cleaning process of the substrate, the structure as represented in Fig. 7A is obtained, wherein the protective layer over the epitaxial layer 108 has been designated with 109. At this point the wafer is ready for anodizing the layers 104 and 107 which will be converted into porous silicon.

The anodization process is performed in an electrochemical cell. An exemplary embodiment of this electrochemical cell is represented in Fig. 14. In this figure the whole wafer is schematically designated with numeral 402 and is wet by an electrolytic solution 403. This solution is preferably hydrofluoric-acid based (HF), with a volume concentration preferably between 0.1% and 50%, deionized water and an additive. This additive can be for example an alcohol, such as ethanol (C₂H₅OH), or isopropyl alcohol (iso- C₃H7OH).

The wafer acts as anode by a contact 400. For the cathode 401 a non-reagent in the process conducting material, such as platinum, tungsten or nickel, is utilized. On the basis of researches carried out by inventors, a dependence of porous silicon porosity on current density for different kind of electrolyte and different doping levels of silicon to be anodized has been disclosed and determined.

In laboratory tests carried out by inventors, silicon has been anodized with different electrolytic solutions with different current density. The porosity of the several samples has been obtained by measuring weight before and after anodization, by measuring the thickness of the obtained porous silicon and knowing the surface of the region transformed into porous silicon, in particular according to the following equations:

P% = (Equation 1) and

PP_S = Ps, ^~ '"_s . '" (Equation 2)

wherein:

P% is the porosity of porous silicon; p_Ps is the density of porous silicon; ps, is the density of single-crystal silicon (known); P,_n is the initial weight of the sample; P_fi_n is the final weight of the sample after anodization (measured); S is the surface of the region transformed into porous silicon (known); and d is the thickness of the porous silicon layer (measured).

Fig. 10 shows the variation of porosity of porous silicon (in %) in terms of current density (mA/cm ) for three different electrolytic solutions and for a fixed value of the dopant concentration in wafer (4 10¹⁸ atoms/cm³).

Fig. 11 shows furthermore the variation of porosity of porous silicon (in %) in terms of current density (mA/cm²) for four different silicon doping levels, shown in the legend of the figure itself. All the four doping levels in the figure refer to a fixed electrolytic solution, composed (in volume concentration) by 25% by HF (by 50%) and by 75% by ethanol (C₂H₅OH).

The anodization process will be here described according to an advantageous embodiment thereof, which provides two steps, a constant current step and a constant voltage step. However, it is to be meant that constant current only or constant voltage only anodization processes may be also provided. A first step is performed with constant current and aims at determining the working voltage to be fixed in the following step which will be performed with constant potential. The choice of the initial value of constant current depends on the silicon porosity percentage which is wanted to be obtained. The value of current density will be preferably determined by diagrams such as those shown in Figs. 10 and 1 1.

For example, by supposing to have a substrate with a dopant surface concentration equal to 4 10 atoms/cm and if a porosity of about 58% is wanted to be obtained, from Fig. 1 1 curve 305 a pair of probable values of current density (about 2 mA/cm and about 160 mA/cm ) to be applied in this constant current step will be determined.

In case there are several values of current density to work with to obtain a determined percentage of porosity of porous silicon, as in the above-mentioned example, a first preferable choice is to utilize the lowest current density, in order to obtain a better homogeneity of porous silicon. In fact, experiments have disclosed that the porous layer is more homogeneous when a lower current density is utilized during anodization. This is due to the fact that, being reaction kinetics slower under these conditions, pores are uniformly formed over the whole substrate. However, should conditions require, a likewise preferable choice can be the utilization of highest current density, in order to shorten the anodization process time.

Then, by multiplying the value of the so-determined current density times the heavily doped surface exposed to electrolytic solution, the current value to be applied in this first step will be obtained.

An alternative process to determine current density makes use of diagrams like those shown in Fig. 10, which represent the porosity dependency on the concentration of the electrolytic solution and current density for a fixed value of dopant concentration in the N⁺⁽⁺⁾ silicon layer exposed to the solution.

For a very good result in the anodization and oxidation steps described hereinafter, the porosity of porous silicon will have to be between 50% and 60%. The oxidation step subsequent to the anodization step in fact takes place with an increase in volume of porous silicon columnar structures. It has been noted that that if porosity is greater than 60% the final oxide is porous and little massive. Viceversa, if porosity is lower than 50%, the subsequent transformation into oxide involves formation of mechanical stress worsening the quality of the oxide itself and consequently of the wafer.

The following Figs. 12A and 12B represent exemplary variation in time of the anodization inventive process for some current values and for 4-inch wafer. In particular, Fig. 12A represents three different voltage variation (V on y-axis) in terms of time (minutes on x-axis), whereas Fig. 12B represents corresponding current variation (mA on y-axis) in terms of time (minutes on x-axis). The three different pair of variation have been designated with pair of Greek letters ( ), (β) and (γ), respectively.

By way of example curves (β) will be followed and initial current to be utilized in the first step of the anodization process (step designated with I in the Figures) will be supposed to be equal to the value designated in Fig. 12B with numeral 311, that is 300 mA. By referring to curve (β) of Fig. 12 A, the potential variation is designated with 309. c when the anodization process is functioning with constant current. It can be noted that in time tl curve 309. c reaches a minimum value.

In this time tl the second step of the anodization process, that is the constant voltage step, designated with II in the Figures, will start. The constant voltage value will be equal to the minimum value of curve 309. c of Fig. 12A, as it can be noted from part 309. a of curve (β) of Fig. 12A. During this second step, the current variation in terms of time will be decreasing-type, as shown by part 309.b of curve (β) of Fig. 12B.

The second step of the anodization process will end as soon as the variation of curve (β) of Fig. 12B will stabilize about a minimum value. By referring to Figs.

12A and 12B, this minimum value is reached in time t2. In this time the anodization process will end, since all the N*" silicon of regions 104 and 107 will have been transformed into porous silicon.

Therefore, in step I the current is held constant at a determined value, for example a value such as to form porous silicon with a porosity between 50% and

60%. This step allows identifying the potential value to be applied in the following step. In this first step, according to the electrolyte composition and the dopant concentration of the N⁺⁽⁺⁾ silicon layer exposed to the solution, the current density could be chosen in the range between 0.5 and 300 mA/cm² (see Figs. 10 and 11). In step II voltage is held constant at the above-determined value and current decreases.

The value of the voltage determined in step I and subsequently applied to step

II depends on potential fall at the ends of electrodes of electrochemical cell which in turn depends on several factors such as kind of electrochemical solution, wafer resistivity, electrode sizes, etc. An indicative range may include values between 1 and 100 V. When current stabilizes (step III) all the N⁺⁽⁺⁾ silicon will have been converted into porous silicon and the anodization process will end.

Determining the time of switching time tl can take place in several ways. Usually, voltage is read at regular intervals, by making then easy determining the time in which it increases. The switching between step I and step II can take then place when voltage has increased by 2%, preferably no more than 5%, compared to the minimum thereof. A different mode consists in determining the voltage derivative and switching as soon this derivative changes in sign.

Determining time t2 (and therefore the end of the constant voltage step) takes place as soon as current stops varying inside a prefixed percentage, 5-10% for example.

The process can be clearly automatized by monitoring voltage and current values with specific sensors and with a circuitry if necessary connected to a computer for switching between the two operating modes (constant current/constant voltage). It is to be noted that the so far described two-step process singularity allows an easy determination of the fact that all the silicon inside the regions 104, 107 has transformed into porous silicon. The voltage applied during the constant voltage step is so as not to allow the transformation of the less doped layer. Furthermore, since current density detects the transformation reaction of silicon into porous silicon, as above illustrated, when it reaches non-significant values it signals in this way the end of the reaction and therefore of the transformation of silicon into porous silicon.

By now referring to Fig. 8, this shows the wafer structure starting from time t2. The regions 104 and 107 referred to in the preceding Figs. 5, 6 and 7A are transformed into regions 110 of porous silicon with a prefixed value of porosity. The oxidation process of the layer 1 10 will start now. This process is preferably performed in three steps.

A first step provides the stabilization of the porous silicon structure. This stabilization is performed at low temperature (about 300°C) for about 1 hour, in dry oxygen ambient; a second step provides the porous silicon oxidation at about 850°C and about 20 atmospheres in water vapour ambient; and a third steps aims at increasing the oxidized porous silicon density, and is performed in dry oxygen ambient at about 1200 °C.

The structure of Fig. 9A is so obtained, comprising the oxide layers 111, correspondent to the preceding ¹^ layers 104 and 107. A SOI structure without mechanical stress is so formed, wherein the porous silicon underneath the silicon islands is fully oxidized. The obtained insulating layer has a resistivity of 10¹⁶ Ohm-cm, a fixed charge density of about 1 10 cm^"". The silicon island above the insulating layer has preferably a maximum width of 40 μm and a defect density lower than 100 cm^"2.

A thin oxide layer, designated with 1 12, will have been formed on the side walls of the silicon islands 108. The oxidation of the surface of the layer 108 is reduced thanks to the mask 109, which is not represented in Fig. 9A.

The table in Fig. 13 shows, by way of example, some of the obtained buried oxide features. In this table ds,o designates the oxide thickness, C_ox designates the oxide capacity, N_sub designates the dopant concentration at the interface between the regions 111 and 101 , ε_r designates the dielectric constant of the layer 11 1 and, at last, p designates the resistivity of the layer 1 11.

A further embodiment of the present invention may provide that once silicon islands 108 shown in Fig. 7 A are manufactured, one of them could be decreased in thickness. Figs. 7B, 8B and 9B are respectively equivalent to Figs. 7A, 8A and 9A wherein the thickness variation Δd is null.

By now referring to Fig. 6 a protective layer is deposited on the layer 108 and by means of litographic processes a desired island structure is obtained, by removing part of the layer 108.

A process which can be advantageously utilized is the chemical etching, anisotropic plasma etching in particular, as it allows obtaining islands with vertical sidewalls.

The protective layer is then removed and silicon nitride (Si₃N₄) is deposited and by means of photolitographic process a window is opened by removing the silicon nitride over one of the islands which is wanted to be decreased in thickness. By way of example and not for limitative purposes part of the island left uncovered is oxidized by means of the known thermal treatment. The grown oxide is then removed by obtaining the new island 208 (Fig. 7B) with different thickness compared to the island 108. Once the Si₃N₄ protective layer utilized in the oxidation step is removed and the wafer is cleaned, another protective layer is deposited again which by way of example and not for limitative purposes can be Si₃N₄ and then by means of litographic and removal processes the structure of Fig. 7B is obtained wherein there are islands with different thicknesses 208 and 108 and the Si₃N₄ protective mask designated with 109.

The following Figs. 8B and 9B show the same technological steps performed in order to obtain the situation shown in Figs. 8A and 9A except for having islands with Δd different from zero. The operating steps required to transform both N⁺⁽⁺⁾ regions into buried oxidized layers will be hereinafter described. By way of example and not for limitative purposes the case will be referred to wherein the surface dopant concentration differ more than 40% between the two regions, so as to require then two anodization steps (one for the region 104 and one for the region 107) and two oxidation steps (one for the region 104 and one for the region 107).

The process is such as to apply the anodization process and then the oxidation process to the region 104, and subsequently the anodization process and then the oxidation process to the region 107. Alternatively, it will be possible to proceed firstly with the region 107 and then with the region 104.

For the description of this process the Figs. 7C, 8C, 9C, 9D, 9E and 9F will be referred to.

Once the island structure of Fig. 7A has been manufactured, the wafer is cleaned (the layer 109 is then removed) and a mask 509 is placed - preferably made of silicon nitride - so as to protect the N ^"^ semiconducting material areas which are not involved in the subsequent anodization step. In Fig. 7C it can be noted to this purpose that the mask 509 wholly protects the region 104 and not the region 107, since the latter will undergo the anodization process in the subsequent step.

Fig. 8C shows the situation subsequent to the anodization step, wherein the layer 107 of Fig. 7C has been transformed into a layer 110 of porous silicon.

Fig. 9C shows the situation subsequent to the following oxidation and mask removal step. In this Fig. it can be noted that the layer 110 of Fig. 8C has been transformed into a layer 111 of silicon oxide. In this Fig. it can also be noted that the layer 104 has remained unchanged, having been protected by the mask 509 in the preceding anodization process.

At this point a new mask 509 is deposited, this time so as to wholly protect the region 111 and not the region 104, since the latter now will have to undergo the subsequent anodization process. The structure illustrated in Fig. 9D is therefore obtained. Figs. 9E and 9F show the situation after the anodization (Fig. 9E) and oxidation and mask 509 removal (Fig. 9F) step.

From what has been so far illustrated, it can be noted that, when the anodization step and the oxidation step are performed region by region, the preferred mode is the one which provides performing firstly the anodizaton step for the first region, then the oxidation step for the first region, then the anodization step for the second region, then the oxidation step for the second region and so on. It is to be meant that the example of the two regions 104, 107 has been shown for clarifying purposes. In practice, several regions similar to regions 104 and 107 so far described are obviously present. In this case a single anodization step will allow the anodization of all those regions for which the surface dopant concentration is identical or similar. By supposing then to have the case wherein there is a first group of regions showing a dopant concentration distributed around a first value and a second group of regions showing a dopant concentration distributed around a second value, the whole steps will be four, and that is: anodization of the first group of regions, oxidation of the first group of regions, anodization of the second group of regions and oxidation of the second group of regions.

The selective anodization step of the N⁺⁽⁺⁾ semiconducting material regions will be then performed group by group, as well as the oxidation step of the formed porous silicon regions. Preferably, the sequence in time of the anodization and oxidation steps will be so as to provide performing of the anodization step for a first group, performing of the oxidation step for this first group, performing the anodization step for a second group, performing the oxidation step for this second group and so on.

The present invention has been so far described according to the embodiments thereof illustrated by way of example and not for limitative purposes. It is to be meant that other embodiments may be provided, all comprised within the scope of the same invention as defined in the annexed claims.

Claims

CLALMS 1. A process for forming insulating layers, of predetermined thickness, in semiconductor wafer for manufacturing integrated circuits by means of Φ/N⁺⁽⁺⁾/N^(")- type structures, characterized in that it comprises the following steps of: a) forming one or more regions of N⁺⁽⁺⁾ semiconducting material inside a N^("} semiconducting material substrate; b) growing a Φ-type epitaxial layer on said substrate of N^(_) semiconducting material, said growing being performed so as to obtain a predetermined thickness of the Φ-type epitaxial layer; c) defining an island structure by removing part of said Φ-type epitaxial layer; d) selectively anodizing the N⁺⁽⁺⁾ semiconducting material regions for forming porous silicon; and e) performing oxidation of the formed porous silicon regions.

2. A process according to claim 1, characterized in that said step a) is performed by ion implantation.

3. A process according to claim 1, characterized in that said step a) is performed by diffusion.

4. A process according to any of the preceding claims, characterized in that said one or more N⁺⁽⁺⁾ semiconducting material regions formed by step a) are a plurality of N⁺⁽⁺⁾ semiconducting material regions.

5. A process according to claim 4, characterized in that: the step d) of selectively anodizing the N⁺⁽⁺⁾ semiconducting material regions is performed simultaneously on all said ISP^"1"' semiconducting material regions; and the step e) of performing oxidation of formed porous silicon is performed simultaneously on all said formed porous silicon regions.

6. A process according to claim 4, wherein said plurality of N⁺⁽⁺⁾ semiconducting material regions is made of several groups of N⁺⁽⁺⁾ semiconducting material regions, each group of regions showing a surface dopant concentration distributed around a certain value, characterized in that: the step d) of selectively anodizing the N⁺⁽⁺⁾ semiconducting material regions is performed group by group; and the step e) of performing oxidation of formed porous silicon is performed group by group.

7. A process according to claim 6, characterized in that the sequence in time of steps d) and e) is so as to provide performing step d) for a first group, performing step e) for said first group, performing step d) for a second group, performing step e) for said second group and so on.

8. A process according to any of the preceding claims, characterized in that said Φ-type epitaxial layer (108) is grown at a temperature lower than about 900°C.

9. A process according to claim 8, characterized in that the growing of said Φ-type epitaxial layer (108) comprises a first growing step performed at a temperature of about 600°C and a second growing step performed at a temperature in the range of about 700 °C and about 900 °C.

10. A process according to claim 8 or 9, characterized in that said temperature lower than about 900°C is in the range of about 700°C and about 850°C.

11. A process according to any of the preceding claims, characterized in that said step d) of selective anodization comprises the operations of: dl) performing a first step of constant current anodization, by determining the value of a working voltage during said constant current anodization; and d2) performing a second step of constant voltage anodization, the value of said constant voltage being equal to the working voltage value determined in the constant current anodization step.

12. A process according to claim 11, characterized in that the value of said constant current of the first constant current anodization step is obtained from a working current density value determined on the basis of a desired porosity percentage of porous silicon.

13. A process according to claim 11 or claim 12, characterized in that said desired porosity percentage of porous silicon is in the range of 50%-60%.

14. A process of selective anodization according to claim 12 or claim 13 if depending from claim 12, characterized in that whenever the working curcent values determined based upon said desired porosity percentage of porous silicon are more than one, the current value utilized in said constant current anodization step is obtained starting from the smallest of said working current density values.

15. A process of selective anodization according to claim 12 or claim 13 if depending from claim 12, characterized in that whenever the working current values determined based upon said desired porosity percentage of porous silicon are more than one, the current value utilized in said constant current anodization step is obtained starting from the biggest of said working current density values.

16. A process according any of the preceding claims 11 to 15, characterized in that said working voltage determined in said constant current anodization step is equal to the minimum value shown by the anodization voltage during said constant current anodization step.

17. A process for manufacturing FIPOS structures based upon the selective anodization of one or more regions of N⁺⁽⁺⁾ semiconducting material, for forming porous silicon inside Φ/N^ N^-type structures for semiconductor integrated circuits, as well as based upon the subsequent oxidation of said porous silicon, characterized in that said Φ/N⁺⁽⁺⁾/N^(")-type regions are manufactured by a process according to any of the claims 1 to 10.

18. A process for manufacturing F POS structures according to claim 17, characterized in that said selective anodization is performed by the process according to any of the claims 11 to 16.

19. A process for manufacturing FIPOS structures according to any of the claims 17 or 18, characterized in that said porous silicon oxidation step comprises the steps of: stabilizing said porous silicon at a temperature of about 300 °C for about one hour, in dry oxygen ambient; oxidizing said porous silicon at about 850°C and about 20 atmospheres in water vapour; and increasing the density of the porous silicon oxidized in dry oxygen ambient at about 1200°C.

20. A FLPOS structure obtained by means of the process according to any of the claims 17 to 19.