WO2001011538A3 - Discrete computer system - Google Patents

Discrete computer system Download PDF

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Publication number
WO2001011538A3
WO2001011538A3 PCT/US2000/040580 US0040580W WO0111538A3 WO 2001011538 A3 WO2001011538 A3 WO 2001011538A3 US 0040580 W US0040580 W US 0040580W WO 0111538 A3 WO0111538 A3 WO 0111538A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
level
mit
central processing
processing unit
Prior art date
Application number
PCT/US2000/040580
Other languages
French (fr)
Other versions
WO2001011538A2 (en
Inventor
Preeth Kumar Patil
Original Assignee
Preeth Kumar Patil
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Preeth Kumar Patil filed Critical Preeth Kumar Patil
Priority to AU77572/00A priority Critical patent/AU7757200A/en
Publication of WO2001011538A2 publication Critical patent/WO2001011538A2/en
Publication of WO2001011538A3 publication Critical patent/WO2001011538A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM

Abstract

A multi-level discrete computer system (100) comprised of a central processing unit, CPU, (105) for processing multi-level discrete signals (mits), memory means (110) for storing multi-level mits of data, input means (115) for receiving mit data from external devices and forwarding said mit data to said central processing unit, output means (120) for receiving mit data from said central processing unit and forwarding said mit data to external devices, and bus lines carrying mit data for operatively connecting said central processing unit with said memory means, input means, and output means. The CPU includes an arithmetic logic unit (ALU) including logic gates, a register unit (150), and a control unit (155) for manipulating mits of data. The system also includes a level converter for converting mit data signals of a first base level to mit data signals of a second base level.
PCT/US2000/040580 1999-08-09 2000-08-07 Discrete computer system WO2001011538A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU77572/00A AU7757200A (en) 1999-08-09 2000-08-07 Discrete computer system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US14785799P 1999-08-09 1999-08-09
US60/147,857 1999-08-09
US50434500A 2000-02-14 2000-02-14
US09/504,345 2000-02-14

Publications (2)

Publication Number Publication Date
WO2001011538A2 WO2001011538A2 (en) 2001-02-15
WO2001011538A3 true WO2001011538A3 (en) 2001-05-25

Family

ID=26845285

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/040580 WO2001011538A2 (en) 1999-08-09 2000-08-07 Discrete computer system

Country Status (2)

Country Link
AU (1) AU7757200A (en)
WO (1) WO2001011538A2 (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4528641A (en) * 1982-11-16 1985-07-09 The United States Of America As Represented By The Secretary Of The Air Force Variable radix processor
US4620188A (en) * 1981-08-17 1986-10-28 Development Finance Corporation Of New Zealand Multi-level logic circuit
US4914614A (en) * 1986-03-04 1990-04-03 Omron Tateisi Electronics Co. Multivalued ALU
US5280440A (en) * 1991-10-09 1994-01-18 Yukichi Sugimura Parallel adding circuit using 3×3 matrix of ± quinary number representation
US5289399A (en) * 1991-12-06 1994-02-22 Sharp Kabushiki Kaisha Multiplier for processing multi-valued data
US5467298A (en) * 1992-11-26 1995-11-14 Sharp Kabushiki Kaisha Multivalued adder having capability of sharing plural multivalued signals
US5469163A (en) * 1993-05-24 1995-11-21 Texas Instruments Incorporated Multiple resonant tunneling circuits for positive digit range-4 base-2 to binary conversion
US5524088A (en) * 1993-06-30 1996-06-04 Sharp Kabushiki Kaisha Multi-functional operating circuit providing capability of freely combining operating functions
US5768476A (en) * 1993-08-13 1998-06-16 Kokusai Denshin Denwa Co., Ltd. Parallel multi-value neural networks

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4620188A (en) * 1981-08-17 1986-10-28 Development Finance Corporation Of New Zealand Multi-level logic circuit
US4528641A (en) * 1982-11-16 1985-07-09 The United States Of America As Represented By The Secretary Of The Air Force Variable radix processor
US4914614A (en) * 1986-03-04 1990-04-03 Omron Tateisi Electronics Co. Multivalued ALU
US5280440A (en) * 1991-10-09 1994-01-18 Yukichi Sugimura Parallel adding circuit using 3×3 matrix of ± quinary number representation
US5289399A (en) * 1991-12-06 1994-02-22 Sharp Kabushiki Kaisha Multiplier for processing multi-valued data
US5467298A (en) * 1992-11-26 1995-11-14 Sharp Kabushiki Kaisha Multivalued adder having capability of sharing plural multivalued signals
US5469163A (en) * 1993-05-24 1995-11-21 Texas Instruments Incorporated Multiple resonant tunneling circuits for positive digit range-4 base-2 to binary conversion
US5524088A (en) * 1993-06-30 1996-06-04 Sharp Kabushiki Kaisha Multi-functional operating circuit providing capability of freely combining operating functions
US5768476A (en) * 1993-08-13 1998-06-16 Kokusai Denshin Denwa Co., Ltd. Parallel multi-value neural networks

Also Published As

Publication number Publication date
WO2001011538A2 (en) 2001-02-15
AU7757200A (en) 2001-03-05

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