WO2001013562A3 - A high speed burst-mode digital demodulator architecture - Google Patents
A high speed burst-mode digital demodulator architecture Download PDFInfo
- Publication number
- WO2001013562A3 WO2001013562A3 PCT/US2000/017873 US0017873W WO0113562A3 WO 2001013562 A3 WO2001013562 A3 WO 2001013562A3 US 0017873 W US0017873 W US 0017873W WO 0113562 A3 WO0113562 A3 WO 0113562A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- demodulator
- rate
- high speed
- digital demodulator
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/22—Repeaters for converting two wires to four wires; Repeaters for converting single current to double current
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
Abstract
A unique demodulator device structure is disclosed which includes methods for enhancing the reliability of processing digital data at high speeds, while in some cases reducing the amount of hardware required for such structures. Parallel data paths within several common functions of the overall demodulator design allow for reducing the rate at which data is processed within each such data path (e.g., Fig. 3, paths 0, 1, 2 and 3) to a rate lower than that at which the data was received. Subsequently, the data may be passed on at the original received data rate or processing may be completed at a lower rate. The reduction in hardware typically results in reductions in mass, size, and power for the final demodulator while simultaneously allowing the demodulator to work at speeds not otherwise possible.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US37371199A | 1999-08-13 | 1999-08-13 | |
US09/373,711 | 1999-08-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001013562A2 WO2001013562A2 (en) | 2001-02-22 |
WO2001013562A3 true WO2001013562A3 (en) | 2002-01-10 |
Family
ID=23473543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/017873 WO2001013562A2 (en) | 1999-08-13 | 2000-08-01 | A high speed burst-mode digital demodulator architecture |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2001013562A2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
US9395953B2 (en) | 2006-12-05 | 2016-07-19 | Altera Corporation | Large multiplier for programmable logic device |
US9600278B1 (en) | 2011-05-09 | 2017-03-21 | Altera Corporation | Programmable device using fixed and configurable logic to implement recursive trees |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6556044B2 (en) * | 2001-09-18 | 2003-04-29 | Altera Corporation | Programmable logic device including multipliers and configurations thereof to reduce resource utilization |
US8386553B1 (en) | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
US8244789B1 (en) | 2008-03-14 | 2012-08-14 | Altera Corporation | Normalization of floating point operations in a programmable integrated circuit device |
US8886696B1 (en) | 2009-03-03 | 2014-11-11 | Altera Corporation | Digital signal processing circuitry with redundancy and ability to support larger multipliers |
US9053045B1 (en) | 2011-09-16 | 2015-06-09 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US9379687B1 (en) | 2014-01-14 | 2016-06-28 | Altera Corporation | Pipelined systolic finite impulse response filter |
US9684488B2 (en) | 2015-03-26 | 2017-06-20 | Altera Corporation | Combined adder and pre-adder for high-radix multiplier circuit |
US10942706B2 (en) | 2017-05-05 | 2021-03-09 | Intel Corporation | Implementation of floating-point trigonometric functions in an integrated circuit device |
CN114338304B (en) * | 2021-12-29 | 2023-08-15 | 中国工程物理研究院电子工程研究所 | Parallel baseband demodulator system for high-speed communication |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5454009A (en) * | 1994-01-13 | 1995-09-26 | Scientific-Atlanta, Inc. | Method and apparatus for providing energy dispersal using frequency diversity in a satellite communications system |
US5459524A (en) * | 1991-11-18 | 1995-10-17 | Cooper; J. Carl | Phase modulation demodulator apparatus and method |
US5867400A (en) * | 1995-05-17 | 1999-02-02 | International Business Machines Corporation | Application specific processor and design method for same |
-
2000
- 2000-08-01 WO PCT/US2000/017873 patent/WO2001013562A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459524A (en) * | 1991-11-18 | 1995-10-17 | Cooper; J. Carl | Phase modulation demodulator apparatus and method |
US5454009A (en) * | 1994-01-13 | 1995-09-26 | Scientific-Atlanta, Inc. | Method and apparatus for providing energy dispersal using frequency diversity in a satellite communications system |
US5867400A (en) * | 1995-05-17 | 1999-02-02 | International Business Machines Corporation | Application specific processor and design method for same |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9395953B2 (en) | 2006-12-05 | 2016-07-19 | Altera Corporation | Large multiplier for programmable logic device |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US9600278B1 (en) | 2011-05-09 | 2017-03-21 | Altera Corporation | Programmable device using fixed and configurable logic to implement recursive trees |
US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
Also Published As
Publication number | Publication date |
---|---|
WO2001013562A2 (en) | 2001-02-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2001013562A3 (en) | A high speed burst-mode digital demodulator architecture | |
WO2002068981A3 (en) | Memory reduction method for a dsp-based gps processor | |
CA2291696A1 (en) | Channel encoding device and method for communication system | |
MY105323A (en) | Communications interface adapter. | |
WO2000004484A3 (en) | Wide instruction word graphics processor | |
WO2002093828A3 (en) | Distributed packet processing system with internal load distribution | |
EP0591008A3 (en) | Data output buffers in semiconductor memory devices. | |
EP1168120A3 (en) | Method and device for serial data transmission between a position measuring system and a processing unit | |
AU2001296002A1 (en) | Image processing method for realizing quick bump mapping, image processing device, computer program, and semiconductor device | |
ATE437528T1 (en) | VERTICAL ELEVATION AND SCALING COMBINING POLYPHASE FILTER IN A PIXEL PROCESSING APPARATUS | |
CA2056356A1 (en) | Interruption handling system | |
JPS53108254A (en) | Information processor | |
WO2000000893A3 (en) | Memory arrangement based on rate conversion | |
EP0962851A3 (en) | Timing circuit utilizing a clock tree as a delay device | |
WO2001025886A3 (en) | Power management method for a computer system having a hub interface architecture | |
EP0338077A4 (en) | High-speed input/output module and plc apparatus | |
EP0336685A3 (en) | Impulse noise detection and supression | |
WO2002039450A3 (en) | Method for switching from scanning the content to playing the content | |
CA2303024A1 (en) | Apparatus and method for protocol application data frame operation requests interfacing with an input/output device | |
CA2085944A1 (en) | Method of processing image data | |
CA2360552A1 (en) | Method and apparatus for digital signal processing | |
WO2004112341A3 (en) | Method and device for processing real-time data | |
TW335542B (en) | A frame for fabrication of electronic components, a fabrication method of such components and components obtained thereby | |
EP1100194A3 (en) | Surface acoustic wave filter | |
WO2003093953A3 (en) | Audio-visual content editing peripheral and system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): CA |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): CA |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
122 | Ep: pct application non-entry in european phase |