WO2001022482A1 - Method of producing relaxed silicon germanium layers - Google Patents

Method of producing relaxed silicon germanium layers Download PDF

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Publication number
WO2001022482A1
WO2001022482A1 PCT/US2000/040938 US0040938W WO0122482A1 WO 2001022482 A1 WO2001022482 A1 WO 2001022482A1 US 0040938 W US0040938 W US 0040938W WO 0122482 A1 WO0122482 A1 WO 0122482A1
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Prior art keywords
germanium
layer
source gas
gas
component
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PCT/US2000/040938
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French (fr)
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WO2001022482A9 (en
Inventor
Eugene A. Fitzgerald
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Amberwave Systems Corporation
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Priority to JP2001525758A priority Critical patent/JP2003517726A/en
Priority to EP00974128A priority patent/EP1214735A1/en
Publication of WO2001022482A1 publication Critical patent/WO2001022482A1/en
Publication of WO2001022482A9 publication Critical patent/WO2001022482A9/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

Definitions

  • the invention relates to the field of relaxed SiGe layers.
  • CVD is, under most conditions and products, the most economical method of depositing thin layers of crystalline semiconductors.
  • High thin-film growth rates are essential in producing economical relaxed SiGe materials on Si substrates, since the SiGe layers are relatively thick.
  • the highest growth rates known to date, which have been deposited in non-commercial equipment, have been achieved with CVD, with a maximum growth rate of about 6 micrometers per hour.
  • CVD deposition equipment can become too coated with thin film deposit in areas other than the substrate area. If this deposition is too great, it may prevent a large number of consecutive wafer deposition processes, leading to greater cost.
  • An additional problem is that in attempting to deposit films at high growth rates, gas-phase nucleation can occur, in which particles of SiGe, Si, or Ge form in the gas stream and subsequently deposit on the wafer surface.
  • FIG. 1 is a graph showing the growth rate of epitaxial silicon as a function of growth temperature for a variety of Si source gases;
  • FIG. 2 is a graph of the threading dislocation density at the surface of a relaxed
  • FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si,. x Ge x (0 ⁇ x ⁇ l) and Si 07 Ge 03 , respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
  • FIG. 1 is a graph showing the growth rate of silicon versus temperature for various source gases. Two distinct growth regimes are evident. For low temperatures, the growth rate has an exponential dependence on temperature, indicating that the growth is reaction rate or kinetically limited. For high temperatures, the growth rate has a weak dependence on temperature, indicating that the growth is mass transport or diffusion limited. Epitaxial layers are formed in the mass transport limited regime to minimize the effects of temperature variations during growth.
  • germane-chlorine-based gas used to increase the decomposition temperature.
  • chlorogermanes can be used to extend growth temperatures to more than 200°C over germane growth temperatures without increasing gas phase nucleation. In this way, the decomposition temperatures of the gases can be optimally chosen such that very high growth rates can be achieved at high temperatures.
  • the most readily available germanium-chlorine source gas is germanium tetrachloride, (GeCl 4 ). This gas, unlike germane, can be used at growth temperatures in excess of 800°C to grow thick, relaxed SiGe layers without excessive equipment coating and particle formation. It can be combined with any of the source gases for silicon, such as silane, dichlorosilane, trichlorosilane, and silicon tetrachloride to form high quality SiGe layers.
  • FIG. 2 is a graph showing experimental data of dislocation density versus growth temperature for SiGe graded layers.
  • SiGe relaxed buffers with a 30% Ge final composition cannot be grown much above 800°C without experiencing severe gas phase nucleation.
  • FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si !.x Ge x (0 ⁇ x ⁇ 1) and Si 07 Ge 03 , respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
  • the structures include a monocrystalline silicon substrate 300, a SiGe graded buffer layer 302, and a uniform concentration SiGe cap layer 304, 306.
  • the SiGe buffer layer 302 is a series of SiGe layers with increasing Ge concentration, usually with a gradient of less than 25% Ge per micron. By increasing the Ge concentration gradually, the strain due to the lattice mismatch between Si and Ge is relieved and the threading dislocation density is minimized.
  • the cap layers are high quality
  • SiGe layer with uniform Ge concentration that can be used as a platform for device fabrication.
  • FIG. 3 A shows a generic structure where the cap layer 304 Ge concentration can vary from 0 ⁇ x ⁇ l.
  • FIG. 3B shows a structure where the cap layer 306 is Si 07 Ge 03 .

Abstract

A method for making a semiconductor material, and subsequent structure, including providing a monocrystalline silicon substrate; epitaxially growing, using a source gas of GexHyClz for the germanium component, on the silicon substrate at a temperature in excess of 850 °C a graded Si1-xGex layer with increasing germanium concentration at a gradient of less than 25 % Ge per micron to a final composition in the range of 0.1<=x<=1; and epitaxially growing a layer of semiconductor material on the graded layer.

Description

METHOD OF PRODUCING RELAXED SILICON GERMANIUM LAYERS
PRIORITY INFORMATION
This application claims priority from provisional application Ser. No. 60/154,851 filed September 20, 1999.
BACKGROUND OF THE INVENTION
The invention relates to the field of relaxed SiGe layers.
The application of reiaxed SiGe layers on Si substrates in optoelectronics and electronics demands that an economical method of forming high quality material be obtained. A summary of the development of relaxed SiGe materials and their application can be found in "Silicon-based Microphotonics and Integrated Optoelectronics", by E.A. Fitzgerald and L.C. Kimerling, MRS Bulletin vol. 23 (1998). Additional details to their specific application in SiGe/Si heterostructures can be found in "SiGe Nanostructures", E.A. Fitzgerald, Annual Review of Material Science p. 417 (1995). In these references, the relaxed SiGe buffers are deposited via chemical vapor deposition (CVD).
CVD is, under most conditions and products, the most economical method of depositing thin layers of crystalline semiconductors. High thin-film growth rates are essential in producing economical relaxed SiGe materials on Si substrates, since the SiGe layers are relatively thick. The highest growth rates known to date, which have been deposited in non-commercial equipment, have been achieved with CVD, with a maximum growth rate of about 6 micrometers per hour.
Current methods of producing SiGe relaxed buffers in research environments consist of using, typically, silane or dichlorosilane for the silicon source gas, and germane for the germanium source gas. The silane molecule is a silicon atom surrounded by 4 hydrogen atoms, the dichlorosilane is the same except 2 of the hydrogen atom are replaced with chlorine atoms, and germane is a germanium atom bonded to 4 hydrogen atoms. These gases are flowed across a hot Si wafer. The gases breakdown and deposit the Si or Ge atom on the semiconductor substrate, and if the substrate is at a sufficient temperature, crystalline thin film growth proceeds. An upper limit in the thin film growth rate is defined by two main factors. One factor is that the CVD deposition equipment can become too coated with thin film deposit in areas other than the substrate area. If this deposition is too great, it may prevent a large number of consecutive wafer deposition processes, leading to greater cost. An additional problem is that in attempting to deposit films at high growth rates, gas-phase nucleation can occur, in which particles of SiGe, Si, or Ge form in the gas stream and subsequently deposit on the wafer surface.
This incorporation of particles into the epitaxial film not only degrades the material quality locally, but also serves as heterogeneous nucleation sites for additional threading dislocations. As a result, high temperature, high growth rate depositions result in material with high defect concentrations and poor surface morphology. Thus, in the conventional gas chemistry used for CVD deposition, there is a problem producing the highest quality films at high growth rates. The origin of this problem is the decomposition temperature of germane. The germane molecule decomposes at an even lower temperature than silane. Therefore, for a given temperature and gas concentration, there will be increased levels of gas phase nucleation and equipment coating when germane is used. This problem is exacerbated for high concentration germanium films, because the germanium concentration in the gas phase is proportionately higher. Since many of the applications for relaxed SiGe require Ge concentrations greater than 10%, these problems are quite severe for the majority of relaxed SiGe thin film growths.
SUMMARY OF THE INVENTION One solution to the problems of the prior art is to change the gas chemistry such that equipment coating and gas phase nucleation of particles is reduced. It is therefore desirable to use a germanium source that decomposes at a higher temperature.
Accordingly, the invention provides a method for making a semiconductor material, and subsequent structure, including providing a monocrystalline silicon substrate; epitaxially growing, using a source gas of GexHyClz for the germanium component, on the silicon substrate at a temperature in excess of 850°C a graded Si,.xGex layer with increasing germanium concentration at a gradient of less than 25% Ge per micron to a final composition in the range of 0.1<=x<=l; and epitaxially growing a layer of semiconductor material on the graded layer.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a graph showing the growth rate of epitaxial silicon as a function of growth temperature for a variety of Si source gases; FIG. 2 is a graph of the threading dislocation density at the surface of a relaxed
SiGe graded layer versus growth temperature for a CVD reactor; and
FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si,.xGex (0<x ≤l) and Si07Ge03, respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a graph showing the growth rate of silicon versus temperature for various source gases. Two distinct growth regimes are evident. For low temperatures, the growth rate has an exponential dependence on temperature, indicating that the growth is reaction rate or kinetically limited. For high temperatures, the growth rate has a weak dependence on temperature, indicating that the growth is mass transport or diffusion limited. Epitaxial layers are formed in the mass transport limited regime to minimize the effects of temperature variations during growth.
It is well known that as more hydrogen atoms in the silane molecule are replaced with chlorine atoms, the decomposition temperature of the source gas increases. This effect is evidenced by the shift of the reaction-limited regime to higher temperatures for source gases with increasing chlorine content. For example, the silicon tetrachloride (SiCl4) growth curve is shifted over 200°C toward higher temperatures from the silane (SiH4) growth curve. As a result, epitaxial films can be grown with SiCl4 at much higher temperatures than with SiH4 without the effects of gas phase nucleation and equipment coating. Additionally, extremely high growth rates can be achieved at high temperatures using these chlorine-based source gas chemistries.
Since the main problem in SiGe film growth is the low decomposition temperature of the germane gas, our invention uses a germanium-chlorine-based gas to increase the decomposition temperature. As in the silicon system, chlorogermanes can be used to extend growth temperatures to more than 200°C over germane growth temperatures without increasing gas phase nucleation. In this way, the decomposition temperatures of the gases can be optimally chosen such that very high growth rates can be achieved at high temperatures. The most readily available germanium-chlorine source gas is germanium tetrachloride, (GeCl4). This gas, unlike germane, can be used at growth temperatures in excess of 800°C to grow thick, relaxed SiGe layers without excessive equipment coating and particle formation. It can be combined with any of the source gases for silicon, such as silane, dichlorosilane, trichlorosilane, and silicon tetrachloride to form high quality SiGe layers.
The ability to deposit films at high temperatures using germanium tetrachloride also results in lower threading dislocation densities in the relaxed graded layer. The dislocation density in a relaxed graded structure is exponentially dependent on the temperature during growth. FIG. 2 is a graph showing experimental data of dislocation density versus growth temperature for SiGe graded layers. Currently, SiGe relaxed buffers with a 30% Ge final composition cannot be grown much above 800°C without experiencing severe gas phase nucleation.
Using conventional source gases at a growth temperature of 800°C results in a dislocation density in the mid-105 cm"2 range. With the germanium tetrachloride process, this growth temperature can be extended to over 1000°C without particle deposits or equipment coating. From Figure 2, it is evident that growth temperatures equal to or greater than 1000°C result in films with dislocation densities in the sub-105 cm"2 regime. Thus, by incorporating a different source gas for germanium introduction, the defect density in the relaxed SiGe layers is improved (lowered).
The structure that is deposited using this gas chemistry is similar to that outlined in Brasen et al., U.S. Pat. No. 5,221,413, incorporated herein by reference. FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si!.xGex (0<x <1) and Si07Ge03, respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention. The structures include a monocrystalline silicon substrate 300, a SiGe graded buffer layer 302, and a uniform concentration SiGe cap layer 304, 306. The SiGe buffer layer 302 is a series of SiGe layers with increasing Ge concentration, usually with a gradient of less than 25% Ge per micron. By increasing the Ge concentration gradually, the strain due to the lattice mismatch between Si and Ge is relieved and the threading dislocation density is minimized. The cap layers are high quality
SiGe layer with uniform Ge concentration that can be used as a platform for device fabrication.
FIG. 3 A shows a generic structure where the cap layer 304 Ge concentration can vary from 0< x ≤l. FIG. 3B shows a structure where the cap layer 306 is Si07Ge03. By using the germanium-chlorine based source gases described herein, these structures can be constructed with fewer defects and at a lower cost.
Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
What is claimed is:

Claims

1. A method for making a semiconductor material comprising the steps of: providing a monocrystalline silicon substrate; epitaxially growing, using a source gas of GexHyClz for the germanium component, on said silicon substrate at a temperature in excess of 850°C a graded Si,.xGex layer with increasing germanium concentration at a gradient of less than 25%) Ge per micron to a final composition in the range of 0.1 <=x<= 1 ; and epitaxially growing a layer of semiconductor material on said graded layer.
2. The method in claim 1 further comprising the step of incorporating a source gas of GexHyClz for the germanium component and silane gas for the silicon component.
3. The method in claim 1 further comprising the step of incorporating a source gas
Figure imgf000007_0001
for the germanium component and dichlorosilane gas for the silicon component.
4. The method in claim 1 further comprising the step of incorporating a source gas of GexHyClz for the germanium component and trichlorosilane gas for the silicon component.
5. The method in claim 2, wherein the source gas for the germanium component comprises germanium tetrachloride (GeCl4).
6. The method in claim 3, wherein the source gas for the germanium component comprises germanium tetrachloride (GeCl4).
7. The method in claim 4, wherein the source gas for the germanium component comprises germanium tetrachloride (GeCl4).
8. A semiconductor structure comprising: a monocrystalline silicon substrate; a graded Si,.xGex layer epitaxially grown, using a source gas of GexHyClz for the germanium component, on said silicon substrate at a temperature in excess of 850°C with increasing germanium concentration at a gradient of less than 25% Ge per micron to a final composition in the range of 0.1 <=x<=l ; and a layer of semiconductor material epitaxially grown on said graded layer.
PCT/US2000/040938 1999-09-20 2000-09-19 Method of producing relaxed silicon germanium layers WO2001022482A1 (en)

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JP2001525758A JP2003517726A (en) 1999-09-20 2000-09-19 Fabrication method of relaxed silicon germanium layer
EP00974128A EP1214735A1 (en) 1999-09-20 2000-09-19 Method of producing relaxed silicon germanium layers

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US60/154,851 1999-09-20

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Cited By (12)

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WO2003069657A1 (en) * 2002-02-15 2003-08-21 Centre National De La Recherche Scientifique Method for production of a layer of silicon carbide or a nitride of a group iii element on a suitable substrate
WO2003079415A2 (en) * 2002-03-14 2003-09-25 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
WO2004019391A2 (en) 2002-08-23 2004-03-04 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
WO2004086473A1 (en) 2003-03-19 2004-10-07 Amberwave Systems Corporation Method of producing high quality relaxed silicon germanium layers
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US7071014B2 (en) 2002-10-30 2006-07-04 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
EP1681711A1 (en) * 2005-01-05 2006-07-19 Siltronic AG Semiconductor wafer with a silicon-germanium layer and process for its manufacture
US7214598B2 (en) 2002-05-31 2007-05-08 Advancesis Limited Formation of lattice-tuning semiconductor substrates
US7288430B2 (en) 2000-11-27 2007-10-30 S.O.I.Tec Silicon On Insulator Technolgoies Method of fabricating heteroepitaxial microstructures
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
EP4220686A1 (en) * 2022-01-31 2023-08-02 Siltronic AG Method for depositing a strain relaxed graded buffer layer of silicon germanium on a surface of a substrate

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US7955435B2 (en) 1999-09-20 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of producing high quality relaxed silicon germanium layers
US7041170B2 (en) 1999-09-20 2006-05-09 Amberwave Systems Corporation Method of producing high quality relaxed silicon germanium layers
US7674335B2 (en) 1999-09-20 2010-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of producing high quality relaxed silicon germanium layers
US7646038B2 (en) 2000-11-27 2010-01-12 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating heteroepitaxial microstructures
US7288430B2 (en) 2000-11-27 2007-10-30 S.O.I.Tec Silicon On Insulator Technolgoies Method of fabricating heteroepitaxial microstructures
US7906776B2 (en) 2001-09-24 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
FR2836159A1 (en) * 2002-02-15 2003-08-22 Centre Nat Rech Scient METHOD FOR FORMING A LAYER OF SILICON CARBIDE OR ELEMENT III NITRIDE ON A SUITABLE SUBSTRATE
WO2003069657A1 (en) * 2002-02-15 2003-08-21 Centre National De La Recherche Scientifique Method for production of a layer of silicon carbide or a nitride of a group iii element on a suitable substrate
WO2003079415A2 (en) * 2002-03-14 2003-09-25 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
WO2003079415A3 (en) * 2002-03-14 2004-01-15 Amberwave Systems Corp Methods for fabricating strained layers on semiconductor substrates
US7214598B2 (en) 2002-05-31 2007-05-08 Advancesis Limited Formation of lattice-tuning semiconductor substrates
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
EP2267762A2 (en) 2002-08-23 2010-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
WO2004019391A2 (en) 2002-08-23 2004-03-04 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7202121B2 (en) 2002-10-30 2007-04-10 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
US7416909B2 (en) 2002-10-30 2008-08-26 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
US7541208B2 (en) 2002-10-30 2009-06-02 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
US7208332B2 (en) 2002-10-30 2007-04-24 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
US7071014B2 (en) 2002-10-30 2006-07-04 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
WO2004086473A1 (en) 2003-03-19 2004-10-07 Amberwave Systems Corporation Method of producing high quality relaxed silicon germanium layers
JP2006523380A (en) * 2003-03-19 2006-10-12 アンバーウェーブ システムズ コーポレイション Method for producing high quality relaxed silicon germanium layer
JP2011223020A (en) * 2003-03-19 2011-11-04 Taiwan Semiconductor Manufactuaring Co Ltd Method of producing high quality relaxed silicon germanium layer
EP1681711A1 (en) * 2005-01-05 2006-07-19 Siltronic AG Semiconductor wafer with a silicon-germanium layer and process for its manufacture
EP4220686A1 (en) * 2022-01-31 2023-08-02 Siltronic AG Method for depositing a strain relaxed graded buffer layer of silicon germanium on a surface of a substrate
WO2023143804A1 (en) * 2022-01-31 2023-08-03 Siltronic Ag Method for depositing a strain relaxed graded buffer layer of silicon germanium on a surface of a substrate

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