WO2001022659A2

WO2001022659A2 - Method and apparatus for distributed synchronization signal

Info

Publication number: WO2001022659A2
Application number: PCT/US2000/026336
Authority: WO
Inventors: Donald W. Moses; Robert W. Moses
Original assignee: Digital Harmony Technologies, Inc.
Priority date: 1999-09-23
Filing date: 2000-09-25
Publication date: 2001-03-29
Also published as: WO2001022659A3; JP2003524947A; AU7614200A

Abstract

A method and apparatus is described for distributing a synchronization signal for deriving sample rate clocks in data transmitted between nodes in a system such as an IEEE 1394 bus-interconnected system. The synchronization signal is coupled onto a conductor of the IEEE 1394 bus by a clock master node, and received by all other nodes. The synchronization signal is coupled to the conductor in the bus without interfering with the signal, such as a power or data signal, carried by that conductor. Each node may derive its sample rate clocks using conventional time stamp means, or optionally referencing its sample rate clocks to the synchronization signal for higher performance. The format of the synchronization signal may be virtually any type of standard or non-standard work clock or longitudinal time code.

Description

METHOD AND APPARATUS FOR DISTRIBUTED SYNCHRONIZATION SIGNAL

TECHNICAL FIELD

The present invention relates generally to bus system architecture and, more particularly, to a method and apparatus for distributing a synchronization clock signal.

BACKGROUND

Today's consumer electronic devices are increasingly being implemented as special-purpose computer systems, complete with processor, memory, and I/O functionality. The various companies who design and manufacture these devices may have their own particular interconnect technology and communication protocols. Consequently, compatibility problems can occur when connecting devices made by different manufacturers. In home entertainment systems, for example, a DVD player manufactured by one company may be incompatible with an audio surround sound decoder manufactured by another company.

To facilitate today's increasingly complex communication between electronic devices, various standards have been developed. In particular, the IEEE 1394 standard for a High Performance Serial Bus (also known as the "1394" bus) has been established to facilitate the development of compatible consumer electronics devices. In addition to defining a standard bus communications protocol, the 1394 bus architecture also provides for standard connections, with each interconnected device being able to communicate with every other such device without requiring individual point-to-point connections between the various devices. The IEEE 1394 standard (IEEE 1394-1995 and IEEE 1394a supplement) is entitled "Standard for a High Performance Serial Bus," and is based on the ISO/IEC 13213 (ANSI/IEEE 1212) specification, entitled "Information technology — Microprocessor systems — Control and Status Registers (CSR) Architecture for microcomputer buses."

Referring to Figure 1, a typical home entertainment system 100 is depicted. The system includes a high speed bus, such as an IEEE 1394 bus 102, that interconnects a variety of electronic devices. The particular configuration depicted is intended solely to show the functional interconnection of representative devices. Those skilled in the art understand that the 1394 bus architecture supports tree and daisy chain connection configurations.

A DVD player 104 is included for playing DVD disks and correspondingly outputting MPEG audio/video data streams on the 1394 bus 102. The audio and video data streams are transported over an isochronous channel of the 1394 bus 102, to an MPEG decoder 108 which demultiplexes the MPEG transport stream and transmits the audio elementary stream to the surround sound decoder 106. The MPEG decoder 106 simultaneously decodes the video elementary stream to a video signal which is typically output to a video monitor (not shown in the diagram). A cable or satellite set- top box 110 receives media from a cable or satellite television provider and outputs an audio/video MPEG data stream on an isochronous channel of the 1394 bus 102. The MPEG decoder 108 demultiplexes this data and sends the audio to the surround decoder 106 and decodes and outputs the video signal. The surround sound decoder 106 receives compressed audio signals from other devices connected to the 1394 bus 102 and decodes the audio. The decoded audio data is then output on the 1394 bus 102 to an amplifier/speaker subsystem 112. The MPEG decoder 108 decodes MPEG transport streams received from various source devices on the 1394 bus 102 and demultiplexes the audio and video. The audio is typically transmitted over the 1394 bus 102 to the surround sound decoder 106. The video is decoded and output to a video monitor for presentation.

A controller 114 provides a point of control for all devices in the system 100. The controller 1 14 may also provide a user interface to configure the system when various devices are added or removed. The controller typically includes a user interface for adjusting audio volume, turning devices on and off, selecting channels on the set-top box 110, etc. Indeed, the controller may be the only device a user interacts with (other than inserting disks into the DVD player 104).

Each of the interconnected devices shown in the system 100 Figure 1 includes interface circuitry connecting the 1394 bus 102 to the particular application circuitry included in the devices. Such interface circuitry includes both the physical electrical connections (known as the PHY layer) and the data format translation interface (known as the Link layer). Such interface circuitry is well known for those skilled in the art, and the general features of such circuitry need not be described herein.

For video and audio applications, which require constant data transfer rates, it is particularly important that a device receiving such data accurately recover the sample rate clock signal from the device transmitting such data. This ensures that data buffers in the system do not overflow or underflow, and that the temporal aspects of audio/video performance are not degraded. 1394 bus architecture supports transmission of isochronous data packets including time stamp information that can be used to recover the sample rate clock, such as in accordance with the IEC 61883 standard, entitled "Digital Interface for Consumer Audio/Video Equipment." Because there is no requirement that different data streams be frequency related (i.e., isochronous streams may have free-running sample rates), each receiving device or node must implement a separate clock recovery circuit for each received isochronous channel of the 1394 bus.

Referring to Figure 2, a functional block diagram depicts the prior art approach of providing time stamps and correspondingly recovering a sample rate clock. The interface circuitry included within a transmitting device or node 200 is depicted, as is a portion of the interface circuitry included within the receiving device or node 202. The transmitting node 200 includes a latch 204 that latches a lower portion of the value stored in a cycle time register 206 included within the Link layer of the interface circuitry. The cycle time register is clocked by oscillator 201. The latch 204 latches the cycle time value every predetermined number of cycles of the sample rate clock (such as a digital audio word clock in the case of audio data transmission). A transfer delay value is added to the latched cycle time register value, and the resulting time stamp is inserted into the header of the corresponding isochronous data packet 208. As is known to those skilled in the art, the value of the transfer delay is determined at system initialization or bus reset. At the receiving device or node 202, the received time stamp is compared with the corresponding lower portion of the value stored in the receiving node's cycle time register 210, clocked by oscillator 211. A comparator 212 produces a pulse signal in the event of equality, which is then input to a phase-locked loop (PLL) circuit 214 to recover the sample rate clock signal. The receiving node's cycle time register value is synchronized to the transmitting node's cycle register value by sending periodic updates to the each register from a "cycle master" node. These updates are sent every 125 microseconds, and oscillators 201 and 211 are specified to have frequency accuracy within 100 parts per million, thereby guaranteeing that the values of cycle time registers 206 and 210 are synchronized to less than one least significant bit (LSB) of the cycle time register. Therefore, this method recovers a sample rate clock signal with average frequency equal to the transmitter's sample rate clock signal, and adjustable resolution of 40.9ns (one LSB of the cycle time register).

The particular approach depicted in Figure 2 has a number of disadvantages. If the stream of time stamps is interrupted for any reason, such as during a bus reset, the pulse signal produced by the comparator 212 experiences drop outs, and the PLL 214 then temporarily loses lock and causes a glitch in the sample rate clock signal. Also, because each node on the bus has a free running oscillator (201 and 211), it is impossible to achieve perfect clock synchronization (exactly equal frequency and 0 degrees phase shift) between the recovered sample rate clocks in different nodes. Consequently, recovered sample rate clocks are prone to jitter and phase errors that degrade the quality of audio and video streams. An additional source of sample rate clock degradation is the retiming that data packets undergo in each node, introducing significant delay to the packets as they are transmitted over a heavily populated bus, and different delay to data packets transmitted over different paths in the system topology. This introduces significant, and different, delays to the time stamps and cycle time register updates, thereby introducing significant sample rate clock misalignment between nodes in the system. These degradations may render the resulting sample rate clock signals unsuitable for high performance systems.

In traditional digital audio and digital video systems it is common to distribute a synchronization signal separately from the digital audio and video data, as shown in Figure 3. This synchronization signal 302 is generated by a master device 304, and is received by a number of devices 306. The format of synchronization signal 302 may be a longitudinal time code such as the SMPTE (Society of Motion Picture and Television Engineers) Time Code; or a square wave "word clock" with frequency equal to the sample rate of the digital audio/video signal; or a "black" digital audio or video signal. This separate synchronization signal requires a separate connection means, thereby reducing the ease of installation and cost advantages of the all-in-one-cable IEEE 1394 serial bus. The standard IEEE 1394 serial bus cable does not contain unused conductors, therefore it cannot carry a separate synchronization signal. Furthermore, the low driving impedance of the circuitry interfacing to the IEEE 1394 cable signals precludes adding a voltage carrier to the existing signals using conventional signal coupling means.

SUMMARY

In accordance with the present invention, a method is provided for distributing a synchronization signal in a system of data exchanging node circuits interconnected by a bus. The method includes generating the synchronization signal and coupling the synchronization signal to a portion of the bus that carries another signal, such as a power or data signal. The synchronization signal may include a periodic signal having a frequency proportional to a sampling rate of the data exchanged by the node circuits. Alternatively, the synchronization signal may include a longitudinal time code signal or a data packet carrying a coded message corresponding to the data sample rate.

In accordance with another aspect of the present invention, a system is provided that has a data source coupled by a bus with a data receiver. The system includes a synchronization signal generator that is connected to a first portion of the bus by coupling circuitry. The synchronization signal generator generates a synchronization signal that is coupled to the first portion of the bus by the coupling circuitry, where the first portion of the bus also carries another signal. The system also includes decoupling circuitry that connects a synchronization signal detector with the first portion of the bus and decouples the synchronization signal from the other signal to provide the synchronization signal to the synchronization signal detector. One or both of the decoupling circuitry and synchronization signal detector may be included in the data receiver.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a functional block diagram that depicts a typical IEEE 1394 system.

Figure 2 is a functional block diagram that depicts circuitry for producing time stamps by a transmitting device and circuitry for sample rate clock recovery in a prior art receiving device in an IEEE 1394 system. Figure 3 is a functional block diagram depicting a typical system with a distributed synchronization signal.

Figures 4-7 are functional block diagrams depicting the standard methods of coupling a DC power signal to a conductor in an IEEE 1394 serial bus cable.

Figures 8-11 are functional block diagrams depicting a synchronization signal coupled to the power conductor in an IEEE 1394 serial bus cable by transmitter nodes, in accordance with an embodiment of the present invention.

Figures 12-15 are functional block diagrams depicting a synchronization signal coupled from the power conductor in an IEEE 1394 serial bus cable by receiver nodes, in accordance with an embodiment of the present invention.

Figure 16 is a functional block diagram depicting an electrical circuit which performs Frequency Shift Keying modulation and demodulation, and which constitutes a preferred embodiment of the present invention.

Figure 17 is a functional block diagram illustrating the connection of a transmitter and a receiver node.

Figure 18 is a functional block diagram illustrating the method of regenerating signal currents. Figure 19 is a functional block diagram of a system arbitrating for automatic selection of a synchronization signal generator.

DETAILED DESCRIPTION

The following is a description of circuitry and methods for recovering a data sample clock from an isochronous data packet stream. The circuitry and methods are conformable to the applicable IEEE 1394, ISO/IEC

13213, and IEC 61883 standards. In this description, certain details are set forth in order to provide a thorough understanding of various embodiments of the present invention. It will be clear to one skilled in the art, however, that the present invention may be practiced without these details. In other instances, well-known circuits, circuit components, control signals, and timing and communications protocols have not been shown or described in detail in order to avoid unnecessarily obscuring the description of the various embodiments of the invention. The described subject matter relates to technology similar to International Application No. PCT/US99/10805, filed

17 May 1999, and entitled "COMBINED ANALOG/DIGITAL DATA

TRANSMISSION SYSTEM," which is incorporated herein by reference.

Figures 4-7 show the conventional methods of coupling a power signal to a pair of conductors in the IEEE 1394 cable. A typical IEEE 1394 node 400 provides one or more bus connectors 402. In Figures 4 and 5, pin 1 of the bus connector 402 is fed with DC power via diode 404 and voltage source 406. Capacitor 408 provides filtering and reserve energy. This voltage is carried over the IEEE 1394 bus cable, to other nodes. In Figures 6 and 7, no power signal is provided. Pin 2 of bus connector 402 provides a ground return path for the DC current: Voltage regulator 410 receives the DC voltage from pin 1 of bus connector 402, and supplies this power to the physical layer interface circuitry.

Figures 8-11 show how the Transmitter Nodes add a synchronization signal to the power conductors in the IEEE 1394 cable. Transformer 512 has been added to the Transmitter Nodes to allow a current, ib, to be modulated onto this DC voltage. The Transmitter Nodes illustrated contain a synchronization signal generator 518 that is buffered by 516 and connected to the primary winding of transformer 512. Capacitors 514 provides DC blocking to prevent the transformer coil from saturating. Capacitors 515 provide DC blocking to isolate power regions on the IEEE 1394 bus. Buffer 516 induces a current, ic, into the transformer 512 primary winding. The current added alternates proportional to the synchronization signal 518. IEEE 1394 connector 502 pin 1 therefore has a combination of DC voltage and current received via diode 504 and alternating current ib received via transformer 512 secondary winding.

. Figures 12-15 show how the Receiver Nodes detect the synchronization signal. The signal is connected to pin 1 of IEEE 1394 bus connector. Transformer 542 has been added to the Receiver Nodes to allow a current, ib, to be demodulated. The Receiver Nodes illustrated contain a synchronization signal detector 548 that is buffered by 546 and connected to the primary winding of transformer 542. Capacitor 544 provides DC blocking to prevent the transformer coil from saturating The current ib from the Transmitter Node energizes the primary winding of transformer 542, causing a current ic to appear in the secondary winding of transformer 542. Current to voltage converter/buffer 546 converts current ic to a voltage, and outputs this to synchronization signal detector 548. Figure 16 depicts an electrical circuit which performs Frequency Shift Keying modulation and demodulation, and which constitutes a preferred embodiment of the present invention. Alternative means of modulating and demodulating the synchronization signal may be employed, such as Amplitude Shift Keying, Minimum Shift Keying, Gaussian Minimum Shift Keying, direct coupling of the baseband signal, or others known to those skilled in the art. In addition, the functional blocks required to accomplish the generation and detection of the signal may be composed of discrete logic devices, as in Figure 16, or of logic blocks in a Field Programmable Gate Array or an Application Specific Integrated Circuit. Microprocessors or Digital Signal Processors may also be employed to generate or detect the signals, using algorithms embodied in their firmware.

Nodes 500 and 530 exchange a DC voltage and the AC synchronization current over the IEEE 1394 bus cable 520 as described in Figure 17. In the configuration shown, node A 500 is the synchronization signal transmitter, and node B 530 is the synchronization signal receiver. The current generated by the Transmitter Node is reflected by a corresponding current, ib, in the secondary winding of transformer 512 in the Receiver Node. It can be seen that the synchronization signal received by 548 is exactly proportional to the synchronization signal transmitted by 518. Therefore, this system has exchanged a synchronization signal between nodes that can be used to represent digital audio, digital video, and other clocks between nodes.

This method operates over a topology of nodes interconnected via multiple cables. For example, in Figure 17, all bus connectors 502 and

532 may be connected to other nodes via bus cables 520, and portions of current ib will be transmitted to the other nodes and recovered similarly to node 530. Therefore, this method provides a means to share a synchronization signal amongst a number of nodes.

If synchronization current ib is degraded by splitting it between many nodes, it could be regenerated at each node before being passed on to the next node, using the method illustrated in Figure 18. This method may also be used to minimize electrical noise propagation between nodes, as an alternative to that illustrated in Figure 8.

Those skilled in the art would understand that it is possible to adapt the above-described circuitry and methods for operation over other conductors in the IEEE 1394 bus cable. It is also possible to apply these circuitry and methods to buses and systems other than IEEE 1394, such as the universal serial bus (USB), ethernet, and power distribution systems. The signal transmitted using this invention could be then formatted in accordance with a corresponding communications protocol to convey messages between nodes.

A protocol for manually or automatically selecting the node in the system to serve as the synchronization signal generator could be introduced to simplify system operation. One method to automatically select this generator node is to designate the node with the lowest bus identification number. Alternatively, an operator could input command to the system specifying the identity of the synchronization signal generator node.

Figure 19 shows an example system 600 with five nodes 601- 605. As is standard on a IEEE 1394 bus, each node is assigned an identification number sequentially from 0 to N-l, where N is equal to the number of nodes on the bus. Each node on the bus that is capable of generating a synchronization signal advertises its capability at a known address within its address space. Any node 601-605 on the bus can, with a single memory read, determine if other nodes are capable of serving as a synchronization signal generator. At the completion of a bus reset (at which time the topology is stable), each potential synchronization generator 603 and 605 queries other nodes on the network to discover if a synchronization generator with a lower node number exists. The synchronization signal generator node 603 with the lowest node number will not find another synchronization generator with a lower identification number, and will therefore automatically become the synchronization signal generator. The node 605 with a higher node number than the other synchronization generator node 603 will automatically become a synchronization receiver.

In a heterogeneous network, not all synchronization generators may have the same capability. People configuring the network may wish to select a different synchronization generator than the one that would be selected automatically. This may be done by polling the complete network, and requesting all other nodes, apart from the one desired, to no longer advertise their synchronization generator capability on the network. Causing a bus reset will then move the clock source to the remaining node.

In case of user error, and all nodes are disabled, if a possible source node is unable to determine an available source node, it will remove the restriction, and then cause a bus reset. Since all source nodes take the same action, this is equivalent to setting the network back to automatic selection. Of course this is just one method to automatically select a synchronization signal generator, and those skilled in the art will understand that it is possible to apply other algorithms for selecting a generator.

Several types of devices could be implemented using this technology. A hub device could be implemented that serves as the synchronization signal generator node, with receive-only nodes connected to it. Alternatively, each node could be configured to serve as sender or receiver of the synchronization signal by swapping buffer 516 for buffer 546 and synchronization signal generator 518 for synchronization signal receiver 548 with a simple switching network.

From the foregoing, it will be appreciated that, although specific embodiments of the invention have been described above for purposes of illustration, various modifications may be made to these embodiments without deviating from the spirit and scope of the invention. Those skilled in the art will understand that any of a wide variety of circuit topologies could be employed to couple and decouple synchronization signals to signal lines carrying other signals. Also, many of the above-described circuit embodiments could instead be performed in software. Indeed, numerous variations are well within the scope of the invention, and the invention is not limited except as by the appended claims.

Claims

CLAIMS A method of providing a synchronization signal in a system of data exchanging node circuits interconnected by a bus, the method comprising: generating the synchronization signal; coupling the synchronization signal to a portion of the bus carrying another signal; receiving the coupled signals; and decoupling the synchronization signal from the other signal.

2. The method of claim 1 wherein the other signal includes a power signal.

3. The method of claim 1 wherein the other signal includes a data signal.

4. The method of claim 1 wherein generating the synchronization signal includes generating a periodic signal having a frequency proportional to a sampling rate of the data exchanged by the node circuits.

5. The method of claim 1 wherein generating the synchronization signal includes generating a longitudinal time code signal.

6. The method of claim 1 wherein generating the synchronization signal includes generating the synchronization signal at a manually selected one of node circuits.

7. The method of claim 1 wherein generating the synchronization signal includes generating the synchronization signal at an automatically selected one of node circuits.

8. The method of claim 1 wherein the coupled signals are received at each of the node circuits.

9. The method of claim 1, further comprising: regenerating the synchronization signal; and recoupling the synchronization signal to the portion of the bus carrying the other signal.

10. The method of claim 1 wherein the bus is an IEEE 1394 bus.

11. In a system including a data source coupled by a bus with a data receiver, the data source producing a stream of isochronous data packets having associated time stamp values, and the data receiver receiving the isochronous data packets, a method for the data receiver to recover a data sample rate, comprising: selecting one of first and second data sample rate recovery methods; if the first method is selected, then recovering the data sample rate corresponding to the received time stamp values; and if the second method is selected, then: generating a synchronization signal corresponding with the data sample rate; coupling the synchronization signal to a portion of the bus carrying another signal; receiving the coupled signals at the data receiver; and decoupling at the data receiver the synchronization signal from the other signal.

12. The method of claim 11 wherein the other signal includes a power signal or a data signal.

13. The method of claim 11 wherein generating the synchronization signal includes generating a periodic signal having a frequency proportional to the data sample rate.

14. The method of claim 11 wherein generating the synchronization signal includes generating a longitudinal time code signal corresponding to the data sample rate.

15. The method of claim 11 wherein generating the synchronization signal includes generating a data packet carrying a coded message corresponding to the data sample rate.

16. The method of claim 11 wherein the data source includes an audio source, and the data receiver includes an audio receiver.

17. The method of claim 11, further comprising: receiving the coupled signals at the data source; and decoupling at the data source the synchronization signal from the other signal.

18. The method of claim 11, wherein the synchronization signal is generated and coupled to the bus at the data source.

19. The method of claim 11, wherein the bus is an IEEE 1394 bus.

20. A system having a data source coupled by a bus with a data receiver, the data source producing a stream of data packets and the data receiver receiving the data packets, the system further comprising: a synchronization signal generator operable to produce a synchronization signal; coupling circuitry connecting the synchronization signal generator to a first portion of the bus, the coupling circuitry being operable to couple the synchronization signal with another signal carried on the first portion of the bus; a synchronization signal detector; and decoupling circuitry connecting the synchronization signal detector with the first portion of the bus, the decoupling circuitry being operable to decouple the synchronization signal from the other signal and to provide the synchronization signal to the synchronization signal detector.

21. The system of claim 20 wherein the coupling circuitry includes a transformer.

22. The system of claim 20 wherein the decoupling circuitry includes a transformer. i 23. The system of claim 20 wherein the synchronization

2 signal detector is included within the data receiver.

1 24. The system of claim 20 wherein the decoupling circuitry

2 is included within the data receiver.

i

25. The system of claim 20 wherein the other signal carried

2 on the first portion of the bus includes a power signal.

i

26. The system of claim 20 wherein the other signal carried

2 on the first portion of the bus includes a data signal.

i

27. The system of claim 20 wherein the synchronization

2 signal includes a periodic signal having a frequency proportional to a

3 sampling rate of the data transmitted by the data source.

i

28. The system of claim 20 wherein the synchronization

2 signal includes a data packet carrying a coded message corresponding to a

3 sampling rate of the data transmitted by the data source.

1 29. The system of claim 20 wherein the data packets are

2 isochronous data packets having associated time stamp values, and wherein

3 the data receiver includes circuitry operable to receive the time stamp values

4 and responsively recover a sampling rate of the data transmitted by the data

5 source.

1 30. The system of claim 20 wherein the bus is an IEEE

2 1394 bus.

31. A home entertainment system, comprising: an audio/video source operable to produce a stream of data packets having associated time stamp values; an audio/video receiver operable to receive the stream of data packets; a bus coupling the audio/video source and receiver; and a synchronization signal generator coupled with a first portion of the bus and operable to produce a synchronization signal that is coupled with another signal carried on the first portion of the bus; and wherein the audio/video receiver includes: a clock recovery circuit operable to receive the time stamp values and to produce a clock signal having a frequency associated with the received time stamp values; and a synchronization signal detector coupled with the first portion of the bus and operable to receive the synchronization signal.

32. The home entertainment system of claim 31 wherein the first portion of the bus carries a power signal to the audio/video source and receiver.

33. The home entertainment system of claim 31 wherein the synchronization signal generator is included within the audio/video source.

34. The home entertainment system of claim 31 wherein the synchronization signal detector is a first synchronization signal detector, and wherein the audio/video source includes a second synchronization signal detector coupled with the first portion of the bus and operable to receive the synchronization signal.

35. The home entertainment system of claim 31, further comprising a transformer coupling the synchronization signal generator with the first portion of the bus.

36. The home entertainment system of claim 31, further comprising a transformer coupling the synchronization signal detector with the first portion of the bus.

37. The home entertainment system of claim 31 wherein the bus is an IEEE 1394 bus.