WO2001024031A3 - Multiprocessor node controller circuit and method - Google Patents

Multiprocessor node controller circuit and method Download PDF

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Publication number
WO2001024031A3
WO2001024031A3 PCT/US2000/027003 US0027003W WO0124031A3 WO 2001024031 A3 WO2001024031 A3 WO 2001024031A3 US 0027003 W US0027003 W US 0027003W WO 0124031 A3 WO0124031 A3 WO 0124031A3
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WO
WIPO (PCT)
Prior art keywords
memory
subset
port
node controller
directory
Prior art date
Application number
PCT/US2000/027003
Other languages
French (fr)
Other versions
WO2001024031A9 (en
WO2001024031A2 (en
Inventor
Martin M Deneroff
Givargis G Kaldani
Yuval Koren
David Edward Mccracken
Swaminathan Venkataraman
Original Assignee
Martin M Deneroff
Givargis G Kaldani
Yuval Koren
David Edward Mccracken
Swaminathan Venkataraman
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Martin M Deneroff, Givargis G Kaldani, Yuval Koren, David Edward Mccracken, Swaminathan Venkataraman, Silicon Graphics Inc filed Critical Martin M Deneroff
Priority to EP00967187A priority Critical patent/EP1222559B1/en
Priority to DE60006842T priority patent/DE60006842T2/en
Priority to JP2001526730A priority patent/JP4472909B2/en
Publication of WO2001024031A2 publication Critical patent/WO2001024031A2/en
Publication of WO2001024031A3 publication Critical patent/WO2001024031A3/en
Publication of WO2001024031A9 publication Critical patent/WO2001024031A9/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

Abstract

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.
PCT/US2000/027003 1999-09-29 2000-09-29 Multiprocessor node controller circuit and method WO2001024031A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00967187A EP1222559B1 (en) 1999-09-29 2000-09-29 Multiprocessor node controller circuit and method
DE60006842T DE60006842T2 (en) 1999-09-29 2000-09-29 Multiprocessor node controller circuit and method
JP2001526730A JP4472909B2 (en) 1999-09-29 2000-09-29 Multiprocessor node controller circuit and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/407,428 US6751698B1 (en) 1999-09-29 1999-09-29 Multiprocessor node controller circuit and method
US09/407,428 1999-09-29

Publications (3)

Publication Number Publication Date
WO2001024031A2 WO2001024031A2 (en) 2001-04-05
WO2001024031A3 true WO2001024031A3 (en) 2001-08-23
WO2001024031A9 WO2001024031A9 (en) 2001-09-20

Family

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Family Applications (1)

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PCT/US2000/027003 WO2001024031A2 (en) 1999-09-29 2000-09-29 Multiprocessor node controller circuit and method

Country Status (5)

Country Link
US (3) US6751698B1 (en)
EP (1) EP1222559B1 (en)
JP (1) JP4472909B2 (en)
DE (1) DE60006842T2 (en)
WO (1) WO2001024031A2 (en)

Families Citing this family (209)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US7072817B1 (en) * 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
AU2001222161A1 (en) * 2000-07-28 2002-02-13 Delvalley Limited A data processor
US7213087B1 (en) * 2000-08-31 2007-05-01 Hewlett-Packard Development Company, L.P. Mechanism to control the allocation of an N-source shared buffer
US20020161453A1 (en) * 2001-04-25 2002-10-31 Peltier Michael G. Collective memory network for parallel processing and method therefor
EP1255201B1 (en) * 2001-05-01 2009-12-23 Sun Microsystems, Inc. Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols
US7222220B2 (en) * 2001-05-01 2007-05-22 Sun Microsystems, Inc. Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices
US7486685B2 (en) * 2001-06-29 2009-02-03 Rankin Linda J System for sharing channels by interleaving flits
US7062609B1 (en) * 2001-09-19 2006-06-13 Cisco Technology, Inc. Method and apparatus for selecting transfer types
US7274692B1 (en) * 2001-10-01 2007-09-25 Advanced Micro Devices, Inc. Method and apparatus for routing packets that have multiple destinations
US7295563B2 (en) * 2001-10-01 2007-11-13 Advanced Micro Devices, Inc. Method and apparatus for routing packets that have ordering requirements
US7221678B1 (en) * 2001-10-01 2007-05-22 Advanced Micro Devices, Inc. Method and apparatus for routing packets
US6901491B2 (en) * 2001-10-22 2005-05-31 Sun Microsystems, Inc. Method and apparatus for integration of communication links with a remote direct memory access protocol
JP3683211B2 (en) * 2001-12-10 2005-08-17 エヌイーシーコンピュータテクノ株式会社 Inter-node data transfer method and inter-node data transfer apparatus
US6807586B2 (en) * 2002-01-09 2004-10-19 International Business Machines Corporation Increased computer peripheral throughput by using data available withholding
US7088711B2 (en) * 2002-02-05 2006-08-08 Forcelo Networks, Inc. High-speed router backplane
CN1152330C (en) * 2002-04-09 2004-06-02 威盛电子股份有限公司 Maintain method for remote node to read local memory and its application device
GB2389207B (en) * 2002-04-09 2004-05-12 Via Tech Inc Remote node accessing local memory by using distributed shared memory
US20030221030A1 (en) * 2002-05-24 2003-11-27 Timothy A. Pontius Access control bus system
US7281055B2 (en) * 2002-05-28 2007-10-09 Newisys, Inc. Routing mechanisms in systems having multiple multi-processor clusters
US7103636B2 (en) * 2002-05-28 2006-09-05 Newisys, Inc. Methods and apparatus for speculative probing of a remote cluster
US6865595B2 (en) * 2002-05-28 2005-03-08 Newisys, Inc. Methods and apparatus for speculative probing of a remote cluster
EP1376373B1 (en) * 2002-06-20 2006-05-31 Infineon Technologies AG Arrangement having a first device and a second device connected via a cross bar switch
US7051150B2 (en) * 2002-07-29 2006-05-23 Freescale Semiconductor, Inc. Scalable on chip network
US7200137B2 (en) * 2002-07-29 2007-04-03 Freescale Semiconductor, Inc. On chip network that maximizes interconnect utilization between processing elements
US6996651B2 (en) * 2002-07-29 2006-02-07 Freescale Semiconductor, Inc. On chip network with memory device address decoding
US7139860B2 (en) * 2002-07-29 2006-11-21 Freescale Semiconductor Inc. On chip network with independent logical and physical layers
US7277449B2 (en) * 2002-07-29 2007-10-02 Freescale Semiconductor, Inc. On chip network
US7346744B1 (en) 2002-11-04 2008-03-18 Newisys, Inc. Methods and apparatus for maintaining remote cluster state information
US7003633B2 (en) * 2002-11-04 2006-02-21 Newisys, Inc. Methods and apparatus for managing probe requests
US7296121B2 (en) * 2002-11-04 2007-11-13 Newisys, Inc. Reducing probe traffic in multiprocessor systems
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7577755B2 (en) * 2002-11-19 2009-08-18 Newisys, Inc. Methods and apparatus for distributing system management signals
US7447794B1 (en) * 2002-12-04 2008-11-04 Silicon Graphics, Inc. System and method for conveying information
US7353321B2 (en) * 2003-01-13 2008-04-01 Sierra Logic Integrated-circuit implementation of a storage-shelf router and a path controller card for combined use in high-availability mass-storage-device shelves that may be incorporated within disk arrays
US7024510B2 (en) * 2003-03-17 2006-04-04 Hewlett-Packard Development Company, L.P. Supporting a host-to-input/output (I/O) bridge
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US6982892B2 (en) * 2003-05-08 2006-01-03 Micron Technology, Inc. Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
US7334089B2 (en) * 2003-05-20 2008-02-19 Newisys, Inc. Methods and apparatus for providing cache state information
US7184916B2 (en) * 2003-05-20 2007-02-27 Cray Inc. Apparatus and method for testing memory cards
US7320100B2 (en) * 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
US7386626B2 (en) * 2003-06-23 2008-06-10 Newisys, Inc. Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systems
US7337279B2 (en) * 2003-06-27 2008-02-26 Newisys, Inc. Methods and apparatus for sending targeted probes
US7395347B2 (en) * 2003-08-05 2008-07-01 Newisys, Inc, Communication between and within multi-processor clusters of multi-cluster computer systems
US7028130B2 (en) * 2003-08-14 2006-04-11 Texas Instruments Incorporated Generating multiple traffic classes on a PCI Express fabric from PCI devices
US7171499B2 (en) * 2003-10-10 2007-01-30 Advanced Micro Devices, Inc. Processor surrogate for use in multiprocessor systems and multiprocessor system using same
US7769959B2 (en) 2004-01-20 2010-08-03 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration to memory
US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US20050160238A1 (en) * 2004-01-20 2005-07-21 Steely Simon C.Jr. System and method for conflict responses in a cache coherency protocol with ordering point migration
US7149852B2 (en) * 2004-01-20 2006-12-12 Hewlett Packard Development Company, Lp. System and method for blocking data responses
US8090914B2 (en) * 2004-01-20 2012-01-03 Hewlett-Packard Development Company, L.P. System and method for creating ordering points
US7620696B2 (en) * 2004-01-20 2009-11-17 Hewlett-Packard Development Company, L.P. System and method for conflict responses in a cache coherency protocol
US7818391B2 (en) 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
US8176259B2 (en) 2004-01-20 2012-05-08 Hewlett-Packard Development Company, L.P. System and method for resolving transactions in a cache coherency protocol
US8468308B2 (en) * 2004-01-20 2013-06-18 Hewlett-Packard Development Company, L.P. System and method for non-migratory requests in a cache coherency protocol
US7757033B1 (en) 2004-02-13 2010-07-13 Habanero Holdings, Inc. Data exchanges among SMP physical partitions and I/O interfaces enterprise servers
US20050182915A1 (en) * 2004-02-12 2005-08-18 Patrick Devaney Chip multiprocessor for media applications
US7843906B1 (en) * 2004-02-13 2010-11-30 Habanero Holdings, Inc. Storage gateway initiator for fabric-backplane enterprise servers
US8868790B2 (en) 2004-02-13 2014-10-21 Oracle International Corporation Processor-memory module performance acceleration in fabric-backplane enterprise servers
US7873693B1 (en) * 2004-02-13 2011-01-18 Habanero Holdings, Inc. Multi-chassis fabric-backplane enterprise servers
US7685281B1 (en) 2004-02-13 2010-03-23 Habanero Holdings, Inc. Programmatic instantiation, provisioning and management of fabric-backplane enterprise servers
US7633955B1 (en) 2004-02-13 2009-12-15 Habanero Holdings, Inc. SCSI transport for fabric-backplane enterprise servers
US7290169B2 (en) * 2004-04-06 2007-10-30 Hewlett-Packard Development Company, L.P. Core-level processor lockstepping
US7296181B2 (en) * 2004-04-06 2007-11-13 Hewlett-Packard Development Company, L.P. Lockstep error signaling
US7237144B2 (en) * 2004-04-06 2007-06-26 Hewlett-Packard Development Company, L.P. Off-chip lockstep checking
JP4469306B2 (en) * 2004-04-30 2010-05-26 株式会社日立製作所 Computer system, management server
KR20040052921A (en) * 2004-05-17 2004-06-23 김기천 Clock synchronizer for distributed traffic control
JP3780457B2 (en) * 2004-06-07 2006-05-31 株式会社トヨタＩｔ開発センター Signal processing apparatus, method, program, and recording medium
US8713295B2 (en) 2004-07-12 2014-04-29 Oracle International Corporation Fabric-backplane enterprise servers with pluggable I/O sub-system
US8000322B2 (en) * 2004-07-30 2011-08-16 Hewlett-Packard Development Company, L.P. Crossbar switch debugging
US20060072563A1 (en) * 2004-10-05 2006-04-06 Regnier Greg J Packet processing
WO2006040718A1 (en) * 2004-10-12 2006-04-20 Koninklijke Philips Electronics N. V. Switch device and communication network comprising such switch device as well as method for transmitting data within at least one virtual channel
US7600023B2 (en) * 2004-11-05 2009-10-06 Hewlett-Packard Development Company, L.P. Systems and methods of balancing crossbar bandwidth
US7290085B2 (en) * 2004-11-16 2007-10-30 International Business Machines Corporation Method and system for flexible and efficient protocol table implementation
US20060149923A1 (en) * 2004-12-08 2006-07-06 Staktek Group L.P. Microprocessor optimized for algorithmic processing
US7970980B2 (en) * 2004-12-15 2011-06-28 International Business Machines Corporation Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures
US20060174050A1 (en) * 2005-01-31 2006-08-03 International Business Machines Corporation Internal data bus interconnection mechanism utilizing shared buffers supporting communication among multiple functional components of an integrated circuit chip
US7136954B2 (en) * 2005-01-31 2006-11-14 International Business Machines Corporation Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism
US7493426B2 (en) * 2005-01-31 2009-02-17 International Business Machines Corporation Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control
US7483428B2 (en) * 2005-02-10 2009-01-27 International Business Machines Corporation Data processing system, method and interconnect fabric supporting a node-only broadcast
US7206889B2 (en) * 2005-03-22 2007-04-17 Hewlett-Packard Development Company, L.P. Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes
JP4758476B2 (en) * 2005-05-18 2011-08-31 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Arbitration method in an integrated circuit and a network on the integrated circuit
JP2006352706A (en) * 2005-06-17 2006-12-28 Hitachi Ltd Microprocessor, network system and communication method
WO2007038445A2 (en) 2005-09-26 2007-04-05 Advanced Cluster Systems, Llc Clustered computer system
JP4546380B2 (en) * 2005-10-04 2010-09-15 エヌイーシーコンピュータテクノ株式会社 Crossbar switch, information processing apparatus, and transfer method
US7890686B2 (en) * 2005-10-17 2011-02-15 Src Computers, Inc. Dynamic priority conflict resolution in a multi-processor computer system having shared resources
JP4887824B2 (en) * 2006-02-16 2012-02-29 富士通セミコンダクター株式会社 Memory system
GB2435531A (en) * 2006-02-27 2007-08-29 Sharp Kk Control Flow Protection Mechanism
US8082289B2 (en) 2006-06-13 2011-12-20 Advanced Cluster Systems, Inc. Cluster computing support for application programs
US7451260B2 (en) * 2006-10-23 2008-11-11 Hewlett-Packard Development Company, L.P. Interleave mechanism for a computing environment
US20080115139A1 (en) * 2006-10-27 2008-05-15 Todd Alan Inglett Barrier-based access to a shared resource in a massively parallel computer system
US7773617B2 (en) * 2006-11-08 2010-08-10 Sicortex, Inc. System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system
US20080162748A1 (en) * 2006-12-31 2008-07-03 Blaise Fanning Efficient power management techniques for computer systems
US20080172510A1 (en) * 2007-01-16 2008-07-17 Wei-Jen Chen Parallel bus architecture and related method for interconnecting sub-systems utilizing a parallel bus
US8238334B2 (en) * 2007-04-30 2012-08-07 Futurewei Technologies Inc. Optimal path selection for accessing networked applications
US7953863B2 (en) * 2007-05-08 2011-05-31 Intel Corporation Techniques for timing optimization in wireless networks that utilize a universal services interface
EP2169555A4 (en) * 2007-06-20 2011-01-05 Fujitsu Ltd Cache controller, cache control method and cache control program
US8509255B2 (en) 2007-06-26 2013-08-13 International Business Machines Corporation Hardware packet pacing using a DMA in a parallel computer
US8468416B2 (en) 2007-06-26 2013-06-18 International Business Machines Corporation Combined group ECC protection and subgroup parity protection
US7802025B2 (en) 2007-06-26 2010-09-21 International Business Machines Corporation DMA engine for repeating communication patterns
US7984448B2 (en) * 2007-06-26 2011-07-19 International Business Machines Corporation Mechanism to support generic collective communication across a variety of programming models
US7827391B2 (en) 2007-06-26 2010-11-02 International Business Machines Corporation Method and apparatus for single-stepping coherence events in a multiprocessor system under software control
US8230433B2 (en) 2007-06-26 2012-07-24 International Business Machines Corporation Shared performance monitor in a multiprocessor system
US8010875B2 (en) 2007-06-26 2011-08-30 International Business Machines Corporation Error correcting code with chip kill capability and power saving enhancement
US7761687B2 (en) * 2007-06-26 2010-07-20 International Business Machines Corporation Ultrascalable petaflop parallel supercomputer
US8108738B2 (en) 2007-06-26 2012-01-31 International Business Machines Corporation Data eye monitor method and apparatus
US8103832B2 (en) * 2007-06-26 2012-01-24 International Business Machines Corporation Method and apparatus of prefetching streams of varying prefetch depth
US7886084B2 (en) 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US8032892B2 (en) * 2007-06-26 2011-10-04 International Business Machines Corporation Message passing with a limited number of DMA byte counters
US8756350B2 (en) 2007-06-26 2014-06-17 International Business Machines Corporation Method and apparatus for efficiently tracking queue entries relative to a timestamp
US7793038B2 (en) 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
US7877551B2 (en) * 2007-06-26 2011-01-25 International Business Machines Corporation Programmable partitioning for high-performance coherence domains in a multiprocessor system
US8458282B2 (en) 2007-06-26 2013-06-04 International Business Machines Corporation Extended write combining using a write continuation hint flag
US8140925B2 (en) 2007-06-26 2012-03-20 International Business Machines Corporation Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
US20090089510A1 (en) * 2007-09-28 2009-04-02 Mips Technologies, Inc. Speculative read in a cache coherent microprocessor
US8392663B2 (en) * 2007-12-12 2013-03-05 Mips Technologies, Inc. Coherent instruction cache utilizing cache-op execution resources
US7974278B1 (en) 2007-12-12 2011-07-05 Integrated Device Technology, Inc. Packet switch with configurable virtual channels
US8055879B2 (en) * 2007-12-13 2011-11-08 International Business Machines Corporation Tracking network contention
US8117401B2 (en) 2008-02-01 2012-02-14 International Business Machines Corporation Interconnect operation indicating acceptability of partial data delivery
US8024527B2 (en) * 2008-02-01 2011-09-20 International Business Machines Corporation Partial cache line accesses based on memory access patterns
US8266381B2 (en) * 2008-02-01 2012-09-11 International Business Machines Corporation Varying an amount of data retrieved from memory based upon an instruction hint
US8108619B2 (en) * 2008-02-01 2012-01-31 International Business Machines Corporation Cache management for partial cache line operations
US7958309B2 (en) 2008-02-01 2011-06-07 International Business Machines Corporation Dynamic selection of a memory access size
US8250307B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Sourcing differing amounts of prefetch data in response to data prefetch requests
US8255635B2 (en) * 2008-02-01 2012-08-28 International Business Machines Corporation Claiming coherency ownership of a partial cache line of data
US20090198910A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Data processing system, processor and method that support a touch of a partial cache line of data
US8140771B2 (en) * 2008-02-01 2012-03-20 International Business Machines Corporation Partial cache line storage-modifying operation based upon a hint
US8490110B2 (en) * 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090248988A1 (en) * 2008-03-28 2009-10-01 Mips Technologies, Inc. Mechanism for maintaining consistency of data written by io devices
US9225545B2 (en) 2008-04-01 2015-12-29 International Business Machines Corporation Determining a path for network traffic between nodes in a parallel computer
US7796585B2 (en) * 2008-05-21 2010-09-14 Dell Products, Lp Network switching in a network interface device and method of use thereof
US8397030B2 (en) 2008-06-24 2013-03-12 International Business Machines Corporation Efficient region coherence protocol for clustered shared-memory multiprocessor systems
US20100005212A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Providing a variable frame format protocol in a cascade interconnected memory system
US7907625B1 (en) 2008-08-04 2011-03-15 Integrated Device Technology, Inc. Power reduction technique for buffered crossbar switch
US8166146B2 (en) * 2008-09-29 2012-04-24 International Business Machines Corporation Providing improved message handling performance in computer systems utilizing shared network devices
US8209489B2 (en) * 2008-10-22 2012-06-26 International Business Machines Corporation Victim cache prefetching
US8347037B2 (en) * 2008-10-22 2013-01-01 International Business Machines Corporation Victim cache replacement
US8225045B2 (en) * 2008-12-16 2012-07-17 International Business Machines Corporation Lateral cache-to-cache cast-in
US8499124B2 (en) * 2008-12-16 2013-07-30 International Business Machines Corporation Handling castout cache lines in a victim cache
US8489819B2 (en) * 2008-12-19 2013-07-16 International Business Machines Corporation Victim cache lateral castout targeting
US8799587B2 (en) * 2009-01-26 2014-08-05 International Business Machines Corporation Region coherence array for a mult-processor system having subregions and subregion prefetching
US8285942B2 (en) * 2009-01-27 2012-10-09 International Business Machines Corporation Region coherence array having hint bits for a clustered shared-memory multiprocessor system
EP2393015B1 (en) * 2009-01-30 2015-07-01 Fujitsu Limited Information processing system, information processing device, control method for information processing device, control program for information processing device, and computer-readable recording medium
US8949540B2 (en) * 2009-03-11 2015-02-03 International Business Machines Corporation Lateral castout (LCO) of victim cache line in data-invalid state
US8095733B2 (en) * 2009-04-07 2012-01-10 International Business Machines Corporation Virtual barrier synchronization cache castout election
US8131935B2 (en) * 2009-04-07 2012-03-06 International Business Machines Corporation Virtual barrier synchronization cache
US8103847B2 (en) * 2009-04-08 2012-01-24 Microsoft Corporation Storage virtual containers
US8312220B2 (en) * 2009-04-09 2012-11-13 International Business Machines Corporation Mode-based castout destination selection
US8347036B2 (en) * 2009-04-09 2013-01-01 International Business Machines Corporation Empirically based dynamic control of transmission of victim cache lateral castouts
US8327073B2 (en) * 2009-04-09 2012-12-04 International Business Machines Corporation Empirically based dynamic control of acceptance of victim cache lateral castouts
US8117390B2 (en) * 2009-04-15 2012-02-14 International Business Machines Corporation Updating partial cache lines in a data processing system
US8176254B2 (en) * 2009-04-16 2012-05-08 International Business Machines Corporation Specifying an access hint for prefetching limited use data in a cache hierarchy
US8140759B2 (en) * 2009-04-16 2012-03-20 International Business Machines Corporation Specifying an access hint for prefetching partial cache block data in a cache hierarchy
US20110010522A1 (en) * 2009-06-12 2011-01-13 Cray Inc. Multiprocessor communication protocol bridge between scalar and vector compute nodes
US8306042B1 (en) * 2009-06-19 2012-11-06 Google Inc. Class-based deterministic packet routing
JP5493575B2 (en) * 2009-08-10 2014-05-14 富士通株式会社 Information processing apparatus and information processing apparatus control method
US8539130B2 (en) * 2009-09-24 2013-09-17 Nvidia Corporation Virtual channels for effective packet transfer
US8446824B2 (en) * 2009-12-17 2013-05-21 Intel Corporation NUMA-aware scaling for network devices
US9189403B2 (en) * 2009-12-30 2015-11-17 International Business Machines Corporation Selective cache-to-cache lateral castouts
CN102273150B (en) * 2010-03-29 2013-09-25 华为技术有限公司 Cluster router and cluster routing method
EP2564322A4 (en) * 2010-04-30 2017-03-08 Hewlett-Packard Enterprise Development LP Management data transfer between processors
US8381014B2 (en) * 2010-05-06 2013-02-19 International Business Machines Corporation Node controller first failure error management for a distributed system
US9552206B2 (en) * 2010-11-18 2017-01-24 Texas Instruments Incorporated Integrated circuit with control node circuitry and processing circuitry
US8949453B2 (en) 2010-11-30 2015-02-03 International Business Machines Corporation Data communications in a parallel active messaging interface of a parallel computer
JP5603507B2 (en) 2010-12-29 2014-10-08 エンパイア テクノロジー ディベロップメント エルエルシー Accelerating cache state migration on directory-based multi-core architectures
CN102141975B (en) * 2011-04-01 2013-10-09 华为技术有限公司 Computer system
WO2013106032A2 (en) * 2011-04-08 2013-07-18 Altera Corporation Systems and methods for using memory commands
KR101873526B1 (en) * 2011-06-09 2018-07-02 삼성전자주식회사 On-chip data scrubbing method and apparatus with ECC
US8949328B2 (en) 2011-07-13 2015-02-03 International Business Machines Corporation Performing collective operations in a distributed processing system
US9176913B2 (en) * 2011-09-07 2015-11-03 Apple Inc. Coherence switch for I/O traffic
US8930962B2 (en) 2012-02-22 2015-01-06 International Business Machines Corporation Processing unexpected messages at a compute node of a parallel computer
JP2013196167A (en) * 2012-03-16 2013-09-30 Toshiba Corp Information processor
JP5949312B2 (en) * 2012-08-16 2016-07-06 富士通株式会社 Parallel computer system, data transfer apparatus, and parallel computer system control method
US8867559B2 (en) * 2012-09-27 2014-10-21 Intel Corporation Managing starvation and congestion in a two-dimensional network having flow control
KR101772037B1 (en) 2012-10-22 2017-08-28 인텔 코포레이션 High performance interconnect physical layer
US9280507B2 (en) 2012-10-22 2016-03-08 Intel Corporation High performance interconnect physical layer
US9160607B1 (en) * 2012-11-09 2015-10-13 Cray Inc. Method and apparatus for deadlock avoidance
CN103049422B (en) * 2012-12-17 2013-11-27 浪潮电子信息产业股份有限公司 Method for building multi-processor node system with multiple cache consistency domains
US9250679B2 (en) * 2013-03-08 2016-02-02 Intel Corporation Reduced wake up delay for on-die routers
US9229894B2 (en) * 2013-04-09 2016-01-05 Apple Inc. Protocol conversion involving multiple virtual channels
WO2014186938A1 (en) * 2013-05-20 2014-11-27 华为技术有限公司 Computer system, access method and apparatus for peripheral component interconnect express endpoint devices
US9600191B2 (en) * 2014-06-02 2017-03-21 Micron Technology, Inc. Systems and methods for reordering packet transmissions in a scalable memory system protocol
US9720838B2 (en) 2015-03-27 2017-08-01 Intel Corporation Shared buffered memory routing
WO2016178717A1 (en) * 2015-05-07 2016-11-10 Intel Corporation Bus-device-function address space mapping
CN105068786B (en) * 2015-07-30 2018-03-23 浪潮(北京)电子信息产业有限公司 A kind of method and Node Controller for handling access request
CN106603355B (en) 2015-10-15 2019-10-18 华为技术有限公司 A kind of computing device, node device and server
US9992135B2 (en) * 2015-12-11 2018-06-05 Intel Corporation Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces
KR102025801B1 (en) * 2016-01-26 2019-09-26 한국전자통신연구원 Distributed file system and method for protecting data thereof
WO2017175549A1 (en) * 2016-04-08 2017-10-12 株式会社清水 Slow-release fertilizer composition and soil
US10291512B2 (en) * 2016-09-13 2019-05-14 Cisco Technology, Inc. Interest message path steering and multi-path traceroute in information-centric networking
NO342930B1 (en) 2016-10-18 2018-09-03 Numascale As Cache Coherent node controller
KR102610984B1 (en) * 2017-01-26 2023-12-08 한국전자통신연구원 Distributed file system using torus network and method for operating of the distributed file system using torus network
US10459659B2 (en) * 2017-03-31 2019-10-29 Intel Corporation Technologies for issuing commands on selected memory devices
NO343359B1 (en) 2017-05-02 2019-02-11 Numascale As Interconnect switch in multiprocessor systems
US11287985B2 (en) 2017-05-17 2022-03-29 Seagate Technology Llc Network data storage buffer system
CN111917656B (en) * 2017-07-27 2023-11-07 超聚变数字技术有限公司 Method and device for transmitting data
EP3662474B1 (en) 2017-07-30 2023-02-22 NeuroBlade Ltd. A memory-based distributed processor architecture
US20190065418A1 (en) * 2017-08-29 2019-02-28 International Business Machines Corporation Message routing in a main memory arrangement
US10474611B2 (en) * 2017-09-19 2019-11-12 International Business Machines Corporation Aligning received bad data indicators (BDIS) with received data on a cross-chip link
US10592465B2 (en) 2017-10-26 2020-03-17 Hewlett Packard Enterprise Development Lp Node controller direct socket group memory access
US11275632B2 (en) 2018-09-14 2022-03-15 Advanced Micro Devices, Inc. Broadcast command and response
CN110677278A (en) * 2019-09-10 2020-01-10 无锡江南计算技术研究所 Message processor
CN113010173A (en) 2019-12-19 2021-06-22 超威半导体(上海)有限公司 Method for matrix data broadcasting in parallel processing
CN113094099A (en) 2019-12-23 2021-07-09 超威半导体(上海)有限公司 Matrix data broadcast architecture
KR20210089804A (en) 2020-01-08 2021-07-19 삼성전자주식회사 Memory module and memory system including the same
JP2022049552A (en) * 2020-09-16 2022-03-29 キオクシア株式会社 Semiconductor device and method
US11403221B2 (en) 2020-09-24 2022-08-02 Advanced Micro Devices, Inc. Memory access response merging in a memory hierarchy
WO2022212415A1 (en) * 2021-03-29 2022-10-06 Google Llc On-chip interconnect for memory channel controllers
US11853231B2 (en) 2021-06-24 2023-12-26 Ati Technologies Ulc Transmission of address translation type packets

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864738A (en) * 1996-03-13 1999-01-26 Cray Research, Inc. Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
US5878241A (en) * 1990-11-13 1999-03-02 International Business Machine Partitioning of processing elements in a SIMD/MIMD array processor
WO1999026429A2 (en) * 1997-11-17 1999-05-27 Cray Research, Inc. Hybrid hypercube/torus architecture

Family Cites Families (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330858A (en) 1979-06-29 1982-05-18 International Business Machines Corporation Time domain supervisory channel for data terminal equipments
US4814979A (en) 1981-04-01 1989-03-21 Teradata Corporation Network to transmit prioritized subtask pockets to dedicated processors
US4814973A (en) 1983-05-31 1989-03-21 Hillis W Daniel Parallel processor
JP2644718B2 (en) 1983-12-28 1997-08-25 株式会社日立製作所 Computer system
US4754394A (en) 1984-10-24 1988-06-28 International Business Machines Corporation Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage
US4630259A (en) 1984-11-14 1986-12-16 At&T Bell Laboratories Lockup detection and recovery in a packet switching network
US4807183A (en) * 1985-09-27 1989-02-21 Carnegie-Mellon University Programmable interconnection chip for computer system functional modules
US4771391A (en) 1986-07-21 1988-09-13 International Business Machines Corporation Adaptive packet length traffic control in a local area network
US4811214A (en) 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US4933933A (en) 1986-12-19 1990-06-12 The California Institute Of Technology Torus routing chip
US5093920A (en) * 1987-06-25 1992-03-03 At&T Bell Laboratories Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
US5170482A (en) 1987-08-14 1992-12-08 Regents Of The University Of Minnesota Improved hypercube topology for multiprocessor computer systems
US5008882A (en) 1987-08-17 1991-04-16 California Institute Of Technology Method and apparatus for eliminating unsuccessful tries in a search tree
US4868818A (en) 1987-10-29 1989-09-19 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Fault tolerant hypercube computer system architecture
US5105424A (en) 1988-06-02 1992-04-14 California Institute Of Technology Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network
DE68927946T2 (en) 1988-08-02 1997-10-16 Philips Electronics Nv Method and device for synchronizing parallel processors using an unsharp lock
EP0364638B1 (en) 1988-10-20 1994-04-20 International Business Machines Corporation Communication network
US5117350A (en) 1988-12-15 1992-05-26 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
US5347450A (en) 1989-01-18 1994-09-13 Intel Corporation Message routing in a multiprocessor computer system
JP2749098B2 (en) 1989-02-03 1998-05-13 株式会社日立製作所 Communication line switching / combination method
US5036459A (en) 1989-03-09 1991-07-30 U.S. Philips Corporation Multi-processor computer system with distributed memory and an interprocessor communication mechanism, and method for operating such mechanism
JP3072646B2 (en) 1989-03-20 2000-07-31 富士通株式会社 Communication control method between parallel computers
US5127092A (en) 1989-06-15 1992-06-30 North American Philips Corp. Apparatus and method for collective branching in a multiple instruction stream multiprocessor where any of the parallel processors is scheduled to evaluate the branching condition
US5166156A (en) * 1989-12-20 1992-11-24 Adir Et Compagnie Naphthyl piperazines useful as 5-HT1A receptor ligands
CA2032620C (en) 1989-12-22 1995-08-15 Takafumi Chujo Method for searching for alternate path in communication network
US5197130A (en) 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5280474A (en) 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
US5218676A (en) 1990-01-08 1993-06-08 The University Of Rochester Dynamic routing system for a multinode communications network
US5161156A (en) 1990-02-02 1992-11-03 International Business Machines Corporation Multiprocessing packet switching connection system having provision for error correction and recovery
US5210705A (en) 1990-02-28 1993-05-11 Texas Instruments Incorporated Digital filtering with single-instruction, multiple-data processor
US5201044A (en) 1990-04-16 1993-04-06 International Business Machines Corporation Data processing method for file status recovery includes providing a log file of atomic transactions that may span both volatile and non volatile memory
US5083265A (en) 1990-04-17 1992-01-21 President And Fellows Of Harvard College Bulk-synchronous parallel computer
US5229990A (en) 1990-10-03 1993-07-20 At&T Bell Laboratories N+K sparing in a telecommunications switching environment
US5794059A (en) * 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5963746A (en) * 1990-11-13 1999-10-05 International Business Machines Corporation Fully distributed processing memory element
US5383191A (en) 1990-12-20 1995-01-17 International Business Machines Corporation Dual ring reconfiguration switching unit
US5175733A (en) 1990-12-27 1992-12-29 Intel Corporation Adaptive message routing for multi-dimensional networks
US5365228A (en) 1991-03-29 1994-11-15 International Business Machines Corporation SYNC-NET- a barrier synchronization apparatus for multi-stage networks
US5265232A (en) 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
US5251131A (en) * 1991-07-31 1993-10-05 Thinking Machines Corporation Classification of data records by comparison of records to a training database using probability weights
JP2836321B2 (en) 1991-11-05 1998-12-14 三菱電機株式会社 Data processing device
EP0562251A2 (en) 1992-03-24 1993-09-29 Universities Research Association, Inc. Parallel data transfer network controlled by a dynamically reconfigurable serial network
DE69329904T2 (en) 1992-03-25 2001-06-13 Sun Microsystems Inc REAL-TIME PROCESSING SYSTEM
EP0570729A3 (en) 1992-05-22 1994-07-20 Ibm Apap i/o programmable router
US5533198A (en) 1992-11-30 1996-07-02 Cray Research, Inc. Direction order priority routing of packets between nodes in a networked system
US5838894A (en) 1992-12-17 1998-11-17 Tandem Computers Incorporated Logical, fail-functional, dual central processor units formed from three processor units
JPH06318951A (en) 1993-01-07 1994-11-15 Toshiba Corp Method and system for transferring cell
US5598568A (en) * 1993-05-06 1997-01-28 Mercury Computer Systems, Inc. Multicomputer memory access architecture
FR2707819B1 (en) 1993-07-12 1995-09-15 Tremel Jean Yves Method and device for monitoring and / or testing an ATM type telecommunications network.
US5546596A (en) 1993-08-24 1996-08-13 Intel Corporation Method and apparatus for integrated local and express routing in a multiprocessor
US5509125A (en) 1993-09-29 1996-04-16 Silicon Graphics, Inc. System and method for fair arbitration on a multi-domain multiprocessor bus
US5504874A (en) 1993-09-29 1996-04-02 Silicon Graphics, Inc. System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
US5390164A (en) 1993-10-22 1995-02-14 At&T Corp. Ring interworking between bidirectional line-switched ring transmission systems
US5434995A (en) 1993-12-10 1995-07-18 Cray Research, Inc. Barrier synchronization for distributed memory massively parallel processing systems
US5583990A (en) 1993-12-10 1996-12-10 Cray Research, Inc. System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel
US5453978A (en) 1994-04-04 1995-09-26 International Business Machines Corporation Technique for accomplishing deadlock free routing through a multi-stage cross-point packet switch
US5634004A (en) * 1994-05-16 1997-05-27 Network Programs, Inc. Directly programmable distribution element
US5546549A (en) 1994-06-01 1996-08-13 International Business Machines Corporation Multi-path channel (MPC) interface with user transparent, unbalanced, dynamically alterable computer input/output channels
US5592610A (en) 1994-12-21 1997-01-07 Intel Corporation Method and apparatus for enhancing the fault-tolerance of a network
US5659796A (en) 1995-04-13 1997-08-19 Cray Research, Inc. System for randomly modifying virtual channel allocation and accepting the random modification based on the cost function
US5701416A (en) 1995-04-13 1997-12-23 Cray Research, Inc. Adaptive routing mechanism for torus interconnection network
US5721819A (en) 1995-05-05 1998-02-24 Silicon Graphics Corporation Programmable, distributed network routing
US5669008A (en) 1995-05-05 1997-09-16 Silicon Graphics, Inc. Hierarchical fat hypercube architecture for parallel processing systems
US5682479A (en) 1995-05-05 1997-10-28 Silicon Graphics, Inc. System and method for network exploration and access
US5680576A (en) 1995-05-05 1997-10-21 Silicon Graphics, Inc. Directory-based coherence protocol allowing efficient dropping of clean-exclusive data
US5634110A (en) 1995-05-05 1997-05-27 Silicon Graphics, Inc. Cache coherency using flexible directory bit vectors
US5721921A (en) 1995-05-25 1998-02-24 Cray Research, Inc. Barrier and eureka synchronization architecture for multiprocessors
US5613071A (en) 1995-07-14 1997-03-18 Intel Corporation Method and apparatus for providing remote memory access in a distributed memory multiprocessor system
US5956342A (en) * 1995-07-19 1999-09-21 Fujitsu Network Communications, Inc. Priority arbitration for point-to-point and multipoint transmission
US5778437A (en) 1995-09-25 1998-07-07 International Business Machines Corporation Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory
US5787241A (en) * 1995-12-18 1998-07-28 Integrated Device Technology, Inc. Method and apparatus for locating exception correction routines
US5970510A (en) * 1996-04-10 1999-10-19 Northrop Grumman Corporation Distributed memory addressing system
US5793962A (en) 1996-04-30 1998-08-11 International Business Machines Corporation System for managing membership of a group of processors in a distributed computing environment
US5787477A (en) 1996-06-18 1998-07-28 International Business Machines Corporation Multi-processor cache coherency protocol allowing asynchronous modification of cache data
US5752258A (en) 1996-07-01 1998-05-12 Sun Microsystems, Inc. Encoding method for directory state in cache coherent distributed shared memory system
US5900015A (en) 1996-08-09 1999-05-04 International Business Machines Corporation System and method for maintaining cache coherency using path directories
US6625166B2 (en) * 1996-11-15 2003-09-23 Canon Kabushiki Kaisha Communication system for communicating a plurality of time-division multiplexed data, and control method therefor
US5915104A (en) 1997-01-09 1999-06-22 Silicon Graphics, Inc. High bandwidth PCI to packet switched router bridge having minimized memory latency
US5995512A (en) * 1997-01-17 1999-11-30 Delco Electronics Corporation High speed multimedia data network
US5978578A (en) * 1997-01-30 1999-11-02 Azarya; Arnon Openbus system for control automation networks
US6101181A (en) 1997-11-17 2000-08-08 Cray Research Inc. Virtual channel assignment in large torus systems
US6085303A (en) * 1997-11-17 2000-07-04 Cray Research, Inc. Seralized race-free virtual barrier network
US5970232A (en) * 1997-11-17 1999-10-19 Cray Research, Inc. Router table lookup mechanism
US6633958B1 (en) * 1997-11-17 2003-10-14 Silicon Graphics, Inc. Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure
US6072772A (en) * 1998-01-12 2000-06-06 Cabletron Systems, Inc. Method for providing bandwidth and delay guarantees in a crossbar switch with speedup
US6334159B1 (en) * 1998-12-22 2001-12-25 Unisys Corporation Method and apparatus for scheduling requests within a data processing system
US6110181A (en) * 1999-02-10 2000-08-29 Veterans General Hospital-Taipei, Vacrs Thread carrier plate device and method
US6484220B1 (en) * 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
US6725307B1 (en) * 1999-09-23 2004-04-20 International Business Machines Corporation Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
US6711636B1 (en) * 1999-09-29 2004-03-23 Silicon Graphics, Inc. Transfer attribute encoding within an address on a bus
US6674720B1 (en) * 1999-09-29 2004-01-06 Silicon Graphics, Inc. Age-based network arbitration system and method
US6516372B1 (en) * 1999-09-29 2003-02-04 Silicon Graphics, Inc. Partitioning a distributed shared memory multiprocessor computer to facilitate selective hardware maintenance
US6604161B1 (en) * 1999-09-29 2003-08-05 Silicon Graphics, Inc. Translation of PCI level interrupts into packet based messages for edge event drive microprocessors
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6546451B1 (en) * 1999-09-30 2003-04-08 Silicon Graphics, Inc. Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
US6564277B1 (en) * 1999-09-30 2003-05-13 Silicon Graphics, Inc. Method and system for handling interrupts in a node controller without attached processors
US6339812B1 (en) * 1999-09-30 2002-01-15 Silicon Graphics, Inc. Method and apparatus for handling invalidation requests to processors not present in a computer system
US6457146B1 (en) * 1999-09-30 2002-09-24 Silicon Graphics, Inc. Method and apparatus for processing errors in a computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878241A (en) * 1990-11-13 1999-03-02 International Business Machine Partitioning of processing elements in a SIMD/MIMD array processor
US5864738A (en) * 1996-03-13 1999-01-26 Cray Research, Inc. Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
WO1999026429A2 (en) * 1997-11-17 1999-05-27 Cray Research, Inc. Hybrid hypercube/torus architecture

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