WO2001027728A1

WO2001027728A1 - Minimizing power consumption during sleep modes by using minimum core voltage necessary to maintain system state

Info

Publication number: WO2001027728A1
Application number: PCT/US2000/011062
Authority: WO
Inventors: Qadeer Ahmad Qureshi; Charles Weldon Mitchell; Dervinn Deyual Caldwell; Gary Baum; Kyle Odiorne
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1999-10-14
Filing date: 2000-04-25
Publication date: 2001-04-19

Abstract

A control circuit reduces voltage being supplied to an integrated circuit in a sleep mode in which context (e.g. CPU state) is maintained. Because the voltage required to maintain the integrated circuit state intact may be significantly less than the voltage at which the integrated circuit can functionally operate at a predetermined frequency, significant power savings can be achieved by reducing voltage while the clocks are stopped, thereby reducing leakage current and saving power.

Description

MINIMIZING POWER CONSUMPTION DURING SLEEP MODES BY USING MINIMUM CORE VOLTAGE NECESSARY TO MAINTAIN SYSTEM STATE

Technical Field

This invention relates to power consumption m mtegrated circuits and more specifically to reducing power consumption on an integrated circuit while clocks are stopped

Background Art

A conventional notebook computer has power constraints that cause it to employ techniques to reduce power consumption to conserve battery life In addition, the conventional notebook computer has thermal constraints due to a small, densely packed system construction that limits its ability to safely dissipate the heat generated by computer operation The power savmgs techmques also beneficially reduce the amount of heat needed to be dissipated.

The frequency of operation (clock frequency) of the processor and its operatmg voltage are primary determinants of power consumption Smce power consumption and dissipation are roughly proportional to the processor's frequency of operation, scaling down the processor's frequency has been a common method of staying within notebook computer power and thermal limitations

A common power management technique, called "throttling", temporarily stops processor clocks, to reduce power consumption and thus reduce heat generation. Throttling continuously stops and starts processor operation by turning its clocks off and on according to a predefined duty cycle with a peπod of a few milliseconds. The reduction in the effective speed of the processor reduces power dissipation and thus the processor's temperature. A clock control signal (e.g., STPCLK# in x86 architectures) modulates the duty cycle of processor operation. The clock control signal, when asserted, causes the processor to gate off the clocks bemg supplied to core logic in the processor. In some current processor designs, e.g , x86 processors, a Stop Grant cycle on a host or system bus is executed to mdicate that the stop clock request on the asserted clock control signal has been completed. A temperature sensor placed on or near the processor's heat sink can initiate throttling when needed.

In addition, when operating from its battery, most notebooks take advantage of the processor's idle penods by periodically stopping processor operation to reduce power consumption. Applications like word processors typically leave the processor idle much of the time. For example, in a word processmg application, a processor will do a brief burst of work after each letter is typed, then its operation is stopped until the next keystroke. As a result, the typical processor power consumption when running a word processmg application, can be as much as 30-50% below the maximum. That idle time can be exploited by the computer system to achieve additional power savmgs by putting the processor to sleep temporarily.

Current x86 based computer systems utilize an industry supported power management approach described m the Advanced Configuration and Power Interface Specification (ACPI), Revision 1.0a, by Intel, Microsoft and Toshiba dated November 19, 1998, which is mcorporated herem by reference The ACPI is an operating system (OS) controlled power management scheme that uses features built into the Wmdows 95, 98 and Windows NT or other compatible operatmg systems It defines a standard interrupt (System Control Interrupt or SCI) that handles all ACPI events System control interrupts are generated by devices to inform the OS about system events

As part of that power management approach, ACPI specifies sleep and suspend states Sleep states temporarily halt processor operation and operation can be restored m a few milliseconds A computer system processor enters the sleep state when internal activity monitors indicate no processmg is taking place When a keystroke is entered, a mouse moves or data is received via a modem, the processor wakes up in order to resume operation, the clocks are turned on and the CPU continues executing from where it left off

Other modes save processor context external to the processor such as to system memory or even to hard disk Suspend states shut down more of the notebook's system (e g display or hard drive) and take a few seconds for operation to be restored Suspend states copy the present context of the system (sufficient for the computer to resume processmg the applιcatιon(s) presently opened) into memory (suspend to RAM) or to the hard drive (suspend to disk) and power down peripherals Obviously m these other modes, longer latency is incurred to resume normal system operation

When computer systems stop the central processmg unit (CPU) clocks duπng a sleep mode or durmg throttling, a short latency for resuming processor operation is desirable One way to achieve that short latency is to ensure that CPU context is not lost That means that the various latches and other circuit nodes m the CPU that hold information required (e g , the state of processor registers) for the processor to resume operations where it left off, are mamtamed m the CPU while clocks are stopped Mamtammg processor context requires that the CPU receive power even though the clocks are stopped

Note that processors typically have separate regions of the chip that receive separate power supply voltages For example, such regions may mclude a core region, as well as a peripheral region where input/output (I/O) circuits are located The peripheral region often remams powered up even if the core voltage is turned off Therefore, core voltage which must be mamtamed to ensure processor context is mamtamed (assuming I/O voltage is also on) In most current notebook designs, CPU core voltage is typically set duπng initialization, and is not changed after that

When power is supplied duπng the sleep state to maintain CPU context, the CPU still consumes power because of leakage current The leakage current is generally proportional to the core voltage, and the power consumption is proportional to the square of the core voltage The leakage current can be significant enough to drain the battery For example, an AMD-K-6®-2 processor can consume several hundred milliwatts while in sleep mode Additionally, some circuit designs may be more leaky than others, resulting in even more power bemg consumed m sleep mode

It is desirable to reduce power consumption in computers, particularly m portable computers where maximizing battery life and reducmg heat generation by reducmg power consumption is particularly advantageous Therefore it would be desirable to reduce power consumption, if possible, when clocks are stopped and power is bemg consumed due to leakage cuπent

DISCLOSURE OF INVENTION

Accordingly, the mvention provides a way to save power while a processor (or other mtegrated circuit) is m a sleep mode m which context is mamtamed Because the voltage required to mamtam the mtegrated circuit context (e g processor state) mtact may be significantly less than the voltage at which the processor can functionally operate at a particular frequency, significant power savings can be achieved by reducing processor voltage while the processor clocks are stopped

In one embodiment, the mvention provides a method of supplymg a first voltage to at least a first circuit portion of an mtegrated circuit during an operational mode The method further mcludes stoppmg clocks which are being supplied to the first circuit portion to place the mtegrated circuit in a reduced power consumption state and then supplymg a second voltage, less than the first voltage, to the first circuit portion while the clocks are stopped, the second voltage bemg at a voltage sufficient to mamtam context of the first circuit portion m existence at a time when the clocks were stopped

In another embodiment, the mvention provides an apparatus that mcludes an mtegrated circuit that has a plurality of circuits holdmg, at least in substantial part, context mdicative of a current operational state of the mtegrated circuit A power supply circuit supplies variable voltages to the mtegrated circuit A control circuit is coupled to the power supply circuit, and supplies the power supply circuit with first voltage control information, indicating a first voltage to be supplied, while clocks are bemg supplied to the plurality of circuits The control circuit supplies the power supply circuit with second voltage control information, indicating a second voltage to be supplied, while the clocks are stopped, the second voltage bemg lower than the first voltage

BRIEF DESCRIPTION OF DRAWINGS

The present mvention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled m the art by referencmg the accompanying drawmgs, wherem

Fig 1 illustrates an exemplary system that can exploit the present invention,

Fig 2 illustrates additional details over a control circuit used in one embodiment of the present mvention, and

Fig 3 is a flow chart of an embodiment of the present mvention

MODE(S) FOR CARRYING OUT THE INVENTION

Additional power savmgs can be realized in computer systems by reducmg the voltage supplied to the processor during a state m which processor clocks are stopped and processor context is mamtamed With the clocks off, the voltage level requured to maintain processor context can be reduced to levels below that needed for proper operation of the clocked circuits Put another way, the voltage required to mamtam state, is lower than that needed to change state reliably

In an exemplary embodiment illustrated in Fig 1, voltage regulator 101 supplies core voltage 102 to processor (CPU) 103 In the embodiment illustrated, integrated circuit 105 controls the voltage level that is supplied to CPU 103 by supplymg voltage control signals VID[0 4] to voltage regulator 101 VID refers to "voltage ID" which is commonly used in the industry to describe the voltage control signals Integrated circuit 105 may be a south bridge mtegrated circuit, which is known m the art as one chip of a chipset pair The south bridge, originally providing a bridge between the Peripheral Component Interconnect (PCI) bus and the ISA bus, also typically mcorporates power management functions The south bridge may also contain mtegrated legacy functions, as well as interfaces for newer buses such as Universal Serial Bus (USB) and other additional functions The chipset pair also typically includes a north bπdge mtegrated circuit (not shown) that provides a memory control function as well as a bridge function between the host bus connected to the processor and the Peripheral Component Interconnect (PCI) bus Clock generator 107 supplies a clock signal 106 used by CPU 103 to generate clocks supplied to core logic m the processor Clock generator 107 can be controlled by clock stop signal 112 to selectably turn on and off clocks supplied to CPU 103 and other system components

The variable voltage regulator 101 may be, e g , the National Semiconductor's LM4130, whose output voltage can be controlled by an external device such as south bridge 105 It is desirable for the voltage regulator to support at least four control bits and for the output voltage to be controllable m steps of 50mV (or smaller) covermg a minimum range of from 1 45 to 2 2 volts A wider range or different granularity may be desirable in some applications

The CPU clocks can be stopped as follows The "stop clock" signal refers to STPCLK# signal 110 (where # indicates an active low signal), which causes CPU 103 to stop execution at the end of the current instruction, and turn off internal distribution of the CPU's clock, to most, if not all sections of processor core logic The CPU executes a "Stop Grant" bus cycle to indicate that the CPU has entered the Stop Grant state

In addition to stoppmg distribution internally, clocks to the CPU and other components may be stopped usmg the "clock stop" signal 112 provided by south bπdge 105 to clock generator 107 One typical sequence to stop the clocks is to assert the STPCLK# signal 110 to enter the Stop Grant state, wait for the Stop Grant bus cycle and then turn off the clock generator 107 distπbution of clocks using the clock stop signal 112 to enter the Stop Clock state

Assume that the clocks to the processor are stopped as described above The particular mechanism to stop clocks may vary in different embodiments and is not cπtical to the present mvention The clocks may be stopped in association with throttling or because of the processor entermg a sleep mode or any other scenario in which clocks are stopped and power is left on After the clocks are stopped, the south bπdge 105 (or any other suitable logic device) supplies new voltage control signals to the CPU core voltage regulator 101 instructing the voltage regulator to supply a reduced voltage to the CPU core Dependmg on the sleep mode, it may still be important that the voltages supplied to other areas of the CPU, such as the I/O circuits are mamtamed at suitable levels since such circuits may be interfacing with I/O devices, external circuits or buses that may be active when the processor has its core logic clocks stopped

Because sleep and throttle (and suspend) states require the processor operation to be stopped, it is impossible for system software to control all sleep, and recover operations To overcome this problem, control logic is typically implemented external to the processor For example, such control logic may be implemented m the input/output mtegrated circuit (referred to herem as south bridge 105) to control the final stages of sleep and suspend operations and the resume operation and other common power management features One such mtegrated circuit is the Intel Corp 82371 AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) The power management features contamed therein reduce power consumption to extend battery life and control heat generation and dissipation to safely operate the processor While some computer systems use a separate microcontroller for the task, most computer systems, including most notebook computers rely on the south bπdge to provide the hardware needed for controlling thermal and power management South bπdge chips from various manufacturers have typically utilized the registers, timers and state machme definitions used in the Intel PIIX4 South Bπdge. PIIX4 compatibility m cuπent south bπdge chips can be extended to support managmg the core voltage during sleep states as described herem

The control logic to reduce the core voltage after the clocks are turned off may be implemented as a state machme in south bridge 105. It may be particularly advantageous to augment or modify existing power management control logic m the south bridge to provide the enhanced functionality descπbed herem Once the voltage to the core has been reduced, the control logic waits for a system event that causes the CPU to resume processmg In the meantime the processor is m a quiescent state with the current consumption lower than it otherwise would have been The system event causmg the processor to wake-up, such as mouse movement or depressmg a keyboard key, causes the CPU to resume normal operations The control logic ensures that the core voltage is returned back to an operational level sufficient to support the desired clock frequency pπor to the clocks bemg turned on Otherwise, unpredictable results may be caused by clocking circuits when the power supply voltage is too low. Thus, the control logic issues new voltage control settings to voltage regulator 101 corresponding to a desired frequency and then the clocks are turned back on by, e.g., enablmg clocks at clock generator 107, if necessary, and deasserting STPCLK#

For a particular processor, the minimum operatmg core voltage (V_coremm), which specifies the minimum operatmg voltage required and the minimum static core voltage (V_coremms), which specifies the voltage necessary to mamtam context with clocks stopped, can be specified over the entire product line In one embodiment, the voltage control signal (VID) settings coπesponding to V_coremιn and V_coremms may be built mto BIOS tables When the system management software determines that the system needs to be put mto a mode where clocks are stopped (e g., a sleep mode or a throttle clock state), the core voltage is reduced to V_coremms after the clock has been stopped Note that if clocks are stopped externally, it may also be possible to reduce the voltage bemg supplied to I/O regions of the processor under some circumstances When the system needs to be restored to operatmg conditions, the system automatically increases the core voltage to the setting needed for the CPU operation at the desired frequency using the VID settings in the BIOS tables The control settings may of course be located m any suitable location m the computer system

Power savmgs will vary accordmg to the leakage current present in the particular mtegrated circuit For example, a processor consuming hundreds milliwatts of power while clocks are stopped in the Stop Grant state (on chip clock multiplier logic is still active) might reduce leakage cuπent by lowering the power supply voltage enough to reduce power consumption by approximately 10%

The voltage regulator's control pms should be configured for appropriate default operation upon power-up Accordmgly, as shown m Fig 1 , south bridge 105 m one embodiment, has jumper inputs IV[4 0] The settings of the jumpers 111 (open or short), along with resistors 113, determine the default values for the VID signals The IBF[2 0] mputs are for frequency control and a descπption of their use is not critical to understand the present mvention In addition to default modes, the south bridge 105 (or other suitable circuit) supplies the voltage regulator 101 with appropriate voltage control settings during operational modes and durmg sleep modes m which processor context is mamtamed

Referring to Fig 2, a high level block diagram shows one approach an mtegrated circuit (such as the south bπdge m cuπent x86 based computer systems) may use to provide appropriate voltage control settings for voltage regulator 101 (Fig 1) In the embodiment illustrated m Fig 2, multiplexer 201 receives three voltage controls settings as mputs The first voltage control setting is from VID jumper settings 111, which as previously descπbed, provide for default voltage settings on power-up Multiplexer 201 also receives mputs from VID stop clock register 202, which provides the voltage control setting for the reduced processor voltage duπng stop clock modes (V_coremιns) Multiplexer 201 receives mputs from VID operational register 203, which provides VID values for operational modes of the processor, l e , when core clocks are running Multiplexer 201 selects between the vaπous voltage control settings accordmg to a select lme 204 supplied by control logic 210 Control logic 210 receives reset signal 207 and selects the jumper settings as the appropriate voltage control settings when reset (power on or other hard or soft reset) is asserted Control logic 210 also receives a stop clock signal 208 which mdicates that the processor has or is about to enter a stop clock state with core power mamtamed In addition, control logic 210 receives indication 209 that a wakeup event has occuπed, l e , that the processor is gomg to resume normal operation

The control logic also supplies load signal 211 to output register 205 Duπng regular operational modes in which clocks are running, multiplexer 201 selects the operational VID register 203 Note that register 203 may be programmable to provide various VID signals durmg vaπous operational modes When the processor is m a sleep or throttle mode m which clocks are stopped, the control logic selects the VID stop clock register settings as the source for the voltage control signals VID Thus, after the clocks are stopped (or simultaneously therewith), the select lme selects the VID values from the stop clock VD register 202 The control logic then waits for a wake-up event to occur When the wake-up event occurs as mdicated by wake up signal 209 and before the clocks are started, the control logic causes the operational voltage control signals coπesponding to the desired frequency of operation to be loaded mto output register 205 from VTD operational register 203 The clocks may then be enabled A variety of other circuit implementations would be readily apparent to one of skill in the art to accomplish the function of the circuit illustrated m Fig 2 For example, the multiplexer may only select between jumper settmgs and a VID register with the VID register bemg appropriately updated before values in the register are supplied to the voltage regulator 100 That is, south bridge 105 can utilize a programmable register that can be written to update the VID pins with the appropπate voltage control settmgs available from, e.g , the BIOS tables rather than have separate operational and stop clock registers

Referring to Fig. 3, a flow chart illustrates the operation of a system incorporating one embodiment for controlling core voltage to effectuate greater power savmgs accordmg to the present invention Assume that the clocks are stopped m 301. The clocks may be stopped usmg the STPCLK# signal 110 or usmg clock stop signal 112 to turn off the clock signal 106 bemg supplied to the processor clock multiplier logic, or both, or m any other manner appropriate for the particular implementation After the clocks are stopped, the system reduces the core voltage bemg supplied to processor core logic in 303 That is accomplished, e g , by selectmg the appropriate voltage control settmgs and supplymg those settmgs to the CPU core voltage regulator Once the processor is mamtammg its context with the reduced core voltage, and thereby realizing greater power savmgs, the control logic waits for a wake-up event in 305 Once the wake-up event occurs, the core logic voltage is changed to a level corresponding to the desned frequency of operation m 307 and then, after the processor is receivmg the higher voltage, the clocks are turned on and the processor resumes normal operation

The description of the mvention set forth herein is illustrative, and is not mtended to limit the scope of the mvention as set forth m the folio wmg claims. For mstance, while this mvention has been descπbed with relation generally to x86 based computer systems and is particularly relevant to notebook computers (which may also be referred to as laptops, portable or mobile computers), the teachmgs herem may also be utilized in any computmg device such as personal digital assistants (PDAs), as well as systems contammg any vaπety of processor m which it is desirable to save power by reducmg voltage while clocks are stopped m a power savmgs mode and still mamtam context Further, while the description herem has focused on reducmg core voltages in processors or CPUs, the power savmgs is equally applicable to any mtegrated cncuit m which clocks are stopped to save power while context is mamtamed Other vaπations and modifications of the embodiments disclosed herem, may be made based on the description set forth herem, without departing from the scope and spint of the mvention as set forth m the following claims

Claims

WHAT IS CLAIMED IS:

1 A method compπsmg supplymg a first voltage to at least a first circuit portion of an integrated circuit durmg an operational mode, stoppmg clocks which are bemg supplied to the first circuit portion to place the mtegrated cncuit m a reduced power consumption state, and then supplymg a second voltage, less than the first voltage, to the first circuit portion while the clocks are stopped, the second voltage bemg at a voltage level sufficient to mamtam context of the first cncuit portion in existence at a time when the clocks were stopped

2 The method as recited in claim 1 wherem the mtegrated cncuit is a microprocessor mcludmg core logic, the first cncuit portion bemg the core logic

3 The method as recited in claim 1 further compπsmg supplymg a thnd voltage to the mtegrated cncuit after supplymg the mtegrated cncuit with the second voltage, the thnd voltage bemg greater than the second voltage, and then starting the clocks being supplied to the first circuit portion to resume mtegrated cncuit operations

4 The method as recited m claim 3 wherem the first and third voltages are equal

5 The method as recited m claim 3 wherem the thnd voltage is supplied m response to a wake- up event

6 A computmg device compπsmg an mtegrated cncuit mcludmg a cncuit region holdmg, at least in substantial part, context mdicative of a current operational state of the mtegrated cncuit, a power supply cncuit responsive to control mputs to supply variable voltages to the mtegrated cncuit, a control cncuit coupled to the control mputs of the power supply cncuit, wherem the control cncuit supplies the control mputs with first voltage control information, indicating an operational voltage, while clocks are bemg supplied to the circuit region and the control cncuit supplies the control mputs with second voltage control information indicating a second voltage, while the clocks are stopped, the second voltage bemg lower than the operational voltage

7 The computmg device as recited m claim 6 wherem the operational voltage is at a voltage level requned to clock the cncuit region at a predetermmed frequency and the second voltage is below the voltage level requned to clock the circuit region at the predetermmed frequency

8. An integrated circuit compπsmg- a logic circuit responsive to an mdication of normal clock operation m which internal clocks are running, to selectably provide first voltage control information indicative of a first voltage level and responsive to an mdication of a stop clock state in which internal clocks are stopped to provide second voltage control mformation mdicative of a second voltage level, the second voltage level bemg lower than the first voltage level; and an output cncuit coupled to receive the selectably provided first and second voltage control mformation, the first and second voltage control information for couplmg to control mputs of a voltage generator.

9. The mtegrated cncuit as recited m claim 8 wherem the logic circuit includes a selector cncuit coupled to selectably provide to the output cncuit the first or second voltage control mformation as the control inputs of the voltage generator and further mcludes at least a first programmable register coupled to the selector cncuit and holdmg at least one of the first voltage control mformation and the second voltage control mformation

10 The mtegrated cncuit as recited m claim 9 further compπsmg control logic coupled to receive an mdication of a wake-up event, an mdication of a reset and an mdication of the clock stop state, and generatmg a select signal for the selector cncuit m response thereto.