WO2001029978A1

WO2001029978A1 - High linearity fm demod for a 4fsk wlan transceiver

Info

Publication number: WO2001029978A1
Application number: PCT/US2000/041418
Authority: WO
Inventors: Bernard C. Duggan; James R. Smillie
Original assignee: Maxim Integrated Products, Inc.
Priority date: 1999-10-20
Filing date: 2000-10-20
Publication date: 2001-04-26
Also published as: WO2001029981A1

Abstract

The present invention is a fully integrated FM demodulator (400) for 4FSK demodulation in a WLAN transceiver. The features and benefits of this invention include high gain and linearity, wide frequency range, and fully integrated FM demodulation requiring no external quad network. The center frequency and gain are accurately maintained by auto-tuning. The present invention is generally applicable to FM demodulators (400).

Description

HIGH LINEARITY FM DEMOD FOR A 4FSK WLAN TRANSCEIVER

FIELD OF INVENTION The present invention relates to modulation circuitry. More specifically, the present invention teaches an FM demodulator in which RLC circuit components have been replaced with gyrators allowing the use of integrated circuit (IC) technology.

DESCRIPTION OF RELATED ART The portable communications revolution is upon us today. It promises to empower individuals throughout the world by giving them low-cost access to information wherever they may be, thus allowing them to make informed decisions and to be more productive in business and at home, without necessarily being tied down to a physical location. Were it not for the advent of the portable communications revolution, radio technique would almost certainly become a lost art. Radio communication methods, at least for nonmilitary applications, have remained relatively unchanged since World War II, and the evolutionary improvements in consumer equipment mainly owes to the use of high-frequency discrete transistors, smaller passive components, and building block integrated circuits which improve the long term reliability and manufacturability of radio and television receivers. However, front-end radio architectures have evolved almost not at all. For example, integrated circuits have contributed digital volume-control, digital frequency tuning and features to alleviate manual effort on the part of the user, but the RF and IF sections still contain discrete and passive components in rather conventional architectures.

To set the stage for further discussion, some of the unique problems of radio receivers and transmitters must be described. Unlike familiar wire-line communications, the wireless environment accommodates essentially an unlimited number of users sharing different parts of the spectrum. As a consequence of this spectrum sharing, very strong signals often coexist next to very weak signals. The radio receiver must be able to select the signal of interest, while rejecting all others, and it must do so using less than perfect active and passive components.

One important problem in receiver design is how to provide a high gain, high linearity, accurate frequency tuned circuit, while still maintaining cost effectiveness. In addition to meeting cost constraints, smaller size requirements are now demanded by the industry.

As requirements for reduced receiver size increase, efforts to eliminate off-chip passive components grow. However, certain passive inductors, capacitors and resistors cannot be eliminated or scaled down. Thus, they conventionally remain off-chip. Prior art FIG. 1 is a block diagram of a prior art single quad demodulator transceiver, illustrated at 100. Included in this transceiver is a limiting circuit at 104, an external RLC filter at 106 coupled to a mixer circuit at 108, an external RLC band-pass filter at 110 and an output amplification stage at 112. As discussed above, the RLC filters at 106 and 110 conventionally are external to the transceiver

IC because of scaling difficulties with transceiver components. It is also well known that the classic single quad demodulator gives poor phase linearity in these types of applications. Quadrature modulation is modulation using two carriers out of phase by 90 degrees and modulated by separate signals. In FIG. 1, circuit 100 illustrates a prior art single quad demodulator wherein a signal input at 102 is sent through a limiter at 104, the output of which is electrically coupled to an RLC circuit at 106 and a mixer at 108. The RLC circuit consists of traditional components, resistor, capacitor and inductor. The output of the RLC circuit is also electrically coupled to the mixer at 108. The mixer output is electrically coupled to an amplifier at 112 via a band pass filter at 110. In FIG. 2, circuit 200 illustrates a prior art double RLC demodulator where a signal input at 202 is sent through a limiter at 204, the output of which is electrically coupled to a mixer at 206 and a series of RLC circuits at 216 and 214. The limiter output is electrically coupled to a first RLC circuit at 216, the output of which is electrically coupled to a second RLC circuit at 214. A drawback to the prior art shown in circuit 100 in FIG. 1 and circuit 200 in FIG. 2 is the use of RLC circuits in the feedback loop. The traditional components used in these RLC circuits are bulky and difficult to implement using integrated circuit (IC) technology. The present invention replaces the RLC circuits used in both FIG. 1 and FIG. 2, eliminating the need for traditional components and allowing for the use of IC technology. Also, as illustrated in FIG. 2, the output of the second RLC circuit at 214 is electrically coupled to a phase shifter at 212. The phase shifter shifts the signal phase 90 degrees, then couples the shifted signal to the mixer at 206. The output of the mixer is electrically coupled to an amplifier at 210 via a band pass filter at 208. Therefore another drawback to the prior art shown in circuit 200 in FIG. 2 is the requirement of a separate phase shifter, which can be difficult and costly to construct. The present invention does not require the construction of a separate phase shifter. A 90 degree phase shift is obtained from the RLC replacement components eliminating the need for any additional circuit components. SUMMARY OF THE INVENTION

The present invention meets the aforementioned needs by providing a double quad 4FSK (frequency-shift keying) demodulator circuit that is fully integrated on-chip. The present invention replaces the use of external filters with an internal RLC gyrator filter. The gyrator filter is comprised of gm cells that are connected in such a manner as to simulate inductors thereby eliminating the need to provide inductors off-chip. In addition to providing on-chip filters, the present invention also provides a phase locked loop circuit to keep the simulated inductor values tuned to specific values.

Therefore it is the object of the present invention to fully integrate an FM demodulator for 4FSK demodulation in a WLAN transceiver creating high gain and linearity, wide frequency range, and fully integrated FM demodulation, requiring no external quad network. The center frequency and gain are accurately maintained by auto-tuning making the present invention generally applicable to FM demodulators.

BRIEF DESCRIPTION OF DRAWINGS

These and other object, features and characteristics of the present invention will become more apparent to those skilled in the art from a study of the following detailed description in conjunction with the appended claims and drawings, all of which form a part of this specification. In the drawings: FIG. 1 illustrates a PRIOR ART single quad demodulator;

FIG. 2 illustrates a PRIOR ART double RLC demodulator;

FIG. 3 illustrates a plot of demodulation phase versus frequency;

FIG. 4 illustrates a demodulation block diagram for the present invention;

FIG. 5 illustrates a "GM" cell component schematic for the present invention; FIG. 6 illustrates a "GYRATOR" cell component schematic for the present invention; and

FIG. 7 illustrates a plot of demodulation output for 4FSK signals at different resonant frequency Fo values.

DETAILED DESCRIPTION OF PRESENTLY PREFERRED EXEMPLARY EMBODIMENTS

An object of the present invention is to fully integrate an FM demodulator for 4FSK (frequency- shift keying) demodulation in a WLAN (wireless local area network) transceiver, creating high gain and linearity, wide frequency range, and fully integrated FM demodulation requiring no external quad network. The center frequency and gain are accurately maintained by auto-tuning making the present invention generally applicable to FM demodulators.

In the prior art FIG. 1 and FIG. 2, demodulators are illustrated in which traditional RLC filters were employed. The function of an RLC filter is to allow desired frequency values to pass but block undesired frequency values. At a resonant frequency, the RLC circuit becomes purely resistive and the point at which response peaks, , is called the center frequency. The two points on the response curve, one point below the center frequency and one point above the center frequency, where response drops 3 dB below the center frequency response, defines the bandwidth of the RLC filter. At very high and very low frequencies, response is reduced drastically. How narrow this bandwidth becomes is determined by the pole-Q. Increasing pole- Q results in a narrower bandwidth and a more selective RLC filter.

The classical single quad demodulator as shown in FIG. 1 gives a relatively poor phase linearity versus frequency value in the range of 4.5 to 5.5 MHz. By the use of two cascaded RLC networks with half the Q of the single quad network, and a 90 degree phase shift, the same demodulation gain can be achieved but with much better linearity.

The results for the phase gain and linearity are as follows,

These results are for a single quad with a resonant frequency Fo of 5MHz and a quality factor Q=3.2 and a double RLC with two networks set to a resonant frequency Fo of 5MHz and a quality factor Q of 1.6. The scale factor for the demodulator is 0.0073 degrees/kHz.

The modulation technique chosen requires the best scale factor, linearity and a low modulation index value. Frequency-shift keying (FSK) is frequency modulation (FM) shifting output frequencies between predetermined values using a modulating signal. FSK may be noncoherent, in which the output frequency is shifted between two discrete values called the "mark" and "space" frequencies or FSK may be coherent, in which no phase discontinuity occurs in the output signal. A 4FSK modulation is a constant envelope modulation scheme where a carrier frequency (Fc), is frequency modulated into four states,

1. Fc+F(low)

2. Fc+F(high) 3. Fc-F(low)

4. Fc-F(high)

A frequency-shift keying modulator takes two carrier waves of different frequencies and assigns each a signal, either a 1 or 0, at any given time. A signal value of 1 will be assigned to carrier waveform (say carrier 1 waveform) and the value of 0 will be assigned to the other carrier waveform (say carrier 2 waveform). A signal value of 1, when received, will result in carrier 1 waveform, for the duration of the signal, being generated as the FSK modulated carrier. A signal value of 0, when received, will result in carrier 2 waveform, for the duration of the signal, being generated as the FSK modulated carrier. Therefore the FSK modulated carrier will consist of various periods in which carrier 1 waveform is present and various periods in which carrier 2 waveform is present, each corresponding to a signal value of 1 or 0 received, respectively.

In the frequency domain, frequency-shift keying results in the frequency shifted to a new center frequency value. A 2FSK modulator will shift the carrier frequency to two new center frequencies and a 4FSK modulator will shift the carrier frequency to four new center frequencies, Fc+F(low), Fc+F(high), Fc-F(low), and Fc-F(high). Frequency-shift keying maintains constant amplitude and is more immune to noise than amplitude-shift keying (ASK), however FSK requires more analog bandwidth.

An FM detector has to operate between 4.5 and 5.5 MHz with 2 FSK +/- 175kHz and 4FSK +/-175kHz and +/- 85kHz signals at 1M symbols/sec. This gives a modulation index value significantly lower than one. The modulation index compares the frequency deviation of the modulated signal to a sinusoidal modulating signal. The frequency deviation being the difference between modulated wave frequency and the carrier frequency during a specific period. The ratio of modulated signal frequency deviation to a sinusoidal modulating signal is the modulation index, equal to the phase deviation in radians. PLL (phase locked loop) and quadrature demodulators appear to give the best demodulated eye diagram, a diagram which displays signal distortion by sampling a data signal from a receiver applied to a vertical axis where data rate is the horizontal axis. An open eye diagram represents little signal distortion and a closed eye diagram indicates the presence of noise and interference. On first inspection, the ideal PLL demodulator has the best performance versus frequency offset, however this will be dependent on the linearity of the VCO (voltage controlled oscillator) employed. A phase locked loop is used to control an oscillator so that a constant phase angle, relative to a reference signal, is maintained. Given the already extensive use of auto-tuned CMOS gm cells to generate LC filters, it was considered the best approach would be the quadrature demodulator method, modulation using two carriers out of phase by 90 degrees and modulated by separate signals. However, we should also consider methods giving the best scale factor (mV/kHz) and linearity.

To fully integrate the circuit, we must address components, which are not IC compatible. A significant drawback of an RLC filter is the requirement of large, bulky traditional components. This greatly limits design options that demand ever smaller, component design, inductors being virtually impossible to fabricate using integrated circuit (IC) technology. One solution is the use of a gyrator to replace inductors in circuits, which lack space for large traditional components. Gyrators may be made having the current- voltage relationship of an inductor, i.e. a synthetic inductor, thereby replacing inductors in circuits such as RLC circuits. A gyrator, as described by the article "Gyrator Video Filter IC with Automatic Tuning" by Kenneth W. Moulding et al. in "IEEE Journal of Solid State Circuits, vol. SC-15, pp. 963-968, Dec. 1980", consists of two voltage controlled current sources of opposite polarities connected in parallel, the input and output of a first current source providing an input port and the input and output of a second current source electrically coupled to a capacitor. A "synthetic" inductance is realized at the input ports.

In FIG. 4, circuit 400 illustrates the replacement of traditional RLC components with gyrators. The first RLC and second RLC circuit of prior art FIG. 2 have been replaced with a first gm cell circuit at 416 electrically coupled to a first gyrator cell circuit at 412, and a second gm cell circuit at 414 which is electrically coupled to a second gyrator cell circuit at 410. The phase shifter of FIG.2 has been removed, requiring no additional components since a convenient feature of either gyrator cell 412 or 410 is the provision of a phase shifted signal output if properly electrically coupled as shown at 410. Prior art U.S. Patent 4812785, issued March 14,

1989 to Pauker Vlad, teaches a known gyrator circuit may be used to simulate an inductance to realize a resonant circuit. The resonant filter circuit taught by Vlad however, is dependent upon a traditional capacitor arranged with the gyrator to constitute the desired LC circuit. As noted, a gyrator requires loading by a capacitance but the capacitance need not be traditional. The present invention does not rely on a traditional capacitance to complete the gyrator circuit. Also, the present invention does not rely on a quartz oscillator included in the prior art circuit. The resonant circuit taught by Vlad includes a quartz oscillator, used to tune an auxiliary gyrator circuit. This is to reduce problems created by varying component characteristics in the circuit and maintain a high quality factor. The present invention replaces traditional resistor, inductor and capacitor components with an arrangement of cells and a phase locked loop auto tuner. The signal input at 402 is electrically coupled to a mixer at 404 and a first gm cell at 416. The output of the first gm cell is electrically coupled to a second gm cell at 414 and a first gyrator cell at 412. The coupling of 416 and 412 creates the equivalent of RLC circuit 216 in FIG. 2. The first gm cell at 416 is back- connected to approximate a resistor, with dual gm cells electrically coupled creating a gyrator (i.e. a synthetic inductance) at 412, while the gate capacitance of appropriately scaled devices serve as the capacitor for the gyrator, completing the RLC equivalent circuit. This allows the use of integrated circuit (IC) technology. The output of the second gm cell at 414 is electrically coupled to a second gyrator cell at

410. The coupling of 414 and 410 creates the equivalent of RLC circuit 214 in FIG. 2. As with the first gm cell, the second gm cell at 414 is also back-connected to approximate a resistor, with dual gm cells electrically coupled creating a gyrator (i.e. another synthetic inductance) at 410 while the gate capacitance of appropriately scaled devices serve as the capacitor for the gyrator, completing the RLC equivalent circuit and allowing the use of integrated circuit (IC) technology as with the first gm cell and gyrator cell coupling.

An output from the second gyrator cell at 410 is electrically coupled to the mixer at 404. By taking the output directly from the second gyrator cell at 410 rather than from the output port of the second gm cell at 414, a 90 degree phase shift in the signal is produced without the need for an additional phase shifter. Therefore the 90 degree phase shifter shown at 212 in FIG. 2 is no longer needed. The 90 phase shift output from 410 essentially is provided "for free" since 410 was required for coupling to 414 to create an equivalent RLC circuit to replace 214 in FIG. 2. As seen in FIG. 1 and FIG. 2, the output of the mixer at 404 is electrically coupled to an amplifier at 408 via a band-pass filter at 405. The mixer at 404 used for the system simulations is a simple bipolar Gilbert cell with signal amplitudes set such that the mixer is fully switching. The mixer output swing is 2 Volts (peak to peak) differential for the 10MHz doubled output. Therefore the DC output can swing from zero to -IV for -90 degree inputs and zero to +1V for +90 degree inputs.

The demodulation mixer scale factor, the given phase difference divided by the value given by zero to peak voltage is 1 volt in this case. This gives a typical demodulation scale factor of:

73e-6 degrees/kHz * 1/90 = 0.81mV/kHz Typical demodulated 4FSK waveform for center frequencies of 4.675, 5 & 5.325 MHz are shown in FIG. 7. A gm cell circuit, as used in FIG. 4 at 416 and 414, is illustrated in circuit 500 in FIG. 5. Circuit 500 contains six pairs of CMOS transistors configured as inverters, where in each pair the gate of one is electrically coupled to the gate of the other, and the drain of one is electrically coupled to the drain of the other. A signal input at 502 is electrically coupled to the gate coupling of CMOS pair 506. A signal input at 504 is electrically coupled to the gate coupling of

CMOS pair 508. The drain coupling of CMOS pair 508 is electrically coupled to the gate coupling of CMOS pair 512 and to the output at 520. The drain coupling of CMOS pair 512 is electrically coupled to the gate coupling and drain coupling of CMOS pair 510. The drain coupling of CMOS pair 506 is electrically coupled to the drain coupling of CMOS pair 510 and the gate coupling of CMOS pair 514 in addition to the output 518. The drain coupling of CMOS pair 514 is electrically coupled to the gate coupling and drain coupling of CMOS pair 516. The drain coupling of CMOS pair 516 is electrically coupled to the output 520. Also in each pair, the p channel source is electrically coupled to a supply voltage at 522, and the n channel source is electrically coupled to ground. The supply voltage 522 is controlled by a frequency auto-tuning loop, a phase locked loop, which maintains a constant inductor value. The phase locked loop is used to maintain a constant phase angle relative to a reference signal.

The pairs operate as CMOS inverters operating in the linear region rather than switching, a gm function which is auto-tunable. A CMOS inverter typically consists of two matched, enhancement-type transistors, one with an n-channel and one with a p-channel. The inverter may operate within five distinct ranges, the first being where Qn is off. The second, where Qn is in the pinch-off region and Qp is in the triode region, is followed by the third region where both Qn and Qp are both in the pinch-off region. The fourth is where Qp is in the pinch-off region and Qn is in the triode region and the fifth region is where Qp is off. The present invention operates in regions 2 and 4 where one Q (either Qn or Qp) is in pinch-off mode and the other Q of the pair (either Qn or Qp) is in the triode region. In these two regions, the voltage transfer at the drain coupling has a slope of-1.

A gyrator cell, as used in circuit 400 in FIG. 4, is illustrated in circuit 600 in FIG. 6. Circuit 600 contains two gm cells, CMOS gm stages in a gyrator configuration, connected in parallel to create a gyrator. An input at 602 is electrically coupled to a first gm cell at 606 and a second gm cell at 604. The output of the first gm cell at 606 is electrically coupled to the output of the second gm cell at 604 and out 608. Each gm cell is electrically coupled to an auto-tuned supply voltage provided by a phase locked loop at 610. As stated, the implementation of the RLC circuit can be achieved by using CMOS gm stages in a gyrator configuration to generate the inductance. The capacitance is reproduced by the gate capacitance of appropriately scaled (W and L) devices. For matching purposes, the resistance of the RLC circuit may be reproduced from a CMOS gm connected as an active resistor. Note that the inductance of the devices, along with the supply voltage at 522, sets Fo (i.e. the ratio of inductance to capacitance, L to C) and W sets the gm and hence the Q. The supply voltage of the gyrators cells is controlled by a frequency auto-tuning loop. The 90 degree phase shift needed for the double RLC demodulator is effectively given 'for free' by either of the gyrator cells.

Also, any process change in, for example, lower capacitance, will lead to a higher gyrated value of inductance (controlled by the auto-tuner) to keep the same Fo, but the active resistance of the RLC will also be higher and hence, the overall Q of the network and therefore demodulator gain, will remain unchanged.

The present invention has been described above with reference to what are presently considered to be the most practical and preferred embodiments. But the invention is not intended to be limited to the above disclosed embodiments. Rather, this invention should be construed to include all modifications and equivalent arrangements encompassed by the scope of the appended claims.

Claims

WHAT IS CLAIMED:

1. A fully integrated double quad 4FSK demodulator circuit comprising: . a limiting circuit; . a mixer circuit; . a phase locked loop circuit;

. a low pass filter; and

. a plurality of gm and gyrator cells connected together so as to provide two RLC filter networks.

2. The demodulator circuit of claim 1 further comprising: two carriers out of phase by 90 degrees; and a separate modulating signal.

3. A 4FSK demodulation circuit on a single integrated circuit chip comprising: a plurality of gm cells; a plurality of gyrator cells; a plurality of gm cells and gyrator cells connected together so as to provide two

RLC filters in series; and a phase locked loop circuit to auto-tune the provided RLC filters.

4. The apparatus of claim 3 further comprising connecting the gyrator cell so as to provide a 90 degree phase shift of the RLC filtered circuit.

5. The apparatus of claim 4 further comprising a limiter circuit to limit a received signal.

6. The apparatus of claim 5 further comprising a mixing circuit to combine the received signal and the RLC filtered and phase shifted signal to produce an output signal.

7. The apparatus of claim 6 further comprising a low pass filter circuit to filter said output signal.

8. The apparatus of claim 7 further comprising an amplifier circuit to amplify said output signal.

9. The apparatus of claim 8 further compromising twelve CMOS transistors to produce one gm cell.

10. A method for providing a 4FSK demodulation circuit on a single integrated circuit chip comprising the steps of; providing a plurality of gm cells; providing a plurality of gyrator cells; connecting a plurality of gm cells and gyrator cells so as to provide two RLC filters in series; and providing a phase locked loop circuit to auto-tune the provided RLC filters.

11. The method of claim 10 further comprising the step of connecting the gyrator cell so as to provide a 90 degree phase shift of the RLC filtered signal.

12. The method of claim 11 further comprising the step of providing a limiter circuit to limit a received signal.

13. The method of claim 12 further comprising the step of providing a mixing circuit to combine the received signal and the RLC filtered and phase shifted signal to produce an output signal.

14. The method of claim 13 further comprising the step of providing a low pass filter circuit to filter said output signal.

15. The method of claim 14 further comprising the step of providing an amplifier circuit to amplify said output signal.

16. The method of claim 15 further comprising the step of providing twelve CMOS transistors to produce one gm cell.

17. The method of claim 16 further comprising the step of connecting two gm cells to provide one gyrator cell.

18. The method of claim 17 further comprising the step of connecting two gm cells back to back to provide a gyrator cell.

19. The method of step 18 further comprising the step of connecting the signal from the phase locked loop circuit to the gyrator cell.

20. The method of claim 19 further comprising the step of simulating an inductor by the connection of the gm and gyrator cells.