WO2001031516A2

WO2001031516A2 - An emulation system having a efficient emulation signal routing architecture

Info

Publication number: WO2001031516A2
Application number: PCT/US2000/019744
Authority: WO
Inventors: Frederic Reblewski
Original assignee: Mentor Graphics Corporation
Priority date: 1999-10-22
Filing date: 2000-07-19
Publication date: 2001-05-03
Also published as: WO2001031516A3; JP2003527674A; EP1226526A2; AU6491400A

Abstract

An emulation system having an efficient I/O pin utilization architecture is disclosed. The emulation system includes a number of reconfigurable logic chips and circuit design mapping software that operates to map a circuit design onto the reconfigurable logic chips to realize and emulate the circuit design. Each logic chip includes a number of buffered I/O pins. Each buffered I/O pin has associated multiplexing circuitry that operates to time multiplex input/output of multiple emulation signals through the buffered I/O pin. The circuit design mapping software operates to interconnect allocated logic resources. All emulation signal fan outs are confined within the logic chips, and output through the buffered I/O pins in a time multiplexed manner, employing multiple signal routing timing domains. Additionally/alternatively, emulation signal routing between logic chips of the same logic board are also confined to their direct connections to provide deterministic timing delay within the logic board.

Description

An Emulation System Having An Efficient Emulation Signal Routing

Architecture

BACKGROUND OF THE INVENTION

Field of the Invention The present invention pertains to the field of circuit design emulation. More particularly, this invention relates to the subject of emulation signal routing efficiency of an emulation system.

Background With advances in integrated circuit technology, various tools have been developed to aid circuit designers in designing and debugging highly complex integrated circuits. In particular, emulation systems comprising reconfigurable emulation resources such as reconfigurable logic chips, reconfigurable interconnects, and so forth, have been developed for circuit designers to quickly "realize" their designs and emulate operation of the circuits.

One common feature shared by most emulation systems known in the art is the employment of a partial interconnect architecture. These partial interconnect architectures include e.g. the architecture disclosed in USP 5,036,437, and the architecture disclosed in USP 5,329,470. Another common feature shared by these prior art emulation systems is the manner in which emulation signal fan out is handled. Typically, at least 4n I/O pins are consumed for every 1 :n fan out, one I/O pin each on the source and destination logic chip and 2 I/O pins on at least one interconnect chip. Thus, these prior art emulation systems all suffer from at least one common disadvantage in that they are inefficient in their utilization of input/output (I/O) pin resources to effectuate inter-logic chip emulation signal routing. Great advances have been made in the art of sub-micron integration in recent years, resulting in significantly higher density for packing reconfigurable logic/interconnect resources onto reconfigurable logic/interconnect chips. However, due to physical constraints, pin density remains substantially unchanged, resulting in higher and higher logic to pin ratio. As a result, I/O pin resources have rapidly become one of the most valuable resources in an emulation system, and inefficient usage of I/O pin resources are increasingly costly. That is because once the I/O pins of a logic chip is used up, the remaining logic resources in the logic chip are pretty much useless, except for emulating "local" combinatorial logic. Yet, for these prior art emulation systems, they remain consuming the valuable I/O pin resources in the conventional inefficient manner.

Additionally, because of the inefficient usage of the logic resources, as a result of the inefficient manner the I/O pin resources are consumed, more logic chips have to be employed to emulate a circuit design than otherwise necessary. In turn, the problem of inter-logic chip emulation signal routing is further compounded, as increasing number of emulation signals have to be routed through multiple interconnect chips. This is because the circuit design being emulated is scattered over more logic chips than necessary. The routing of increasing number of emulation signals through multiple interconnect chips in turn cause more emulation signals to incur indeterministic timing delays, which in turn compound the emulation signal synchronization problem.

Thus, a more efficient approach to emulation signal routing is desired.

SUMMARY OF THE INVENTION

An emulation system having an efficient emulation signal routing architecture is disclosed. The emulation system includes a number of reconfigurable logic chips and circuit design mapping software that operates to map a circuit design onto the reconfigurable logic chips to realize and emulate the circuit design. Each logic chip includes a number of buffered I/O pins. Each buffered I/O pin has associated multiplexing circuitry that operates to time multiplex input/output of multiple emulation signals through the buffered I/O pin. The circuit design mapping software operates to allocate and interconnect allocated logic resources. In one embodiment, all emulation signal fan outs are confined within the logic chips, the internally fanned out emulation signals are output through the buffered I/O pins in a time multiplexed manner, employing multiple signal routing timing domains.

In one embodiment, the reconfigurable logic chips are distributively disposed on a number of logic boards, and the reconfigurable logic chips disposed on each logic board are directly and fully connected with one another to provide deterministic timing delay to all inter-logic chip emulation signal routing between logic chips of the same logic board. All inter-logic chip emulation signal routing between logic chips of the same logic board are confined to their direct connections.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

Figure 1 is a block diagram showing an exemplary emulation system incorporated with the teachings of the present invention;

Figure 2 is a block diagram showing one embodiment of the circuit design mapping software of Figure 1,

Figure 3 is a block diagram showing the emulation resources of the emulator of Figure 1 in further details;

Figure 4 is a block diagram showing one embodiment of a logic chip suitable for use in an emulation system of the present invention; Figure 5a-5b are block diagrams contrasting the manners in which emulation fan outs are handled under the prior art, and in accordance with the present invention; Figure 6 is a block diagram illustrating one embodiment of a logic board of the present invention;

Figure 7 is a flow diagram illustrating one embodiment of the method steps of the present invention for handling emulation signal fan out;

Figure 8 is a flow diagram illustrating one embodiment of the method steps of the present invention for handling inter-logic chip emulation signal routing within a logic board;

Figures 9a-9b are block diagrams illustrating two embodiments for distributively packaging the logic boards;

Figure 10 is a block diagram illustrating one embodiment of the interconnect board of Figure 9b; and

Figures 11a-11b are two block diagrams illustrating two embodiments for interconnecting the crates.

DETAILED DESCRIPTION

In the following description, various aspects of the present invention will be described. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some or all aspects of the present invention. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well known features are omitted or simplified in order not to obscure the present invention.

Parts of the description will be presented in terms of operations performed by a computer system, using terms such as data, flags, bits, values, characters, strings, numbers and the like, consistent with the manner commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. As well understood by those skilled in the art, these quantities take the form of electrical, magnetic, or optical signals capable of being stored, transferred, combined, and otherwise manipulated through mechanical and electrical components of the computer system; and the term computer system include general purpose as well as special purpose data processing machines, systems, and the like, that are standalone, adjunct or embedded.

Various operations will be described as multiple discrete steps in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Referring now to Figure 1, wherein a block diagram illustrating an exemplary emulation system incorporated with the teachings of the present invention is shown. As illustrated, emulation system 10 includes host system 12 and emulator 14. Host system 12 includes in particular circuit design mapping software 22 incorporated with teachings of the present invention, whereas emulator 14 includes configuration unit 18, host interface 20, and emulation resources denoted as emulation array and interconnect 16, which is also incorporated with the teachings of the present invention. The elements are coupled to each other as shown, and cooperate with one another in accordance with the present invention to enable emulation signals to be advantageously routed in a more efficient manner than prior art emulation systems.

Except for circuit design mapping software 22, host system 12 is intended to represent a broad category of host systems found in conventional emulation systems, including elements such as processor, memory, storage medium, and so forth (not shown). Thus, except of mapping software 22, host system 12 will not be otherwise further described. One embodiment of circuit design mapping software 22 will be described in detail below with references to Figure 2.

Similarly, except for the manner emulation resources of emulation array and interconnect 16 are organized to facilitate efficient emulation signal routing, emulator 14 is also intended to represent a broad category of emulator known in the art. In other words, configuration unit 18 and host interface 20 perform their conventional functions, and they are conventionally constituted. Thus, except for emulation array and inteconnect 16, emulator 14 will not be otherwise further described. Various embodiment of emulation array and interconnect 16 will be described in detail below with references to Figures 3-4 and 6.

Figure 2 illustrates one embodiment of mapping software 22 is shown. For the illustrated embodiment, circuit design mapping software 22 comprises design reader 30, primitive converter 32, partitioner 34, netlisting and interconnection generator 36, and logic and interconnect element configuration generator 38. Design reader 30, primitive converter 32, partitioner 34 and logic and interconnect element configuration generator 38 are intended to represent a broad category of these elements known in the art. In the case of netlist and interconnection generator 36, except for the teachings of the present invention incorporated, it too is intended to represent a broad category of such generators known in the art.

In other words, design reader 30 is employed to process formally represented circuit designs 40, whereas primitive converter 32 is employed to convert various circuit primitives described in circuit designs 40, as in prior art emulation systems. Similarly, partitioner 34 in turn is employed to partition the transformed circuit designs for mapping to various emulation resources of emulator 14. Netlist and interconnection generator 36 is employed to generate logic and interconnection netlists 42 of the emulation resources of emulator 14 to "realize" the circuit designs. Except, in accordance with one embodiment of the present invention, netlist and interconnection generator 36 confines all emulation signal fan outs within reconfigurable logic chips of emulator 14, and time multiplex input/output of the emulation signals through the I/O pins of reconfigurable logic chips of emulator 14. In accordance with another embodiment, netlist and interconnection generator 36 further confines at least inter-logic emulation signal routing between logic chips disposed on the same logic board to their direct connections. These and other aspects of the present invention will be further described below. Logic and interconnect element configuration generator 38 performs its conventional function of generating the configuration information 44 for the reconfigurable emulation resources included in logic and interconnect netlists 42 of the circuit designs.

In one embodiment, circuit design mapping software 22 is pre-loaded and stored in a suitable storage medium such as a disk of host system 12, and during operation, loaded into memory of host system 12 for execution by a processor of host system 12. In alternate embodiments, circuit design mapping software 22 may be distributed using any one of a number of distribution medium known in the art, such as CD or remote distribution through a server, and loaded onto host system 12 at the customer's site. Furthermore, in alternate embodiments, all or part of circuit design mapping software 22 may be implemented in hardware.

Figure 3 illustrates one embodiment of emulation array and interconnect 16. Emulation array and interconnect 16 includes reconfigurable logic resources 52, I/O resources 54 and service resources 56, interconnected by reconfigurable interconnects 58. In one embodiment, the reconfigurable logic resources 52 are distributively disposed on a number of logic boards. Similarly, I/O resources 54 and service resources 56 are distributively disposed on I/O and service boards respectively. The logic boards, I/O boards and service boards are interconnected and distributively packaged in a number of interconnected crates, to be described more fully below.

Figure 4 illustrates one embodiment of a reconfigurable logic chip suitable for use as a reconfigurable logic resource in the emulation system of the present invention with improved emulation signal routing. For the illustrated embodiment, logic chip 100 is a custom or special purpose logic chip. Logic chip 100 is equipped to enable mapping software 22 (more specifically, netlist and interconnection generator 36 of mapping software 22) to confine emulation signal fan outs to inside logic chip 100. As illustrated, logic chip 100 includes reconfigurable logic element (LE) array 102, on-chip interconnect network 104 and buffered I/O pins 113 having associated multiplexing circuitry 115 and 116, coupled to each other as shown. LE array 102 includes multiple reconfigurable LEs clocked by user clock(s) 118. Reconfigurable LEs are used to "realize" various logic elements of circuit designs. On-chip interconnect network 104 is used to facilitate on-chip emulation signal routing between e.g. LEs or LE and buffered I/O pins 113. Buffered I/O pins 113 are used to provide time multiplexed input/output of emulation signals to/from logic chip 100. In accordance with the present invention, netlist and interconnection generator 36 of mapping software 22, when interconnecting allocated logic resources of emulation system 10, netlist and interconnection genaertor 36 leverages on the time multiplexing input/output ability of logic chip 100 and confines all emulation signal fan outs within logic chip 100, to be described more fully below.

Figures 5a-5b contrast the prior art and the present invention's approach to emulation signal fan out are shown. As illustrated in Figure 5a, in a conventional prior art emulation system, emulation signals, e.g. emulation signals A and B, are permitted to be fanned out to multiple destination logic chips going through one or more interconnect chips, consuming numerous valuable I/O pins. In contrast, under the present invention, as illustrated in Figure 5b, emulation signals are not fanned out externally. Netlist and interconnection generator 36 of mapping software 22 will cause the emulation signals to be fanned out to different buffered I/O pins 113 internally within logic chip 100, and then time multiplexed to output the multiple emulation signals routed to a buffered I/O pin 113, to be described more fully below. According, the amount of I/O pin resources required to emulate a circuit design is significantly reduced under the present invention.

Referring back to Figure 4, for the illustrated embodiment, each buffered I/O pin 113 can be statically configured to be either an input or an output pin. This static configuration can be accomplished in any of a wide variety of conventional manners, such as by way of a configuration register. Additionally and more importantly, each buffered I/O pin 113 is used to input/output multiple emulation signals. In the illustrated embodiment, for ease of explanation, each buffered I/O pin 113 is used to time multiplex input/output of two different emulation signals. However, in alternate embodiments, each buffered I/O pin 113 is used to time multiplex input/output of two or more emulation signals. Obviously, the more emulation signals buffered I/O pins 113 can multiplex, the more versatile I/O pin 113 is. It is expected with the continued advances in sub- micron integration technology, the number of emulation signals I/O pin 113 can multiplex will increase geometrically. The emulation signals are time multiplexed on buffered I/O pins 113 by I/O circuitry 115, which includes a n-to- one multiplexer, and I/O circuitry 116, which includes a one-to-n demultiplexer, using signal routing clock 117. Thus, for the illustrated embodiment, only m/n buffered I/O pins 113 are necessary to support input/output of m emulation signals, due to the n-to-one multiplexing performed by I/O circuitry 115 and 116.

As illustrated, I/O circuitry 115 and 116 are clocked by signal routing clock(s) 117 whereas the LEs are clocked by a different clock signal (or signals), user clock(s) 118. In one embodiment, I/O circuitry 115 and 116 of each of the buffered I/O pins 113 is clocked by the same signal routing clock 117. In alternate embodiments, I/O circuitry 115 and 116 for different buffered I/O pins 113 can be clocked by different signal routing clocks rather than a single signal routing clock. Except for the relationship that each signal routing clock 117 has a higher frequency than an "associated" user clock 118, signal routing clocks 117 are independent of user clocks 118. For the purpose of this application, the "associated" user clock of a signal routing clock is the user clock employed to clock the logic elements from which the I/O signals of the I/O pins clocked by the signal routing clock originate or destined for. Typically, the frequency of the clock signal(s) in the signal routing time domain is 10 to 100 times greater than the frequency of the clock signal(s) in the user time domain. However, alternate embodiments could have different frequency ratios. As a result of the higher frequency of signal routing clock 117, emulation signals may be input to/output from logic chip 100 more frequently than emulation signals are changed internally within logic chip 100. Thus, signals can be advantageously transferred into and out of logic chip 100 asynchronously to the changing of the signals internal to logic chip 100. In other words, inter-logic chips emulation signal routing may be time multiplexed in a regionally time multiplexed manner, employing multiple signal routing as well as user time domains. Regionally time multiplexing of emulation signals is the subject of U.S. Patent Application, number 08/xxx,xxx (to be assigned), entitled "A regionally time multiplexed emulation system", filed on September 24, 1999, having at least a common inventor with the present invention. The application is hereby fully incorporated by reference.

In one embodiment, the multiplexing circuitry of I/O circuitry 115 and 116 are conventional multiplexers and demultiplexers. In alternate embodiments, other conventional mechanisms for sharing a single physical signal line by multiple logical signals may be employed instead. One embodiment of such conventional mechanism is described in detail in the incorporated by reference U.S. Patent Application, number 08/xxx,xxx (to be assigned). Still referring to Figure 4, for the illustrated embodiment, logic chip 100 further includes memory 112, context bus 106, scan register 108, and trigger circuitry 110. Memory 112 facilitates usage of logic chip 100 to emulate circuit design with memory elements. Context bus 106, scan register 108 and trigger circuitry 110 provide on-chip integrated debugging facility for logic chip 100. These elements are described in U.S. patent application serial number 08/542,838, entitled "A Field Programmable Gate Array with Integrated Debugging Facilities", now U.S. Patent 5,777,489, which is hereby fully incorporated by reference.

Referring now to Figure 6, wherein a block diagram illustrating one embodiment of a logic board employed to distributively package the logic chips of the emulation system of the present invention is shown. As shown, each logic board 200 includes a number of logic chips 100 described earlier. In accordance with the present invention, logic chips 100 of the same logic board 200 are directly and fully interconnected with one another, to provide deterministic timing delay within the logic board for emulation signal routing between the logic chips 100 of the same logic board 200. Each "direct connection" includes multiple direct connections between I/O pins of two logic chips 100. The number of direct connections provided between any two logic chips is application dependent, depending on number of I/O pins available per logic chip, and the number of logic chips included in each logic board. In accordance with the present invention, netlist and interconnection generator 36 of mapping software 22 when interconnecting allocated logic resources, further advantageously leverages on the fully interconnected architecture of logic board 200 and confines all inter-logic chip emulation signal routing between logic chips 100 of logic board 200 to the direct connections between them.

Figures 7-8 illustrate the method steps for various relevant aspects of the present invention for interconnecting allocated logic resources, in accordance with one embodiment. Fig. 7 illustrates the steps for confining a 1 :n fan out within a logic chip; and Fig. 8 illustrates the steps for interconnecting two I/O pins of two logic chips.

As shown in Fig. 7, whenever a 1 :n fan out situation is encountered, netlist and interconnection generator 36 iteratively confines the fan out to inside the source logic chip. At step 702, a fan out destination is selected. Next, generator 36 determines if an I/O pin of the source logic chip is already allocated to output signals to the destination logic chip, step 704, and if an I/O pin of the source logic chip is already allocated, whether all time slots of the I/O pin have been used, step 706. If either an I/O pin of the source logic chip has not been allocated, or the time slots of the allocated I/O pin have all been used, generator 36 allocates a new I/O pin to output the signal to the destination logic chip, step 708. Upon allocating a new I/O pin, or upon identifying an allocated I/O pin with available time slot(s), generator 36 allocates a time slot (and its correspondinig buffer) of the I/O pin to output the signal to the destination logic chip, step 710. Steps 702 - 710 are repeated until all fan-out destinations are determined to be handled for the particular fan out situation, step 712. Steps 702-712 are repeated for each fan out situation in a logic chip, step 714. The described process is repeated for all logic chips. At this point, the process proceeds to route signals between logic chips, before continuing on with interconnecting the buffers of the allocated time slots to the source logic elements of the fan out signals.

Figure 8 illustrates one embodiment of the method steps of the present invention for handling emulation signal routing between logic chips of the same logic board. Recall that at this point, all fan outs have been confined to within a logic chip, and each output signal has been assigned to an I/O pin, including a particularized time slot buffer. At step 802, netlist and interconnection generator 36 selects a source logic chip of the logic board. Next, generator 36 selects an allocated time slot buffer of an output pin of the source logic chip, step 804. Next, generator 36 selects the corresponding time slot buffer of an input pin of the destination logic chip, and of a direct connection connecting the selected input pin of the destination logic chip and the output pin of the source logic chip, steps 806 - 808. If the corresponding time slot buffer of all direct connections of the selected input pin are used, generator 36 attempts to select another input pin. If all corresponding time slot buffers of all direct connections of all directly connected input pins are used, generator 36 may attempt to reassign the output signal to another time slot buffer of another I/O pin of the logic chip, terminate the process and cause partitioner 34 to re-partition the circuit design, or employ other recovery or adjustment process. In any event, once an input pin with a corresponding time slot buffer and a direct connection is found, the input pin, together with the corresponding time slot buffer and the direct connection are allocated. Steps 802 - 808 are repeated until all allocated time slot buffers of all output pins of the source logic chip are processed, step 810. Steps 802 - 810 are then repeated until all logic chips of the logic board are processed. The described process is repeated for each logic board. The I/O pins of logic boards are interconnected in like manner.

Referring now back to Figure 7, more specifically, at step 720, generator 36 (after having successfully interconnecting all time slot buffers of all I/O pins of all logic chips) now proceeds to iteratively allocate the interconnect fabrics within the logic chips to interconnect all time slot buffers of all I/O pins of all logic chips to their corresponding signal source logic elements within the corresponding logic chips. The allocation may be performed in any one of a number of techniques known in the art. If an interconnect path to the source signal logic element is not available for an allocated time slot buffer, generator 36 may attempt to to find such interconnect path by swapping "equivalent" time slot buffers (equivalent in both destination and timing). Alternatively, generator 36 may terminate the process to cause partitioner 34 to re-partition the circuit design. Referring now to Figures 9a-9b, wherein two block diagrams illustrating two embodiments of a crate employed to distributively package the fully interconnected logic board of the emulation system of the present invention are shown. As shown in both Figure 9a and 9b, each crate 300a or 300b includes a number of logic boards 200a or 200b (which are variants of logic board 200 described earlier), and a number of I/O and service boards 220a or 220b, and 240a or 240b. For the embodiment illustrated in Figure 9b, crate 300b further includes a number of interconnect boards 260b.

Logic, I/O and service boards 200a, 220a and 240a of the each crate 300a (Figure 9a) are also directly and fully interconnected with one another, to provide deterministic timing delay within the crate for emulation signal routing between boards 200a, 220a and 240a of the same crate 300a. The I/O pins of boards 200a, 220a and 240a are similarly buffered and having associated multiplexing circuitry (not shown) as described earlier for logic chips 100. In accordance with the present invention, netlist and interconnection generator 36 of mapping software 22 when interconnecting allocated logic resources, further advantageously leverages on the fully interconnected and time multiplexed architecture of crate 300a and confines all inter-board emulation signal routing between boards 200a, 220a and 240a of crate 300a to the direct connections between them. Netlist and interconnection generator 36 of mapping software 22 employs similar method steps described earlier for logic chips 100.

In contrast, logic, I/O, service and interconnect boards 200b, 220b, 240b and 260b of the same crate 300b (Figure 9b) employ a conventional partial interconnect architecture instead. The I/O pins of boards 200b, 220b, 240b and 260b are conventionally constituted. Interconnect board 260b includes a number of routing chips 140, partially interconnected with each other (Figure 10), except routing chips 140, similar to logic chips 100, are equipped with buffered I/O pins with associated multiplexing circuitry to facilitate time multiplexing employing multiple signal routing timing domains. Each of routing chips 140 includes a static routing core. One embodiment of routing chip 140 is described in detail in the incorporated by reference U.S. Patent Application, number 08/xxx,xxx. Netlist and interconnection generator 36 of mapping software 22 when interconnecting allocated logic resources further advantageously leverages on the time multiplexing capabilities of routing chips 140 of interconnect board 260b and regionally time multiplexes routing of emulation signals between boards 200b, 220b and 240b, employing multiple signal routing time domains, as described in the incorporated by reference U.S. Patent Application, number 08/xxx,xxx.

Figures 11a-11b illustrate one embodiment each for interconnecting crates 300a or 300b together to form emulator 14. In Figure 11a, crates 300a are directly and fully connected with each other, using the buffered and time multiplexing capable I/O pins of I/O boards 220a, whereas in Figure 11b, crates 300b are partially interconnected, by interconnecting interconnect boards 260b. For the embodiment of Figure 11a, netlist and interconnection generator 36 of mapping software 22 when interconnecting allocated logic resources, further advantageously leverages on the fully interconnected and time multiplexed architecture and confines all inter-crate emulation signal routing between crates 300a to the direct connections between them. Netlist and interconnection generator 36 of mapping software 22 employs similar method steps described earlier for logic chips 100. For the embodiment of Figure 11b, netlist and interconnection generator 36 of mapping software 22 when interconnecting allocated logic resources further advantageously leverages on the time multiplexing capabilities of routing chips 140 of interconnect board 260b and regionally time multiplexes routing of emulation signals between crates 300b, employing multiple signal routing time domains, as described in the incorporated by reference U.S. Patent Application, number 08/xxx,xxx.

While for ease of understanding, the present invention has been described in terms of the above illustrated embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of restrictive on the present invention.

Thus, an emulation system having an efficient I/O pin utilization architecture has been described.

Claims

CLAIMSWhat is claimed is:

1. An emulation system comprising

(a) an emulator having a plurality of reconfigurable logic chips reconfigurable to emulate logic elements of a circuit design, wherein each logic chip includes a plurality of buffered I/O pins having associated multiplexing circuitry to time multiplex input/output of emulation signals through the buffered I/O pins; and

(b) a host system programmed with programming instructions that operate to generate configuration information for the circuit design to configure the recofigurable logic chips to emulate the circuit design, wherein all emulation signal fan outs are confined within the reconfigurable logic chips and the fanned out emulation signals are output through the buffered I/O pins in the time multiplexed manner.

2. The emulation system of claim 1 , wherein emulation signals, including the fanned out emulation signals, are output through the buffered I/O pins in a regionally time multiplexed manner, employing multiple signal routing time domains.

3. The emulation system of claim 1 , wherein the reconfigurable logic chips are distributively disposed on a plurality of logic boards, with the reconfigurable logic chips disposed on the same logic board being directly and fully connected to one another to provide deterministic timing delay for all inter-logic chip emulation signal routing between logic chips of the same logic board; and the host system operates to route the time multiplexed emulation signals between the logic chips, confining all time multiplexed emulation signals routing between logic chips of the same logic board to their direct connections.

4. An emulation system comprising:

(a) an emulator having a plurality of reconfigurable logic chips reconfigurable to emulate logic elements of a circuit design, wherein the logic chips are distributively disposed on a plurality of logic boards, with the reconfigurable logic chips disposed on the same logic board being directly and fully connected to one another to provide deterministic timing delay for all inter- logic chip emulation signal routing between logic chips of the same logic board; and

(b) a host system programmed with programming instructions that operate to generate configuration information for the circuit design to configure the recofigurable logic chips to emulate the circuit design, wherein routing of emulation signals between the logic chips of the same logic board are confined to the direct connections.

5. The emulation system of claim 4, wherein the routing of the emulation signals are time multiplexed in a regionally time multiplexed manner, employing multiple signal routing time domains.

6. An emulation system comprising:

(a) an emulator having a plurality of reconfigurable logic chips reconfigurable to emulate logic elements of a circuit design, wherein each logic chip includes a plurality of buffered I/O pins having associated multiplexing circuitry to time multiplex input/output of emulation signals through the buffered I/O pins, and wherein the logic chips are distributively disposed on a plurality of logic boards, with the reconfigurable logic chips disposed on the same logic board being directly and fully connected to one another to provide deterministic timing delay for all inter-logic chip emulation signal routing between logic chips of the same logic board.

7. An apparatus comprising: (a) a storage medium having stored therein programming instructions, when executed, operate to generate configuration information for a circuit design for configuring recofigurable logic chips for emulating the circuit design, wherein the programming instructions confine all emulation signal fan outs within the reconfigurable logic chips and output the fanned out emulation signals through buffered I/O pins of the reconfigurable logic chips in a time multiplexed manner, and wherein the programming instructions confine routing of the time multiplexed emulation signals between reconfigurable logic chips of the same logic board to their direct connections; and

(b) an execution unit coupled to the storage medium that operate to execute the programming instructions.

8. A method comprising:

(a) partitioning a circuit design to map the circuit design to a plurality of reconfigurable logic chips, where each of the reconfigurable logic chips having a plurality of buffered I/O pins having associated multiplexing circuitry to time multiplex input/output of emulation signals;

(b) routing emulation signals between the reconfigurable logic chips, confining all emulation signal fan outs within the reconfigurable logic chips, and inputting/outputting the emulation signals in a time multiplexed manner; and

(c) configuring the reconfigurable logic chips in accordance with said partitioning and routing to emulate the circuit design.

9. The method of claim 8, wherein (b) comprises routing emulation signals between the reconfigurable logic chips in a regionally time multiplexed manner, employing multiple signal routing time domains.

10. The method of claim 8, wherein the reconfigurable logic chips are distributively disposed on a plurality of logic boards, with reconfigurable logic chips of the same logic board being directly and fully interconnected to one another to provide deterministic time delay to inter-logic chip emulation signal routing between logic chips of the same logic board, and the routing of (b) is performed with all inter-logic chip emulation signal routing between logic chips of the same logic board being confined to their direct connections.

11. A method comprising:

(a) partitioning a circuit design to map the circuit design to a plurality of reconfigurable logic chips distributively disposed on a plurality of logic boards, where the reconfigurable logic chips disposed on the same logic board are directly and fully connected to each other to provide deterministic timing delay for all inter-logic chip emulation signal routing between logic chips of the same logic board;

(b) routing emulation signals between the reconfigurable logic chips, confining all inter-logic chip emulation signal routing to the direct connections of the reconfigurable logic chips; and

12. A storage medium having stored therein programming instructions to be executed by an execution unit, wherein, when executed, the programming instructions operate to generate configuration information for a circuit design for configuring recofigurable logic chips for emulating the circuit design, the programming instructions confining all emulation signal fan outs within the reconfigurable logic chips, and outputting the fanned out emulation signals through buffered I/O pins of the reconfigurable logic chips in a time multiplexed manner.

13. A storage medium having stored therein programming instructions to be executed by an execution unit, wherein, when executed, the programming instructions operate to generate configuration information for a circuit design for configuring recofigurable logic chips for emulating the circuit design, the programming instruction confining routing of time multiplexed emulation signals between reconfigurable logic chips of the same logic board to their direct connections.