WO2001037430A1

WO2001037430A1 - Arrangement and method for implementing transmitter unit of digital data transmission system

Info

Publication number: WO2001037430A1
Application number: PCT/FI2000/000982
Authority: WO
Inventors: Risto Hietala
Original assignee: Nokia Corporation
Priority date: 1999-11-12
Filing date: 2000-11-10
Publication date: 2001-05-25
Also published as: AU1526001A

Abstract

The invention relates to a method and an arrangement implementing the method for implementing the transmitter operation of a digital data transmission system. The method comprises the steps of converting an information signal to be transmitted into a first intermediate-frequency signal such that the first intermediate-frequency signal is processed to a desired frequency band, and converting the first intermediate-frequency signal into a variable-frequency signal on the above mentioned frequency band, and filtering away interference signals. The method further comprises the steps of mixing the first intermediate-frequency signal with a fixed-frequency signal in order to generate a second intermediate-frequency signal such that the second intermediate-frequency signal is a variable-frequency signal similarly as the first intermediate-frequency signal, converting the second intermediate-frequency signal into an output signal to a transmission band width which is in its entirety at a higher frequency range than the second intermediate-frequency signal, and converting the second intermediate-frequency signal into the output signal such that the output signal is adapted to frequency changes of the second intermediate-frequency signal.

Description

ARRANGEMENT AND METHOD FOR IMPLEMENTING TRANSMITTER UNIT OF DIGITAL DATA TRANSMISSION SYSTEM

FIELD OF THE INVENTION

The invention relates to an arrangement and a method for imple- menting a transmitter unit of a digital data transmission system, the transmitter unit being typically implemented in a base station of a telecommunication system.

BACKGROUND OF THE INVENTION

In a prior art solution a transmitter unit of a digital data transmission system is implemented in a base station by means of a digital synthesizer, a fixed PLL synthesizer, parallel active PLL synthesizers, switches, mixers, a passband filter and a power unit. The PLL (Phase Locked Loop) synthesizer is a synthesizer comprising a feedback. The digital synthesizer converts an information signal to be transmitted into a first intermediate-frequency signal such that the first intermediate-frequency signal settles to a bandwidth which equals to the final transmission band width to be formed at the output of the transmitter unit. The digital synthesizer also converts the first intermediate- frequency signal into a variable-frequency signal. A signal that has a variable frequency moves to a channel of a different frequency range at desired inter- vals.

A first fixed PLL synthesizer and a first mixer convert the first intermediate-frequency signal into a second intermediate-frequency signal which is at higher frequencies than the first intermediate-frequency signal. By means of passband filtering, spurious pulses that have been formed in the mixer are filtered away from the second intermediate-frequency signal. The active PLL synthesizers are frequency processing units which generate a variable- frequency signal such that they follow the frequency changes caused by the digital synthesizer to the first intermediate-frequency signal. By means of two alternately operating active PLL synthesizers and a second mixer, the second intermediate-frequency signal is converted into a transmit frequency output signal of the transmitter unit. The power unit increases the transmission power of the output signal to a desired level. Both parallel active PLL synthesizers mentioned above generate a variable-frequency signal such that both synthesizers perform frequency hopping. In the prior art solution there has to be two active PLL synthesizers in parallel, because it takes a relatively long time until these PLL synthesizers settle to new frequencies. During the settling time the first active PLL synthesizer settles to a new frequency, whereafter it can be switched on by a switch. During the operation of the first active PLL synthesizer, the second active PLL synthesizer settles to the new frequency during its settling time, after which the first active PLL synthesizer is switched off and the second active PLL synthesizer is switched on. In the above example of parallel active PLL synthesizers, the frequency hopping of the active PLL synthesizers causes interference signals to the output signal, which may cause serious problems. In addition, crosstalk from the supply lines of the ac- tive PLL synthesizers may occur especially via the switch such that it causes an interference signal to the output signal. As a result of the above, the active PLL synthesizers have to be protected from external interference signals, and this leads to additional electrical and mechanical special solutions. A disadvantage of the prior art solution is also that the phase comparison frequencies to be used in PLL synthesizers are relatively low, which causes phase noise and phase error. All in all, it can be stated that the prior art solution is complicated, requires a lot of components and suffers from interference signals.

BRIEF DESCRIPTION OF THE INVENTION

It is an object of the invention to provide a method and an arrange- ment implementing the method such that the above problems can be solved. This is achieved by a method of implementing the transmitter operation of a digital data transmission system. The method comprises the steps of converting an information signal to be transmitted into a first intermediate-frequency signal such that the first intermediate-frequency signal is processed to a de- sired frequency band, converting the first intermediate-frequency signal into a variable-frequency signal on the above mentioned frequency band and filtering away interference signals, mixing the first intermediate-frequency signal with a fixed-frequency signal in order to generate a second intermediate-frequency signal such that the second intermediate-frequency signal is a variable- frequency signal similarly as the first intermediate-frequency signal, converting the second intermediate-frequency signal into an output signal to a transmission band width which is in its entirety at a higher frequency range than the second intermediate-frequency signal, and converting the second intermediate-frequency signal into the output signal such that the output signal is adapted to frequency changes of the second intermediate-frequency signal. The invention also relates to an arrangement for implementing a transmitter unit of a digital data transmission system. The arrangement comprises a digital synthesizer for converting an information signal to be transmitted into a first intermediate-frequency signal with a variable frequency to a de- sired bandwidth, a passband filter for filtering away interference signals, a first frequency processing unit generating a fixed-frequency signal, a mixer for mixing the above mentioned fixed-frequency signal with the first intermediate- frequency signal in order to form a second intermediate-frequency signal such that the second intermediate-frequency signal is a variable-frequency signal similarly as the first intermediate-frequency signal, a second frequency processing unit for converting the second intermediate-frequency signal into an output signal to a transmission band width which is in its entirety at a higher frequency range than the second intermediate-frequency signal, and the second frequency processing unit for converting the second intermediate- frequency signal into the output signal such that the output signal is adapted to frequency changes of the second intermediate-frequency signal.

The preferred embodiments of the invention are disclosed in the dependent claims.

The invention is based on the idea that the first frequency process- ing unit generates a fixed-frequency signal which is mixed with a first intermediate-frequency signal with a variable frequency, generated from an information signal to be transmitted, in order to generate a second intermediate- frequency signal with a variable frequency. The second frequency processing unit converts the second intermediate-frequency signal into an output signal, which follows the frequency changes of the second intermediate-frequency signal, to a desired bandwidth.

The method and arrangement of the invention provide a plurality of advantages. Since the first frequency processing unit is arranged to generate a fixed-frequency signal that remains at the same frequency and the digital synthesizer is arranged to convert an information signal to be transmitted into a variable-frequency signal, low division numbers can be used in the second frequency processing unit, wherefore the phase comparison frequencies can be at higher frequencies than in the prior art solution. Since the phase comparison frequencies are at high frequencies, phase error and phase noise are relatively low in the solution of the invention. As regards PLL synthesizers operating typically as frequency processing units it is often so that the higher the phase comparison frequency is, the lower the phase error and phase noise are. Thus, the invention enables an accurate operation of a transmitter unit. The most significant advantage of the solution according to the invention is that no parallel frequency processing units generating variable-frequency sig- nals are required.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following the invention will be described in greater detail in connection with the preferred embodiments, with reference to the attached drawings, in which Figure 1 shows a transmitter unit according to the invention,

Figure 2 shows a transmitter unit according to a preferred embodiment of the invention,

Figure 3 shows a first PLL synthesizer,

Figure 4 shows a second PLL synthesizer.

DETAILED DESCRIPTION OF THE INVENTION

A transmitter unit according to the invention can typically be applied to base stations of GSM-900, GSM-1800 and GSM-1900 systems.

Figure 1 shows a structure of a transmitter unit according to the invention. A digital synthesizer 100 converts an information signal to be trans- mitted into a first intermediate-frequency signal. The digital synthesizer 100 comprises a DA converter (Digital to Analogy) which converts a digital information signal to be transmitted to an analog signal. The DA converter sets certain frequency limits for the digital synthesizer. Nowadays the maximum frequencies of DA converters are about 400 MHz, but the maximum frequen- cies will probably become even higher in the future. The digital synthesizer 100 comprises a modulator which modulates the information signal to be transmitted to a first intermediate-frequency signal to a desired bandwidth, which is narrower than the final transmission band width. The digital synthesizer further comprises a frequency hopping synthesizer by which it can change the frequency of the first intermediate-frequency signal at desired intervals.

Due to the frequency limits set by the DA converter for the digital synthesizer, the first intermediate-frequency signal generated by the digital synthesizer is at relatively low frequencies. Thus, the frequencies of the inter- mediate-frequency signal have to be increased at the following signal proc- essing stages of the transmitter unit. Frequencies are increased at the next signal processing stage, at which the first intermediate-frequency signal is converted into a second intermediate-frequency signal. The second intermediate-frequency signal is a variable-frequency signal similarly as the first inter- mediate-frequency signal, and also typically on the corresponding bandwidth. Thus, the only essential difference between the first and the second intermediate-frequency signal is typically that the second intermediate-frequency signal is at a higher frequency range than the first intermediate-frequency signal. A first frequency processing unit 102 generates a fixed-frequency signal, which is a narrow-band signal, such as a 172 MHz signal, that remains at a specific frequency. To increase the frequencies of the second intermediate- frequency signal to a desired level, a fixed-frequency signal with a desired frequency can be mixed by a mixer 104 with the first intermediate-frequency signal. Thereafter, interference signals are filtered from the second intermediate- frequency signal by means of a filter 106. A considerable number of interference signals to be filtered have been formed in connection with the above mentioned mixing.

The second intermediate-frequency signal is an input signal of a second frequency processing unit 108, and it can also be called a reference signal of the second frequency processing unit. The second frequency processing unit comprises a feedback. The second frequency processing unit converts the second intermediate-frequency signal into an output signal of the transmitter unit, which output signal may be at considerably higher frequencies and on a considerably broader transmission band width than the first and the second intermediate-frequency signal. On its frequency band, the output signal is a variable-frequency signal similarly as the first and the second intermediate-frequency signal. The power level of the output signal of the second frequency processing unit is increased by means of a power unit 114 to a desired transmission power level. The settling time of a signal to new frequencies can be made shorter by increasing the bandwidth of the passband of a loop filter 112, for instance. There are naturally limitations as regard to the broadening of the bandwidth. Increasing the bandwidth too much causes an excessive amount of phase error and frequency error to the output signal of the transmitter unit. Referring to Figure 1 , a detailed description of a preferred embodiment of the invention is given in the following in connection with Figure 2, the embodiment being typically applicable to the GSM-900 system. This preferred embodiment of the invention comprises corresponding matters as Figure 1 , but certain facts are described in more detail as they are in a typical preferred embodiment according to the invention. As a modulator, the digital synthesizer 100 comprises a frequency modulator which forms adjacent channels with a bandwidth of 40 kHz to a frequency range of 13 MHz to 20 MHz, so there are 175 channels altogether. The digital synthesizer 100 generates a first intermediate-frequency signal which has a bandwidth of 40 kHz and is located on one of the above mentioned channels. Only one signal is transmitted at a time. In the GSM system a signal is typically divided into eight time slots, and in different time slots the signal can be on different amplitude levels. The digital synthesizer determines which channel is used at each time. The signal is a variable-frequency signal such that a handover is performed at desired intervals, these intervals naturally having their minimum time slot restrictions. The digital synthesizer performs modulation and handovers on the basis of control received at the transmitter unit.

At the next signal processing stage the first intermediate-frequency signal at a frequency range of 13 to 20 MHz is converted into a second intermediate-frequency signal to a frequency range of 185 MHz to 192 MHz such that the first intermediate-frequency signal is mixed by the mixer 104 for example with a 172 MHz fixed-frequency signal which is generated by means of a first PLL synthesizer 200 which is the first frequency processing unit. The second intermediate-frequency signal with its total bandwidth of 7 MHz is a variable-frequency signal similarly as the first intermediate-frequency signal with the same total bandwidth. Thus, what differs these two signals is that the second intermediate-frequency signal is located at a frequency range of 185 MHz to 192 MHz.

The PLL synthesizer (Phase Locked Loop) comprises a feedback 110 which can convert a fixed-frequency signal with a desired frequency or a variable-frequency signal accurately into an output signal of the PLL synthesizer. Referring to Figure 3, the first PLL synthesizer 200 is described in the following. The first PLL synthesizer comprises a frequency oscillator 300, a first divider 302, a second divider 307, a phase comparator 306 and a loop filter 308. As a first frequency processing unit there is the first PLL synthesizer 200 (Phase Locked Loop) which is arranged to generate a fixed-frequency signal, such as a 172 MHz signal, from a frequency range of 100 MHz to 300 MHz. What differs the PLL synthesizer generating a fixed-frequency signal from the PLL synthesizer generating a variable-frequency signal is that during its entire operation the division numbers remain the same and the oscillation range of a voltage oscillator may be narrower than that of the PLL synthesizer generating a variable-frequency signal. The PLL synthesizer forming a variable-frequency signal is a phase-locked synthesizer performing frequency hopping.

Still referring to Figure 3, the divider 302 typically comprises a multiplier circuit. The division ratio of the dividers is set to a fixed value in order to generate a desired fixed-frequency signal to the output of the first PLL synthesizer. A first divider 302 divides the output signal of the first PLL synthesizer 200 by a desired value, whereafter the signal is transmitted to the phase comparator 306. The phase comparator is typically a PFD phase comparator (Phase-Frequency Detector) comparing both frequency and phase. The phase comparator compares the frequency of the output signal of the first PLL synthesizer and the frequency of the signal supplied from the feedback on the basis of the phase difference between the signals. On the basis of this difference, the frequency difference between the signals can be determined analogically. The phase comparator 304 comprises a charge pump. The fre- quency difference and the division numbers of the dividers determine the current value of a signal in current mode, the signal being formed by the charge pump.

In the loop filter 308 the signal in current mode is converted into a signal in current mode. The loop filter 308 is a filter of a low-pass type, which filters away the phase comparison frequency and its harmonic frequencies. The loop filter can also set the bandwidth of the PLL synthesizer feedback 110 as desired, adjust the slope of the passband of the feedback as desired, and also reduce phase noise.

The frequency oscillator 300 is a voltage-controlled oscillator the operation of which is controlled by a voltage-mode control signal to maintain the output signal of the first PLL synthesizer 200 as a fixed-frequency signal. If the control signal voltage remains constant, also the output signal frequency remains constant. As the control signal voltage increases, the output signal frequency increases correspondingly, and as the control signal voltage de- creases, the output signal frequency decreases correspondingly, and this can be understood as an implementation of positive polarity. This can also be done vice versa, i.e. by implementing negative polarity. In this opposite implementation, as the control signal voltage increases, the output signal frequency decreases, and as the control signal voltage decreases, the output signal frequency increases. By using the above manners, the voltage-controlled oscil- lator adjusts the fixed-frequency signal which is the output signal of the PLL synthesizer such that instead of the signal changes inside the PLL synthesizer the output signal remains at a desired frequency, e.g. at 172 MHz. A signal having the same frequency as the output signal is transmitted from the output 309 of the first PLL synthesizer to the feedback 110 where a second divider 307 divides the signal by a desired value. The above mentioned signal has thus the same frequency as the output signal, and it can also otherwise be similar to the output signal, depending on how the signal having the same frequency as the output signal is transmitted to the feedback 110. The above mentioned signal with the same frequency as the output signal is transmitted from the output 309 of the first PLL synthesizer to the feedback 110 by using a prior art method. The signal that is divided by the second divider is transmitted from the feedback to the phase comparator 306. The phase comparator compares the signal phase and thus the signal frequency with the first PLL synthesizer output signal received at the phase comparator. Returning to Figure 2, the mixer 104 typically comprises a multiplier circuit. The passband filter 106, which filters particularly interference signals that have been formed in the mixer, performs passband filtering for the second intermediate-frequency signal.

The second intermediate-frequency signal is called a reference sig- nal of the second PLL synthesizer 202 operating as a second frequency processing unit. The reference signal is the second PLL synthesizer output signal by which the operation of the second PLL synthesizer can be controlled in certain ways.

The second PLL synthesizer 202 converts the second intermediate- frequency signal into an output signal of the transmitter unit to the output 115 of the transmitter unit. The second PLL synthesizer generates the output signal in such a manner that it is on a transmission band width of 35 MHz at a transmission frequency range of 925 MHz to 960 MHz. The bandwidths of the output signal channels are spread to a fivefold width, i.e. to 200 kHz, com- pared to the bandwidths of the first and second intermediate-frequency signal channels of 40 kHz. The second PLL synthesizer 202 follows the frequency changes, i.e. frequency hopping, between various channels of the second intermediate-frequency signal such that the output signal changes its channel similarly as the second intermediate-frequency signal.

The second PLL synthesizer, which is shown in Figure 4, comprises a first divider 400 and a phase comparator 402, a loop filter 403, a frequency oscillator 404 and a second divider 406 located at a feedback 110. Since the bands are spread to a fivefold width, the division ratio of the dividers should correspondingly be five. The division ratio of the dividers 400, 406 is set to be five, as in Figure 4, for example, which means that the value of the first divider 400 is four and the value of the second divider 406 is twenty. The division ratio can also be other than five. In such a case, however, the frequencies of the intermediate-frequency signals in the GSM-900 system should be from different frequency ranges than is described in this preferred embodiment of the invention, with a division ratio of five. In the GSM-1800 or GSM-1900 systems, the division ratio of the dividers should be different than what it is in the GSM- 900 system.

The first divider 400 divides the second intermediate-frequency signal received at the second PLL synthesizer 202 by four such that the frequency of the second intermediate-frequency signal decreases to its fourth to a frequency range of 46.25 MHz to 48 MHz. After the division, the second intermediate-frequency signal is transmitted to the phase comparator 402 which compares the phase of the second intermediate-frequency signal with the phase of the signal supplied from the feedback. The phase comparator 402 is similar to the phase comparator 306 of the first PLL synthesizer 200. Phase changes are analogous to frequency changes, so it can be stated correspondingly that the phase comparator compares the frequencies of the above mentioned signals. The loop filter 403 is a low-pass type of filter which performs a current-voltage conversion and filters a signal with a phase comparison frequency and the harmonic signals thereof. The output signal of the loop filter is a voltage-mode control signal of the voltage-controlled frequency oscillator.

The frequency oscillator 404 of the second PLL synthesizer is a voltage-controlled oscillator comprising a frequency hopping synthesizer. The frequency hopping synthesizer forms a desired transmission band, which is 35 MHz in this embodiment example. The frequency hopping synthesizer can form 175 channels with parallel frequency ranges and a 200 kHz bandwidth for the above mentioned transmission band to the transmitter unit output 115. These channels correspond to the first and thus the second intermediate- frequency signal channels with a 40 kHz bandwidth that are formed by the digital synthesizer. In addition, the frequency hopping synthesizer performs 'frequency hopping' of the output signal, i.e. transfers the output signal from one channel to another in a voltage-controlled manner, based on how the second intermediate-frequency signal received at the second PLL synthesizer changes the channel. This is performed by means of a control signal of the frequency oscillator 404 in the following manner: if the control signal voltage remains constant, the frequency of the corresponding output signal remains constant, i.e. the channel remains the same. If the control signal voltage increases, the frequency of the corresponding output signal increases. The output signal changes its channel according to the fact how much the voltage has increased. If the control signal voltage decreases, also the frequency of the corresponding output signal decreases. The output signal changes its channel according to the fact how much the voltage has decreased. As explained in connection with the first PLL synthesizer, the above mentioned changes between the control signal and the output signal can also relate to each other in the opposite way. The output signal changes its channels in a similar manner as the first intermediate-frequency signal, formed by the digital synthesizer, and the second intermediate-frequency signal change their channels.

Still referring to Figure 4, the output signal is transmitted in the second PLL synthesizer 202 to the output 115. The power level of the output signal is increased by means of the power unit 114 to the desired transmission power level in the output 115. The signal with the same frequency as the output signal is also transmitted in the second PLL synthesizer 202 to the feedback 110. Thus, the signal has the same frequency as the output signal and it can also otherwise be similar to the output signal, depending on how the signal with the same frequency as the output signal is transmitted to the feedback 110. The signal with the same frequency as the output signal is transmitted from the transmitter unit output 115 to the feedback 110 in some prior art manner. In the feedback 110 the signal is transmitted to the second divider 406 which divides the signal by twenty. Thus a signal, which is on a channel of a transmission frequency range of 925 MHz to 960 MHz, can be divided on the corresponding channel of a frequency range of 46.25 MHz to 48 MHz into a signal which is a signal supplied from the feedback to the phase comparator 402. The phase comparator compares the signal supplied from the feedback with the second intermediate-frequency signal received at the second PLL synthesizer in order to form a control signal for the frequency oscillator 404, as described above. Naturally, the numerical values given above in connection with the description of the preferred embodiment of the invention are approximations. In addition, only one preferred embodiment of the invention is described above, but various embodiments can be implemented, for instance, by setting the frequency values as desired. In the solution according to the invention, the fixed-frequency signal has the desired frequency. The frequency varies within a frequency range of 10 MHz to 5 GHz. Preferably the frequency varies from 150 MHz to 200 MHz. The first intermediate-frequency signal has the desired frequency. The frequencies of the first intermediate-frequency signal vary between 1 MHz and 1 GHz. Preferably the frequencies are between 10 MHz and 100 MHz. The second intermediate-frequency signal has the desired frequency. The frequencies of the second intermediate-frequency signal vary within a frequency range of 30 MHz to 5 GHz. Preferably the frequencies vary from 100 MHz to 1 GHz. The output signal has the desired frequency. The frequencies of the output signal vary between 100 MHz and 8 GHz and preferably they are between 700 MHz and 2 GHz.

Although the invention has been described above with reference to the example according to the attached drawings, it is obvious that the invention is not restricted thereto, but may be modified in a variety of ways within the scope of the inventive concept disclosed in the attached claims.

Claims

1. A method of implementing the transmitter operation of a digital data transmission system, which method comprises the steps of converting an information signal to be transmitted into a first intermediate-frequency signal such that the first intermediate-frequency signal is processed to a desired frequency band, and converting the first intermediate-frequency signal into a variable-frequency signal on the above mentioned frequency band and filtering away interference signals, characterized by mixing the first intermediate-frequency signal with a fixed-frequency signal in order to generate a second intermediate-frequency signal such that the second intermediate-frequency signal is a variable-frequency signal similarly as the first intermediate-frequency signal, converting the second intermediate-frequency signal into an output signal to a transmission band width which is in its entirety at a higher fre- quency range than the second intermediate-frequency signal, and converting the second intermediate-frequency signal into the output signal such that the output signal is adapted to frequency changes of the second intermediate-frequency signal.

2. A method as claimed in claim 1, characterized by imple- menting the transmitter operation in a transmitter unit of a base station.

3. A method as claimed in claim 1, characterized by generating the fixed-frequency signal in a first PLL synthesizer (200).

4. A method as claimed in claim 1, characterized by mixing the fixed-frequency signal with the information signal to be transmitted by a mixer (104) to generate the second intermediate-frequency signal.

5. A method as claimed in claim 1, characterized in that the broadening of the bandwidth of the intermediate-frequency signal to a desired transmission band width and the adaptations to the frequency changes of the intermediate-frequency signal are performed in a second PLL synthesizer (202).

6. A method as claimed in claim 1, characterized by the signal being a variable-frequency signal such that it moves to channels of different frequency ranges at desired intervals.

7. A method as claimed in claim 3, characterized by the frequency of the fixed-frequency signal being 10 MHz to 5 GHz.

8. A method as claimed in claim 7, characterized by the frequency being preferably 150 MHz to 200 MHz.

9. A method as claimed in claim 1, characterized by the frequencies of the first intermediate-frequency signal being from a frequency range of 1 MHz to 1 GHz.

10. A method as claimed in claim 9, characterized by the frequencies being preferably from a frequency range of 10 MHz to 100 MHz.

11. A method as claimed in claim 1, characterized by the frequencies of the second intermediate-frequency signal being from a fre- quency range of 30 MHz to 5 GHz.

12. A method as claimed in claim 11, characterized by the frequencies being preferably from a frequency range of 100 MHz to 1 GHz.

13. A method as claimed in claim 1, characterized by the frequencies of the output signal being from a frequency range of 100 MHz to 8 GHz.

14. A method as claimed in claim 13, characterized by the frequencies being preferably from a frequency range of 700 MHz to 2 GHz.

15. An arrangement for implementing a transmitter unit of a digital data transmission system, which arrangement comprises a digital synthesizer (100) for converting an information signal to be transmitted into a first intermediate-frequency signal with a variable frequency to a desired bandwidth, and a passband filter (200) for filtering away interference signals, characterized in that the arrangement comprises a first frequency processing unit (102) generating a fixed-frequency signal, a mixer (104) for mixing the above mentioned fixed-frequency signal with the first intermediate-frequency signal in order to form a second intermediate-frequency signal such that the second intermediate-frequency signal is a variable-frequency signal similarly as the first intermediate-frequency signal, a second frequency processing unit (108) for converting the second intermediate-frequency signal into an output signal to a transmission band width which is in its entirety at a higher frequency range than the second intermediate-frequency signal, and the second frequency processing unit (108) for converting the sec- ond intermediate-frequency signal into the output signal such that the output signal is adapted to frequency changes of the second intermediate-frequency signal.

16. An arrangement as claimed in claim 15, characterized in that the transmitter unit is a transmitter unit of a base station.

17. An arrangement as claimed in claim 15, characterized in that the first frequency processing unit (102) is a first PLL synthesizer (200).

18. An arrangement as claimed in claim 15, characterized in that the second frequency processing unit (108) is a second PLL synthesizer (202).

19. An arrangement as claimed in claim 15, characterized in that the arrangement is adapted to generate the variable-frequency signal such that the signal moves to channels of different frequency ranges at desired intervals.

20. An arrangement as claimed in claim 15, characterized in that the arrangement comprises the first frequency processing unit (102) adapted to generate a fixed-frequency signal the frequency of which is from a frequency range of 10 MHz to 5 GHz.

21. An arrangement as claimed in claim 20, characterized in that the frequency is preferably from a frequency range of 150 MHz to 200 MHz.

22. An arrangement as claimed in claim 15, characterized in that the arrangement is adapted to generate the first intermediate-frequency signal the frequencies of which are from a frequency range of 1 MHz to 1 GHz.

23. An arrangement as claimed in claim 22, characterized in that the frequencies are preferably from a frequency range of 10 MHz to 100

MHz.

24. An arrangement as claimed in claim 15, characterized in that the arrangement is adapted to generate the second intermediate- frequency signal the frequencies of which are from a frequency range of 30 MHz to 5 GHz.

25. An arrangement as claimed in claim 24, characterized in that the frequencies are preferably from a frequency range of 100 MHz to 1 GHz.

26. An arrangement as claimed in claim 15, characterized in that the arrangement is adapted to generate the output signal the frequencies of which are from a frequency range of 100 MHz to 8 GHz.

27. An arrangement as claimed in claim 26, characterized in that the frequencies are preferably from a frequency range of 700 MHz to 2 GHz.