WO2001039562A1

WO2001039562A1 - Printed circuit board employing lossy power distribution network to reduce power plane resonances

Info

Publication number: WO2001039562A1
Application number: PCT/US2000/031686
Authority: WO
Inventors: Istvan Novak
Original assignee: Sun Microsystems, Inc.
Priority date: 1999-11-23
Filing date: 2000-11-17
Publication date: 2001-05-31
Also published as: US6753481B2; US20040163846A1; US20030015344A1; US6441313B1; EP1232679A1; ATE310374T1; EP1232679B1; DE60024128D1; AU1921701A; DE60024128T2; US6894230B2

Abstract

An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board (10) includes a lossy power distribution network formed by a pair of parallel planar conductors (16, 18) separated by a dielectric layer (24). The pair of parallel planar conductors (16, 18) includes a first power supply plane (16) suitable for use, for example, as a ground plane and a second power supply plane (18) suitable for use, for example, as a power plane (e.g., VCC). The dielectric layer (24) has a loss tangent value of at least 0.2, and preferably of at least 0.3. In one embodiment, the dielectric material (24) between the power planes could have a frequency dependent loss tangent, such that a loss tangent value of 0.3 is achieved at and above the lowest resonance frequency of the planes. Due to the relatively large loss tangent characteristic of the dielectric layer (24) separating the power supply planes (16, 18), the electrical impedance characteristics associated with the power planes may be stabilized, and power plane resonances may be reduced. The printed circuit board (10) may also include one or more signal layers (14, 20) separated from the power planes (16, 18) by respective dielectric layers (22, 26). The dielectric layers (22, 26) separating the signal layers from the power planes or other signal layers may be associated with much lower loss tangent values, such as in the range of 0-0.05. In this manner, high frequency losses associated with the signal traces may be kept relatively low. In another embodiment, power plane resonances are suppressed by decreasing the thickness of the dielectric material (24) between the power supply planes (16, 18) to less than 0.5 mils. For example, in one embodiment, the plane separation is preferably reduced to less than 0.2 mils such as, for example, 0.1 mils. In embodiments where the plane separation approaches 0.1 mils or less, plane resonances may be substantially suppressed.

Description

TITLE: PRINTED CIRCUIT BOARD EMPLOYING LOSSY POWER DISTRIBUTION NETWORK TO REDUCE POWER PLANE RESONANCES

BACKGROUND OF THE INVENTION

1 Field of the Invention

This invention relates to electronic systems, and more particularly to power distribution networks embodied within printed circuit boards and semiconductor

ice packages having continuous planar conductors

2. Description of the Related Art

Electronic systems typically employ several different types of electrical interconnecting apparatus having planar layers of electrically conductive material (t e., planar conductors) separated by dielectπc layers A portion of the conductive layers may be patterned to form electrically conductive signal lines or "traces" Conductive traces m different layers (I e.. on different levels) are typically connected using contact structures formed in openings in the dielectπc layers (i.e., vias) For example, printed circuit boards typically have several layers of conductive traces separated by dielectπc layers. The conductive traces are used to electrically interconnect terminals of electronic devices mounted upon the PCB. Similarly, semiconductor device packages often have several layers of conductive traces separated by dielectric layers to electronically connect bonding pads of an integrated circuit to terminals (e.g.. pms or leads) of the device package

Signals in digital electronic systems typically carry information by alternating between two voltage levels (i.e., a low voltage level and a high voltage level). A digital signal cannot transition instantaneously from the low voltage level to the high voltage level, or vice versa. The finite amount of time during which a digital signal transitions from the low voltage level to the high voltage le\ el is called the rise time of the signal. Similarly, the finite amount of time during which a digital signal transitions from the high voltage level to the low voltage level is called the fall time of the signal.

Digital electronic systems are continually bemg proαuced which operate at higher signal frequencies (l e , higher speeds) In order for the digital signals within such

stems to remain stable for appreciable periods of time between transitions, the rise and fall times of the signals must decrease as signal frequencies increase. This decrease m signal transition times (i.e , rise and fall times) creates several problems withm digital electronic systems, including signal degradation due to reflections, pow er supply "droop", ground "bounce^", and increased electromagnetic emissions.

A signal driven upon (i.e., launched) from a source end of a conductive trace suffers degradation when a portion of the signal reflected from a load end of the trace arm es at the source end after the transition is complete ( I e . after the rise time or fall time of the signal) A poπion of the signal is reflected back from the load end of the trace when the input impedance of the load does not match the characteristic impedance of the trace When the length of a conductive trace is greater than the signal transition time (1 e.. the rise or fall time) divided by about 20 times the delay per unit length along the trace, the effects of reflections upon signal integrity (i.e . transmission line effects) should be considered. If necessary, steps should be taken to minimize the degradations of signals conveyed upon the trace due to reflections. The act of altering impedances at the source or load ends of the trace in order to reduce signal reflections is referred to as ' terminating" the trace For example, the mput impedance of the load may be altered to match the charactenstic impedance of the trace in order to prevent signal reflection As the transition time (1 e , the πse or fall tune) of the signal decreases so does the length of trace which must be terminated in order to reduce signal degradation A digital signal alternating between the high and low voltage levels includes contributions from a fundamental smusoidal frequency (1 e , a first harmonic) and integer multiples of the first harmonic As the rise and fall times of a digital signal decrease, the magnitudes of a greater number of the integer multiples of the first harmonic become significant As a general rule, the frequency content of a digital signal extends to a frequency equal to the reciprocal of π times the transition time (1 e , πse or fall time) of the signal For example, a digital signal with a 1 nanosecond transition time has a frequency content extending up to about 318 MHz

All conductors have a certain amount of inductance The voltage across the inductance of a conductor is directly proportional to the rate of change of current through the conductor At the high frequencies present m conductors carrying digital signals having short transition times, a significant voltage drop occurs across a conductor having even a small inductance A power supply conductor connects one terminal of an electπcal power supply to a power supply terminal of a device, and a ground conductor connects a ground terminal of the power supply to a ground terminal of the device When the device generates a digital signal havmg short transition times, high frequency transient load currents flow in the power supply and ground conductors Power supply droop is the term used to descπbe the decrease m voltage at the power supply terminal of the device due to the flow of transient load current through the mductance of the power supply conductor Similarly, ground bounce is the term used to descnbe the increase in voltage at the ground terminal of the device due to the flow of transient load current through the mductance of the ground conductor When the device generates several digital signals havmg short transition times simultaneously, the power supply droop and ground bounce effects are additive Sufficient power supply droop and ground bounce can cause the device to fail to function correctly

Power supply droop is commonly reduced by arranging power supply conductors to form a cπsscross network of mtersectmg power supply conductors (l e , a power supply gnd) Such a gnd network has a lower inductance, hence power supply droop is reduced A contmuous power supply plane may also be provided which has an even lower mductance than a grid network Placmg a "bypass" capacitor near the power supply terminal of the device is also used to reduce power supply droop The bypass capacitor supplies a substantial amount of the transient load current, thereby reducing the amount of transient load current flowing through the power supply conductor Ground bounce is reduced by usmg a low mductance ground conductor gnd network, or a contmuous ground plane havmg an even lower amount of mductance Power supply and ground grids or planes are commonly placed in close proximity to one another m order to further reduce the mductances of the grids or planes

Electromagnetic interference (EMI) is the term used to descπbe unwanted interference energies either conducted as currents or radiated as electromagnetic fields High frequencv components present within circuits producing digital signals havmg short transition times may be coupled mto nearby electronic systems (e g , radio and television circuits), disrupting proper operation of these systems The United States Federal Communication Commission has established upper limits for the amounts of EMI products for sale in the United States may generate Signal circuits form current loops which radiate magnetic fields m a differential mode. Differential mode EMI is usually reduced by reducmg the areas proscnbed by the circuits and the magnitudes of the signal currents. Impedances of power and ground conductors create voltage drops along the conductors, causmg the conductors to radiate electric fields in a common mode. Common mode EMI is typically reduced by reducmg the impedances of the power and ground conductors. Reducing the impedances of the power and ground conductors thus reduces EMI as well as power supply droop and ground bounce.

Within the wide frequency range present within electronic systems with digital signals having short transition times, the electncal impedance between any two parallel conductive planes (e.g , adjacent power and ground planes) may vary widely The parallel conductive planes may exhibit multiple electncal resonances, resultmg m alternating high and low impedance values. Parallel conductive planes tend to radiate a significant amount of differential mode EMI at their boundaπes (I e., from their edges). The magnitude of differential mode EMI radiated from the edges of the parallel conductive planes vanes with frequency and is directly proportional to the electrical impedance between the planes.

Fig. 1 is a perspective view of a pair of 10 m. x 10 m. square conductive planes separated by a fiberglass- epoxy composite dielectric layer. Each conductive plane is made of copper and is 0.0014 m. (1 4 mils) thick. The fiberglass-epoxy composite layer separatmg the planes has a dielectric constant of 4.0 and is 0.004 m (4 mils) thick. Fig. 2 is a graph of the magnitude of the simulated electrical impedance between the pair of rectangular conductive planes of Fig. 1 (log₁₀ scale) versus the frequency of a voltage between the planes (log₁₀ scale). The graph was created by modelmg each square inch of the pair of conductive planes as a matnx of transmission line segments. The impedance value was computed by simulating the application of a 1 ampere constant current between the centers of the rectangular planes, varying the frequency of the current, and determining the magnitude of the steady state voltage between the centers of the rectangular planes.

As shown m Fig. 2, the magnitude of the electncal impedance between the parallel conductive planes of Fig. 1 vanes widely at frequencies above about 20 MHz The parallel conductive planes exhibit multiple electncal resonances at frequencies between 100 MHz and 1 GHz, resultmg m alternating high and low impedance values The parallel conductive planes of Fig. 1 tend to radiate substantial amounts of EMI at frequencies where the electrical impedance between the planes anywhere near their penpheπes is high.

It would thus be desirable to provide a power distnbution network wherein the electncal impedance between parallel conductive planes may be stabilized. Such a network would reduce power supply droop, ground bounce, and the amount of electromagnetic energy radiated from the edges of the planes. Such impedance stabilization may also reduce the need for bypass capacitors.

SUMMARY OF THE INVENTION

The problems outlmed above are m large part solved by an interconnecting apparatus employing a lossy power distnbution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer The pair of parallel planar conductors mcludes a first power supply plane suitable for use, for example, as a ground plane and a second power supply plane suitable for use, for example, as a power plane (e.g , VCC) The dielectric WO 01/39562 PCTVUSOO/31686

layer has a loss tangent value of at least 0 2. and preferably of at least 0 3 In one embodiment, the dielectric material between the power planes could have a frequency dependent loss tangent, such that a loss tangent value of 0 3 is achieved at and above the lowest τesonance frequency of the planes Due to the relatively large loss tangent characteristic of the dielectric layer separating the power supply planes, the electrical impedance charactenstics associated with the power planes may be stabilized, and power plane resonances may be reduced The printed circuit board may also mclude one or more signal layers separated from the power planes by respective dielectric layers The dielectric layers separatmg the signal layers from the power planes or other signal layers may be associated with much lower loss tangent values, such as in the range of 0-0 05 In this manner, high frequency losses associated with the signal traces may be kept relatively low In another embodiment, power plane resonances are suppressed by decreasmg the thickness of the dielectric material between the power supply planes to less than 0 5 mils For example, m one embodiment, the plane separation is preferably reduced to less than 02 mils such as, for example, 0 1 mils In embodiments wheie the plane separation approaches 0 1 mils or less, plane resonances may be substantially suppressed

In various embodiments, the power distribution network of a pπnted circuit board or a semiconductor package interconnect may require relatively large cunents For example, it is not uncommon for systems implemented on printed circuit boards to reach DC current requirements of 100 amps or more Thus, relatively heavy copper or other conductor layers may be required to handle the large currents Since a structure that includes very heavy conductive layers on a very thm dielectnc layer may be associated with manufacturing and handlmg problems, a power distribution network may be provided within a printed circuit board or package interconnect in which numerous, relatively thm conductive layers are separated by relatively thm dielectnc layers For example, rather than employmg a smgle pair of relatively thick (e g , 1-2 mils) conductor layers separated by a relatively thick (e g , 1-2 mils) dielectπc layer in the power distnbution network of a printed circuit board, a relatively large number of relatively thm (e g , 05- 3 mils) dielectric layers with relatively thm (e g , 0 1-0 2 mils) conductor layers on each side Alternating conductive layers m the stack up are connected by vias, every second of them connecting to one polarity (e g , ground) and every other connecting to the other polarity (e g , VCC) In this manner, the power distribution network may have a relatively low DC resistance to support relatively high cunents, while attaining a relatively low high frequency impedance without resonances

In yet another embodiment, a relatively thin conductive layer is provided between a pair of relatively thick conductive layers A first relatively thick dielectnc layer is provided between one of the thick conductive layers and the thm conductive layer, while a relatrv ely thm dielectπc layer is provided between the other relatively thick copper conductive layer and the thm conductive layer A PCB core constructed accordmg to this embodiment may be associated with relatively good mechanical strength and stability and may be capable of supporting relatively high cunents The structure may further be associated with a relatively low high-frequency impedance without resonances The thm conductive layer may further be formed in a uniform pattern to create fuses which open if a short occurs through a portion of the thm dielectnc BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon readmg the following detailed descπption and upon reference to the accompanying drawings in which.

Fig 1 is a perspective view of a pair of 10 m. x 10 in. square conductive planes separated by a fiberglass- epoxy composite dielectric layer;

Fig 2 is a graph of the magnitude of the simulated electrical impedance |Z| (log,₀ scale) between the pair of rectangular conductive planes of Fig 1 versus the frequency of a voltage (log,₀ scale) between the planes;

Fig. 3 is a perspective view of one embodiment of an electncal interconnecting apparatus including a set of planar electrical conductois separated by dielectnc layers, Figs. 4A-4I are graphs illustrating the magnitude of simulated electncal impedance between the parallel conductive planes of Fig. 3 versus frequency for different loss tangent values of a dielectnc layer.

Figs. 5A-5H are graphs of the magnitude of the simulated electncal impedance between the conductive planes of Fig 3 versus frequency for different plane separations

Figs. 6A-6E are graphs of the magnitude of the simulated electncal impedance between the conductive planes of Fig 3 versus frequency for different dielectnc and conductor thickness values.

Fig 7 is a cross-sectional view of another embodiment of a powe distribution network employmg numerous parallel power and ground planes.

Fig. 8 is a cross-sectional view of yet another embodiment of a power distribution network employmg a thm dielectric layer to reduce resonance. Fig 9 is a top view of a thm conductive layer where small regions of the layer are coupled to the rest of the plane with short narrow bndges to form a fused structure.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be descπbed m detail. It should be understood, however, that the drawings and detailed descnption thereto are not intended to limit the invention to the particula form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the spirit and scope of the present mvention as defined by the appended claims

DETAILED DESCRIPTION OF THE INVENTION

Fig. 3 is a perspective view of one embodiment of an electncal interconnecting apparatus 10 mcludmg a set of planar electncal conductors illustrated by a first signal plane 14, a ground plane 16, a power plane 18, and a second signal plane 20. Additional layers (e.g , additional signal layers) may be stacked on top of or beneath the illustrated structure, as desired. Interconnecting apparatus 10 may be, for example, a prmted circuit board or an interconnect substrate of a semiconductor device package Power plane 18 and ground plane 16 are continuous across at least a portion of interconnecting apparatus 10. First signal plane 14 and second signal plane 20 are patterned mto electncally conductive traces to form signal Imes that electronically connect to components or contact pads of the interconnecting apparatus. First signal plane 14 and ground plane 16 are separated

a first dielectπc layer 22 Ground plane 16 and power plane 18 are separated by a second dielectric layer 24 Power plane 18 and second signal plane 20 are separated by a third dielectnc layer 26. During use of interconnecting apparatus 10, power plane 18 is connected to a power terminal of an electrical power supply, and ground plane 16 is connected to a ground terminal of the power supply. Ground plane 16 and power plane 18 are each generally referred to as a power supply plane. In embodiments where interconnecting apparatus is a printed circuit board, electronic devices 19 (illustrated in phantom) mounted on the surface of the structure and receive electrical power via ground plane 16 and power plane 18. In embodiments where interconnecting apparatus is an interconnect substrate of a semiconductor package, contact pads 21 (also shown in phantom) associated with signal layer 14 may provide electrical connection (including power) to conesponding pads of an integrated circuit contact pads (not shown) on the opposite side of the apparatus (e.g., formed as a portion of signal layer 20) may provide connection to terminals (such as BGA leads) of a device package.

It is customary to express the dielectric and conductive losses of signal traces by the following formula:

where A is the attenuation of the matched-terminated trace in dB,

Rs is the series attenuation at the required frequency, Gd is the parallel conductance of the dielectrics at the required frequency, Zo is the characteristic impedance of trace.

Rs is the total series resistance of the conductor at the frequency of interest, determined by the cross section of conductor. At higher frequencies, the resistance of conductor increases, because current tends to flow on the surface, leaving for current conduction only an effective channel of depth, which is proportional to the inverse square root of frequency. This effective depth is called the skin depth, and at a first approximation is expressed as:

where δ is the skin depth, f is the frequency of interest, σ is the conductivity of conductor, μ is the permeability of mconductor.

The dielectric losses are usually expressed in terms of loss tangent, which is the ratio of conductance and capacitive reactance. From this relationship, the Gd (frequency dependent) conductance is simply GD=loss_tangent*omega*C, where omega is the radian frequency The loss tangent is usually a weak function of frequency, and therefore the parallel conductance mcreases approximately linearly with frequency

Though the above expressions are usually valid and are applied mostly to signal traces under some further restnctive conditions, the same formulas may be applied to power-distnbution planes. This approach is validated by the fact that popular simulation methods use matnces of one-dimensional transmission Imes (traces) to obtam the response of two-dimensional power planes

From the above loss equation, the required loss tangent to achieve the suppression of resonances can be calculated, for mstance, by equating the low-frequency equivalent charactenstic impedance of the planes (sqrt(L/C) and the mverse of the parallel loss conductance (Gd) at the lowest resonance frequency (approximately twice the mverse of the propagation delay along one side of the planes) By domg so, a required loss tangent as l/PI-0 3 is obtamed This result is independent of the size and separation of the planes and of the dielectnc constant of the matenal, and depends only on the ratio of mverse loss conductance and charactenstic impedance (here set to one) at the specified frequency

Figs 4A-4I are graphs illustrating the magnitude of simulated electncal impedance between the parallel conductive planes of Fig 3 versus frequency for different loss tangent values of dielectπc layer 24 The data depicted m the graphs was obtamed assuming 10 inch by 10 mch square parallel planes, usmg 0 7-mιl copper conducting planes, a lossy dielectnc with a dielectπc constant of 4, and 2 mils of plane separation. The impedance profiles are shown with the following dielectric loss tangent values:

0.01 (Fig. 4A)

0.3 (Fig. 4E)

0 6 (Fig. 4G)

As illustrated by Figs. 4A-4I, the ripples m the impedance profile gradually decreases as the loss tangent reaches a value of 0.3. There is no sigmficant further change m the impedance profile as the loss tangent mcreases beyond 0.3.

In accordance, m one embodiment of the electncal interconnecting apparatus illustrated by Fig. 3, the dielectnc layer 24 separating ground plane 16 and power plane 18 is provided with a loss tangent of at least 0 2, and preferably of 0.3 or higher for frequencies at or above the lowest resonance frequency of the planes. In this manner, power plane resonances may be reduced, and low DC resistance may be attained.

It is noted that dielectπc materials commonly used m printed circuit boards have a loss tangent typically of only a few percent (e.g., 0.02) at most. In one embodiment, to keep high frequency signal losses associated with the signal traces of first signal plane 14 and second signal plane 20 relatively low, dielectπc layers 22 and 26 may be formed usmg such a common printed circuit board dielectnc matenal havmg a relatively low loss tangent of approximately 0 01-0 02 (or generally within the range of between 0 00 and 0 05)

Senes conductor losses may also help to suppress resonances In general, for signal interconnects, a given series conductor loss provides higher attenuation at high frequencies if the characteristic impedance of the interconnect is low Thus, m one embodiment, to lower the charactenstic impedance, the separation between ground plane 16 and power plane 18 is reduced Figs 5 A-5H are graphs of the magnitude of the simulated electrical impedance between the conductive planes of Fig 3 versus frequency for different plane separations The profiles depicted m Figs 5A-5H agam assume 10 mch by 10 mch square parallel planes, with 0 7-rml copper and a lossless dielectnc havmg a dielectnc constant of 4 The impedance profiles are depicted for the followmg dielectπc thicknesses

0 2 mil (Fig 5F)

It is evident from Figs 5A-5H that with a plane separation approachmg 0 1 mil and less, the plane resonances are almost totally suppressed It is noted that the thinnest dielectric commonly used m modern printed circuit boards is approximately 2-mιls (for example, a ZBC2000 core) However, as depicted m Fig 5C, the impedance profile associated with a 2-rmls dielectnc thickness exhibits relatively large resonances Accordmgly, a printed circuit board havmg a power distnbution network as illustrated m Fig 3 is provided where the thickness of dielectric layer 24 is at most 0 5 mil, and is preferably 0 1 mil or less

Resonances may also be suppressed by reducmg the thickness of the conductive layers Figs 6A-6E are graphs of the magnitude of the simulated electrical impedance between the conductive planes of Fig 3 versus frequency for different dielectnc and conductor thicknesses The profiles depicted in Figs 6A-6E agam assume 10 mch by 10 mch square parallel planes, with a lossless dielectnc havmg a dielectnc constant of 4 The impedance profiles are depicted for the followmg dielectπc and conductor thicknesses 2 mils dielectnc, 0 1 mils copper (Fig 6A) 0 2 mils dielectnc, 0 2 mils copper (Fig 6B) 0 2 mils dielectnc, 0 1 mils copper (Fig 6C) 0 1 mils dielectric, 0 1 mils copper (Fig 6D) 0 05 mils dielectnc, 0 05 mils copper (Fig 6E)

It is noted that the amount of required copper (or other conductor) m the planes may be dictated by the DC current requirements With system currents reaching 100 amps or more, sometimes greater than one ounce of copper (approximately 1 2 mils) may be required to guarantee good power distribution The use of very heavy copper or conductor layers on very thm dielectrics, however, may create manufacturing and handlmg problems. Thus, as illustrated m Fig 7, m one embodiment a power distnbution network formed by a smgle ground plane and a smgle power plane may be replaced by multiple thm (e.g . 0 2 mil or less) conductor layers in parallel each with proportionally less conductive matenal m each layer, and with a thm (e g , 0 2 mil or less) dielectnc layer between each conductor layer In Fig. 7, a plurality of alternating ground planes 60 and power planes 62 are separated by respective thm dielectric layers 64 To ensure resonance suppression, the thickness of each power supply plane 60 and 62 is no more than 0.5 mil. For example, m one embodiment, each conductive layer 60 and 62 formed by copper has a thickness of 0.1 mil. Additionally, each dielectnc layer 64 has a thickness of no more than 0.5 mil. The ground planes 60 are electncally interconnected by a plurality of vias 66, and the power planes 62 are electncally interconnected by a plurality of vias 68 It is noted that clearance antipads may be etched m the conductive layers at respective locations of ground planes 60 and power plane 62 to prevent shorting. More particularly, to prevent vias 66 from providing electncal connections to power planes 62, clearance antipads may be provided at appropriate locations m each power plane 62 to avoid such contact Similar clearance antipads may be provided within ground planes 60 It is noted that additional v s (not shown) for interconnecting vanous signal layers may also be incorporated within the structure of Fig. 7, as desired.

Fig. 7 further illustrates additional dielectnc layers 70 which separate the power distnbution network (formed by the alternating ground and power planes 60 and 62) from signal layers 72. In one embodiment, the thickness of dielectπc layers 70 is at least 1 mil to keep high frequency signal losses relatively low The power distribution network as illustrated m Fig 7 may advantageously reduce power supply resonances while allowing for relatively high cunent capabilities and avoidmg manufacturing and handlmg problems For example, consider a situation m which a 2 mil dielectnc layer with one ounce (1.2 mils) copper planes on each side is replaced with 11 parallel layers of 0.2 mil dielectnc with 0.1 mil copper layers on each side. The ongmal structure (havmg a 2 mil dielectnc layer with one ounce [1.2 mils] copper planes on each side) has a thickness of 4 4 mils, and an impedance m the 10-1000 MHz range of 8-500 milliohms with resonance peaks and dips. A structure embodied accordmg to Fig 7 havmg eleven .2 mil thick dielectric layers with 0 1 mil copper on each side has approximately the same DC resistance, but its high frequency impedance m the same 10-1000 MHz range may be below 3 milliohms without resonances

Yet another embodiment is illustrated in Fig. 8 In Fig. 8, a power distribution network mcludes two relatively thick (e.g., each bemg at least 1 0 mil thick, such as 1 2 mils) conductive layers 74 and 76 to allow for relatively high DC currents A third, relatively thm (e.g, 0.5 mil or less, such as .1 mil), conductive layer 78 is further provided, with a thm (e g, 0.5 mil or less, such as .1 mil) dielectric layer separatmg conductive layers 74 and 78, and a relatively thick (e g, at least 1 mil) dielectnc layer 82 separating conductive layers 76 and 78. A via 84 electrically interconnects conductive layers 76 and 78 Conductive layers 74 and 76 in conjunction with dielectπc layer 82 provides sufficient copper weight for low resistance and high current capability, and also provides for mechanical strength and protects the thm inner layers 78 and 80 The thm conductive layer 78 and dielectnc layer 80 provide for low mductance and loss, efficiently suppressmg plane resonances A via 84 is provided to interconnect conductive layers 76 and 78 It is noted that the layered structure of Fig. 8 may be formed before (and mdependent of) the incorporation of the vias (such as via 84) which interconnect planes 76 and 78 No antipads internal to the structure need to be mcorporated. only the outer layer (conductor 74) needs to be provided with an antipad (or similar isolation) to provide isolation from the vias It is also noted that m an alternative embodiment, an additional thm (e g , 0 5 mil or less, such as 1 um ) conductor layer and an additional thm (e g , 0 5 mil or less, such as 1 um ) dielectnc layer could be mcorporated between dielectric layer 82 and conductive layer 76 to create a symmetric stack-up structure

A further advantage of the structure illustrated m Fig 8 may be achieved by employmg a "fused" construction to deal with local defects or shorts For example, as illustrated m Fig 9, a uniform pattern may be formed on the thm conductive layer 78, where small regions 90 of the layer are coupled to the rest of the plane with short narrow bπdges 92 Slots 94 which are removed or etched away portions of the conductive layer separate regions 90 If a short occurs due to a failure or defect m the thm dielectnc associated with a particular region 90, the narrow bndges act like a fuse and opens This allows the remamder of the conductive plane 78 the plane may function properly The shape and size of the regular pattern may have forms other than that shown m Fig 9 For frequencies up to a few GHz, a slot dimension of approximately 100 mils long and 5 mils wide with a 5 mil gap between adjacent slots may be sufficient Embodiments employmg such a fused structure may require dielectπc mateπals which will not carbonize or create conductive particles upon arching

While the present mvention has been descnbed with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited Any vaπations, modifications, additions and improvements to the embodiments descnbed are possible These vanations, modifications, additions and improvements may fall within the scope of the mvention as detailed within the followmg claims

Claims

WHAT IS CLAIMED IS:

1 A prmted circuit board compnsmg a first conductive layer formmg a first power supply plane, a second conductive layer formmg a second power supply plane; a first dielectπc layer separatmg the first and second conductive layers, a third conductive layer; and a second dielectπc layer separatmg said second and third conductive layers, wherem said first dielectπc layer has a thickness of no more than 0 5 mils

2. The pπnted circuit board as recited m Claim 1 wherem the second dielectric layer has a thickness of at least 1 mil

3 The pπnted circuit board as recited m Claim 1 wherem said first dielectric layer has a thickness of no more

4 The pπnted circuit board as recited m Claim 1 further compnsmg a via that electncally interconnects said second conductive layer and said third conductive layer

5 The prmted circuit board as recited m Claim 1 wherem the second conductive layer has a thickness of no more than 0.5 mils.

6 The prmted circuit board as recited m Claim 1 wherem the second conductive layer has a thickness of no more than 0 2 mil

7 The prmted circuit board as recited m Claim 4 wherem the second dielectric layer has a thickness of 1 mil or greater

8 A prmted circuit board compnsmg a first conductive layer formmg a first power supply plane; a second conductive layer formmg a second power supply plane; a first dielectnc layer adjacent to and separating the first and second conductive layers, a second dielectric layer adjunct to said second conductive layer, a third conductive layer formmg a third power supply plane, wherem the third conductive layer is adjacent to said second dielectnc layer, a fourth conductive layer forming a fourth power supply plane, a third dielectπc layer adjacent to and separatmg the third and fourth conductiv e layers

9. The printed circuit board as recited in Claim 8 wherein the first dielectric layer has a thickness of no more than 0.5 mils.

10. The printed circuit board as recited in Claim 9 wherein the first conductive layer has a thickness of no more than 0.5 mils.

11. The printed circuit board as recited in Claim 10 wherein the second conductive layer, the second dielectric layer, the third conductive layer, the fourth conductive layer, and the third dielectric layer each have a thickness of no more than 0.5 mils.

12. The printed circuit board as recited in Claim 8 wherein the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the first dielectric layer, the second dielectric layer, and the third dielectric layer each have a thickness of no more than 0.2 mils.

13. The printed circuit board as recited in Claim 8 further comprising a via which electrically interconnects the first conductive layer and the third conductive layer.

14. The printed circuit board as recited in Claim 14 further comprising a second via which electrically interconnects the second conductive layer and the fourth conductive layer.

15. A printed circuit board comprising: a first conductive layer forming a first power supply plane; a second conductive layer forming a second power supply plane; and a dielectric layer separating said first and second conductive layers, wherein said dielectric layer has a loss tangent value of at least 0.2.

16. An electrical interconnecting apparatus comprising: a first conductive layer forming a first power supply plane; a second conductive layer forming a second power supply plane; a first dielectric layer separating the first and second conductive layers; a third conductive layer; and a second dielectric layer separating said second and third conductive layers, wherein said first dielectric layer has a thickness of no more than 0.5 mils.

17. An electrical interconnecting apparatus as recited in Claim 16 wherein the second dielectric layer has a thickness of at least 1 mil.

18 An electncal mterconnectmg apparatus as recited in Claim 16 wherem said first dielectric layer has a thickness of no more than 0.1 mil.

19 The electncal mterconnectmg apparatus as recited in Claim 16, wherem the electncal mterconnectmg apparatus forms a substrate within an mtegrated circuit package

20 An electncal mterconnectmg apparatus compnsmg. a first conductive layer formmg a first power supply plane; a second conductive layer formmg a second power supply plane; a first dielectπc layer adjacent to and separatmg the first and second conductive layers; a second dielectnc layer adjunct to said second conductive layer; a third conductive layer formmg a third power supply plane, wherem the third conductive layer is adjacent to said second dielectnc layer; a fourth conductive layer forming a fourth power supply plane, a third dielectπc layer adjacent to and separatmg the third and fourth conductive layers.

21. An electncal mterconnectmg apparatus as recited m Claim 20 wherem the first conductive layer, the second conductive layer, the first dielectπc layer, the second dielectnc layer, the third conductive layer, the fourth conductive layer, and the third dielectnc layer each have a thickness of no more than 0.5 mils

22. The electncal mterconnectmg apparatus as recited m Claim 20, wherem the electncal mterconnectmg apparatus forms a substrate within an mtegrated circuit package.