WO2001042964A2 - Method and apparatus for structure prediction based on model curvature - Google Patents

Method and apparatus for structure prediction based on model curvature Download PDF

Info

Publication number
WO2001042964A2
WO2001042964A2 PCT/US2000/033481 US0033481W WO0142964A2 WO 2001042964 A2 WO2001042964 A2 WO 2001042964A2 US 0033481 W US0033481 W US 0033481W WO 0142964 A2 WO0142964 A2 WO 0142964A2
Authority
WO
WIPO (PCT)
Prior art keywords
curvature
integrated circuit
determined
medium
line segment
Prior art date
Application number
PCT/US2000/033481
Other languages
French (fr)
Other versions
WO2001042964A3 (en
Inventor
Yuri Granik
Nicolas Bailey Cobb
Franklin Mark Schellenberg
Original Assignee
Mentor Graphics Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corporation filed Critical Mentor Graphics Corporation
Priority to AU20820/01A priority Critical patent/AU2082001A/en
Publication of WO2001042964A2 publication Critical patent/WO2001042964A2/en
Publication of WO2001042964A3 publication Critical patent/WO2001042964A3/en

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441Optical proximity correction [OPC]
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Definitions

  • the invention relates to structure modeling and prediction. More specifically, the invention relates to predicting a physical structure, for example, integrated circuit structures, based on information derived from contour representations.
  • Optical and process correction can be used to improve image fidelity.
  • Optical proximity correction is a subset of optical and process correction.
  • OPC techniques include, for example, introduction of additional structures to the IC layout that compensate for various process distortions.
  • Two general categories of OPC are currently in use: rule-based OPC and model-based OPC.
  • rule-based OPC a reticle layout is modified according to a set of fixed rules for geometric manipulation.
  • rule-based OPC has limited capability and when more complex OPC is desired, model-based OPC is used.
  • model-based OPC an IC structure to be formed is modeled and a threshold that represents the boundary of the structure on the wafer can be determined from simulated result generated based on the model used.
  • Simple forms of model-based OPC generate a simulated aerial image, l x,y), having a threshold, I lh , to predict the structure to be manufactured.
  • VTR Variable Threshold Resist
  • Figure 1 is one embodiment of contours representing an integrated circuit line end based on a Variable Threshold Resist (VTR) model.
  • VTR Variable Threshold Resist
  • the VTR model is used to determine characteristics of the integrated circuit structure where the threshold,
  • lh J max is a function of two variables, maximum intensity, 7 max , and
  • VTR model has been used to provide improved IC manufacturing; however, for certain situations, for example, line-end shortening, rule-based OPC can still provide better correction. Therefore, it is desirable to have an improved model- based OPC model.
  • a predicted curvature for a structure to be realized is determined.
  • the structure can be, for example, an integrated circuit structure on a layer of an integrated circuit.
  • the predicted curvature is used to determine a predicted boundary of the structure.
  • the layout of the integrated circuit structure can be modified.
  • Figure 1 is one embodiment of contours representing an integrated circuit line end based on a Variable Threshold Resist (VTR) model.
  • VTR Variable Threshold Resist
  • Figure 2 represents one embodiment of an integrated circuit layer prediction process suitable for use with the invention.
  • Figure 3 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a first manner.
  • FIGS. 4A-4F illustrate exemplary sampling patterns suitable for use with the invention.
  • Figure 5 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a second manner.
  • FIG. 6 illustrates an electronic design automation (EDA) tool that can be incorporated with the invention.
  • EDA electronic design automation
  • Figure 7 illustrates one embodiment of a computer system suitable for use to practice the invention.
  • Figure 8 a flow chart corresponding to one embodiment of OPC based on curvature.
  • the invention also relates to apparatuses for performing the operations herein.
  • apparatuses may be specially constructed for the required purposes, or may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.
  • a simulation result corresponding to an integrated circuit or other structure is generated.
  • the result includes contour data representing a feature value, for example, height (or intensity) of the structure at various points. Three or more points are used to determine a curvature of the result at a predetermined location.
  • the curvature information can be used to determine boundaries of the structure.
  • the curvature can be used for optical and process correction (OPC) purposes to modify an integrated circuit layout such that the resulting integrated circuit more closely resembles the designed integrated circuit than would otherwise be possible.
  • OPC optical and process correction
  • both slope and curvature of the integrated circuit structure are used for OPC purposes.
  • Figure 2 represents one embodiment of an integrated circuit layer prediction process suitable for use with the invention.
  • the process described with respect to Figure 2 generates a predicted circuit layer from a circuit design.
  • the predicted circuit layer can be used for OPC purposes.
  • the process can be used for multiple layers of an integrated circuit design.
  • Circuit design 200 represents a circuit described in functional, rather than, physical terms.
  • circuit design 200 is a high-level integrated circuit (IC) description languages such as VHDL and Verilog®, which are commonly used to design circuits.
  • VHDL is described in greater detail in "IEEE Standard VHDL Language Reference Manual," ANSI Std. 1076-1993, Published June 6, 1994.
  • Verilog® is described in greater detail in IEEE Standard 1364-1995.
  • Circuit design 200 is typically input to a synthesis tool 210, which generates netwlist 220.
  • Other software tools can also be used to create netlists using customized design techniques.
  • Netlist 220 describes the logical relationship of circuit elements to provide the desired functionality. Netlist 220 can then be used to develop the layout that will be used to fabricate an IC having the desired functionality. Netlist 220 can also be used for verification purposes.
  • Netlist 220 is input to layout tool 230, which can be an electronic design automation (EDA) tool, one embodiment of which is described in greater detail below, or any other tool that generates a circuit layout based on circuit design 200.
  • Circuit layout 240 is generated by layout tool 230.
  • Circuit layout 240 has multiple layers, determined based on circuit design 200 and the manufacturing process to be used, and can be represented in any appropriate format for describing a layout for circuit design 200.
  • Process model 250 receives circuit layout 240 and generates intensity pattern 260.
  • process model 250 is a mathematical model that is based on the manufacturing process to be used to manufacture an integrated circuit based on circuit design 200.
  • the mathematical model can be performed by, for example, a computer system having a processor that executes a sequence of instructions stored in memory that represent the mathematical model.
  • Process models are known in the art and examples of process models and/or references to process models can be found in the papers cited above in the Background of the Invention.
  • Process model 250 generates intensity pattern 260 for a layer of the integrated circuit, which represents the intensity of light to which the physical integrated circuit will be exposed based on information related to the manufacturing process to be used.
  • the intensity determines the exposure, and therefore, the size and shape of the integrated circuit structure.
  • intensity pattern 260 is a mathematical representation of the integrated circuit structure stored, for example, in a machine- readable storage medium.
  • Graphical processor 270 operates on intensity pattern 260 to generate intensity representation 275.
  • Graphical processor 270 and intensity representation 275 are not necessary to practice the invention; however, intensity representation 275 can be useful in circuit design and OPC.
  • Intensity representation 275 is any physical representation of intensity pattern 260, for example, a display on a computer screen, a printed contour plot, etc.
  • intensity representation 275 illustrates the integrated circuit layer with contour lines that represent constant intensity, or constant elevation.
  • Graphical processor 270 is any device (e.g., a computer system with a display device and/or printer) that converts intensity pattern 260 to intensity representation 275.
  • VTR model 280 also operates on intensity pattern 260 to generate predicted realization of the circuit layer 285.
  • predicted realization of the circuit layer 285 provides a threshold line, I lh , that represents a predicted boundary of the integrated circuit structure(s) on the layer processed.
  • the threshold line, I lh is determined taking into consideration curvature information determined as described below with respect to Figure 3. In one embodiment, predicted realization of the circuit layer 285 also includes curvature information as discussed below.
  • Predicted realization of the circuit layer 285 is used to modify circuit layout 240. For example, if predicted realization of the circuit layer 285 indicates that the circuit layer will not provide an appropriate structure (e.g., line end shortening), circuit layout 240 can be modified (e.g., extend the line end) to compensate for the deficiency. Thus, predicted realization of the circuit structure 285 can be used as feedback to provide OPC for the integrated circuit design. The layout modification and modeling process can be repeated as necessary until predicted realization of the circuit structure 285 indicates a satisfactory design.
  • Reticle 290 can be generated in any manner known in the art.
  • Reticle 290 is used in an integrated circuit manufacturing process to manufacture integrated circuit structure 295.
  • Figure 3 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a first manner.
  • a two dimensional sampling pattern is used to determine slope of the model along the x-axis and curvature of the model along the y-axis.
  • only curvature along the y-axis is measured.
  • the angle between the line along which slope is determined and the line along which the curvature is determined are not perpendicular to each other.
  • slope and curvature are discussed as being determined along one or more predetermined lines, the sampling points used in determining slope and/or curvature are not required to be linear.
  • Representative integrated circuit structures are described herein with respect to x- and y-axes, which are traditionally horizontal and vertical axes, respectively; however, the slope and curvature samples can be taken along any orientation with respect to the integrated circuit structure.
  • samples are taken at predetermined locations relative to the contour to determine slope along a first predetermined line (X) and curvature along a second predetermined line (Y).
  • slope is determined between adjacent sampling points along the first predetermined line; however, the sampling points used for determining slope are not all required to be on a common line.
  • curvature is determined based the slope of a parabola fit to three sampling points on the second predetermined line; however, curvature can be determined in a different manner, for example, more than three points can be used, or curvature can be determined along a non-linear section.
  • the threshold for the corresponding structure can be determined according to:
  • the sampling points along the x-axis used for determining the slope of the intensity representation of the integrated circuit structure define a first line segment. In one embodiment seven sampling points are used along the x-axis; however, any number of sampling points can be used. In one embodiment, the points used for determining curvature define a second line segment perpendicular to the first line segment; however, a perpendicular orientation is not required. Many different sets points can be used to estimate the curvature of the intensity representation of the integrated circuit structure. For example, the curvature can be determined at a midpoint of the first line segment, at either end of the first line segment, at the point of maximum intensity, at the point of maximum slope, or at any other point along the first line segment. A grid pattern of sampling points can also be used to determine slope and/or curvature of the intensity representation of the integrated circuit structure.
  • curvature can be used rather than fitting a parabola to a set of three or more points and determining the second derivative of the points along the parabola.
  • Gaussian curvature can be used, the radius of a circle fitted to the intensity representation of the structure can be used, other types of curvature and other geometric shapes can also be used to determine curvature.
  • information gained from the slope and curvature can be used to make corrections to the layout used for manufacturing the integrated circuit structure such that the structure resulting from the manufacturing process more closely resembles the intended resulting structures than it would otherwise.
  • circuit layout structures are segmented. The various segments of the circuit layout are modified to facilitate closer realization of the intended structures.
  • Segmenting an integrated circuit layout involves inserting additional vertices to create smaller sections of edges, or edge fragments.
  • Predefined rules generally define where vertices should be added. For example, vertices are usually added so that there is no more than a maximum edge segment length between vertices. Vertices can also be added near particular types of vertices, such as adding vertices near corner vertices so that a corner is comprised of two short edge fragments.
  • design layout segment placement is modified, if necessary, in response to the threshold determined based on the curvature of the contour representation of the integrated circuit structure. For example, a line end segment of a layout can be moved so that the threshold of the modeled integrated circuit structure corresponds more closely to the end of the design layout.
  • Figures 4A-4F illustrate exemplary sampling patterns suitable for use with the invention.
  • Figure 4A illustrates a sampling pattern where the curvature line segment is located at the midpoint of the slope line segment.
  • Figure 4B illustrates a sampling pattern where the curvature line segment is located at the endpoint of the slope line segment.
  • Figure 4C illustrates a sampling pattern where the curvature line segment is located at a point between the end point and the midpoint.
  • Figure 4D illustrates a grid sampling pattern.
  • Figure 4E illustrates a sampling pattern where the curvature line segment is located at the point of maximum intensity along the slope line segment.
  • Figure 4F illustrates a sampling pattern where the curvature line segment is located at the point of maximum slope along the slope line segment.
  • Other sampling patterns can also be used.
  • FIG. 5 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a second manner.
  • curvature is measured along a contour line, C.
  • the intensity threshold can be measured as:
  • FIG 6 illustrates an electronic design automation (EDA) tool that can be incorporated with the invention.
  • EDA tool suite 600 includes simulation tool 602 incorporated with the teachings of the present invention as described earlier (e.g., VTR model 280 of Figure 2). Additionally, EDA tool suite 600 includes other tool modules 604. Examples of these other tool modules 602 include but not limited to synthesis module, layout verification module and so forth.
  • Figure 7 illustrates one embodiment of a computer system suitable for use to practice the invention.
  • computer system 700 includes processor 702 and memory 704 coupled to each other via system bus 706. Coupled to system bus 706 are non-volatile mass storage 708, such as hard disks, floppy disk, and so forth, input/output devices 710, such as keyboard, displays, and so forth, and communication interfaces 712, such as modem, LAN interfaces, and so forth. Each of these elements perform its conventional functions known in the art.
  • system memory 704 and non-volatile mass storage 708 are employed to store a working copy and a permanent copy of the programming instructions implementing the above described teachings of the present invention.
  • System memory 704 and non-volatile mass storage 706 may also be employed to store the IC designs.
  • the permanent copy of the programming instructions to practice the present invention may be loaded into non-volatile mass storage 708 in the factory, or in the field, using distribution source/medium 714 and optionally, communication interfaces 712. Examples of distribution medium 714 include recordable medium such as tapes, CDROM, DVD, and so forth.
  • the programming instructions are part of a collection of programming instructions implementing EDA tool 600 of Fig. 6.
  • the constitution of elements 702-714 are well known, and accordingly will not be further described.
  • Figure 8 a flow chart corresponding to one embodiment of OPC based on curvature.
  • the process of Figure 8 is performed by an EDA tool based on an integrated circuit design layout.
  • the process of Figure 8 can be performed by a non-EDA application.
  • a simulation result such as an image of an integrated circuit structure layout is generated at 810. Generating the simulation result can be accomplished in any manner known in the art. Alternatively, a previously generated integrated circuit intensity pattern can be used instead.
  • Sampling points are determined at 820.
  • a set of sampling points e.g., Figs 4A-4F
  • samples are taken according to the chosen sampling pattern for the contour of each segment.
  • the x-axis sampling points described above are perpendicular to the contour of the design layout segment and the y-axis sampling points are parallel to or coincident with the contour of the layout segment.
  • sampling points are not necessarily orthogonal as described above, for example, the x-axis can be at an angle of 45° with respect to the contour of the layout segment.
  • Slope is determined at 830.
  • both the point of maximum intensity and the steepest slope i.e., the pair of sampling points on the contour representation having the greatest slope therebetween
  • Curvature is determined at 840. Curvature can be determined according to any manner described above.
  • OPC is performed at 850.
  • layout for line segments can be modified to compensate for optical effects (e.g., line end shortening) that result in an integrated circuit structure closer to the designed integrated structure using the determined slope and curvature.
  • optical effects e.g., line end shortening
  • the process of Figure 8 can be repeated for the modified integrated circuit layout to improve results further.

Abstract

Methods and apparatuses for structure prediction based on model curvature are described. A simulation result corresponding to an integrated circuit or other structure is generated. The result includes contour data representing a feature value, for example, height (or intensity) of the structure at various points. Three or more points are used to determine a curvature of the result at a predetermined location. The curvature information can be used to determine boundaries of the struture. For example, when used with an integrated circuit layout, the curvature can be used for optical and process correction (OPC) purposes to modify an integrated circuit layout such that the resulting integrated circuit more closely resembles the designed integrated circuit than would otherwise be possible. In one embodiment, both slope and curvature of the integrated circuit structure are used for OPC purposes.

Description

METHOD AND APPARATUS FOR
STRUCTURE PREDICTION BASED ON MODEL CURVATURE
FIELD OF THE INVENTION
The invention relates to structure modeling and prediction. More specifically, the invention relates to predicting a physical structure, for example, integrated circuit structures, based on information derived from contour representations.
BACKGROUND OF THE INVENTION
As integrated circuits (ICs) become more dense, the widths of lines and components, as well as the separation between lines becomes increasingly smaller. Currently, deep sub-micron (<0.25 μm) processes are being used. However, with deep sub-micron processes, silicon yield is affected by several factors including reticle/mask pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. Typical problems include line- width variations that depend on local pattern density and topology and line end pullback.
Optical and process correction (OPC) can be used to improve image fidelity. Optical proximity correction is a subset of optical and process correction. OPC techniques include, for example, introduction of additional structures to the IC layout that compensate for various process distortions. Two general categories of OPC are currently in use: rule-based OPC and model-based OPC. In rule-based OPC, a reticle layout is modified according to a set of fixed rules for geometric manipulation. However, rule-based OPC has limited capability and when more complex OPC is desired, model-based OPC is used.
In model-based OPC, an IC structure to be formed is modeled and a threshold that represents the boundary of the structure on the wafer can be determined from simulated result generated based on the model used. Simple forms of model-based OPC generate a simulated aerial image, l x,y), having a threshold, Ilh , to predict the structure to be manufactured.
A more sophisticated and accurate model-based OPC technique, referred to as the Variable Threshold Resist (VTR) model, allows the threshold, Ith , to take on multiple values. The VTR model is described by Cobb, et al., "Mathematical and CAD Framework for Proximity Correction," Optical Microlithography IX, Proc. SPIE 2726, pp. 208-222 (1996); Cobb, et al., "Experimental Results in Optical Proximity Correction with Variable Threshold Resist Model," Optical Microlithography X. SPIE 3051, pp. 458-468 (1998); and Nicholas B. Cobb, "Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing," PhD dissertation, Univ. Cal. Berkeley (1998).
Figure 1 is one embodiment of contours representing an integrated circuit line end based on a Variable Threshold Resist (VTR) model. In general, the VTR model is used to determine characteristics of the integrated circuit structure where the threshold,
lh J max is a function of two variables, maximum intensity, 7max , and
Figure imgf000003_0001
maximum slope, — as measured along a one-dimensional cut-line through the x- fx axis of the simulated result. As illustrated in Figure 1, the x-axis orientation is parallel to one of the axes used in the integrated circuit layout. The slope determined from the simulated result can be used to modify the design of the integrated circuit.
The VTR model has been used to provide improved IC manufacturing; however, for certain situations, for example, line-end shortening, rule-based OPC can still provide better correction. Therefore, it is desirable to have an improved model- based OPC model.
SUMMARY OF THE INVENTION
Methods and apparatuses for structure prediction based on model curvature are described. A predicted curvature for a structure to be realized is determined. The structure can be, for example, an integrated circuit structure on a layer of an integrated circuit. The predicted curvature is used to determine a predicted boundary of the structure. Based on the predicted boundary of the integrated circuit structure to be realized, the layout of the integrated circuit structure can be modified. BRIEF DESCRIPTION OF THE DRAWINGS
The invention is illustrated by way of example, and not by way of limitation in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Figure 1 is one embodiment of contours representing an integrated circuit line end based on a Variable Threshold Resist (VTR) model.
Figure 2 represents one embodiment of an integrated circuit layer prediction process suitable for use with the invention.
Figure 3 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a first manner.
Figures 4A-4F illustrate exemplary sampling patterns suitable for use with the invention.
Figure 5 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a second manner.
Figure 6 illustrates an electronic design automation (EDA) tool that can be incorporated with the invention.
Figure 7 illustrates one embodiment of a computer system suitable for use to practice the invention.
Figure 8 a flow chart corresponding to one embodiment of OPC based on curvature.
DETAILED DESCRIPTION
Methods and apparatuses for structure prediction based on model curvature are described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
Some portions of the detailed descriptions which follow are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art.
An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The invention also relates to apparatuses for performing the operations herein. These apparatuses may be specially constructed for the required purposes, or may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.
Briefly, a simulation result corresponding to an integrated circuit or other structure is generated. The result includes contour data representing a feature value, for example, height (or intensity) of the structure at various points. Three or more points are used to determine a curvature of the result at a predetermined location. The curvature information can be used to determine boundaries of the structure. For example, when used with an integrated circuit layout, the curvature can be used for optical and process correction (OPC) purposes to modify an integrated circuit layout such that the resulting integrated circuit more closely resembles the designed integrated circuit than would otherwise be possible. In one embodiment, both slope and curvature of the integrated circuit structure are used for OPC purposes.
Figure 2 represents one embodiment of an integrated circuit layer prediction process suitable for use with the invention. In general, the process described with respect to Figure 2 generates a predicted circuit layer from a circuit design. The predicted circuit layer can be used for OPC purposes. The process can be used for multiple layers of an integrated circuit design.
Circuit design 200 represents a circuit described in functional, rather than, physical terms. In one embodiment, circuit design 200 is a high-level integrated circuit (IC) description languages such as VHDL and Verilog®, which are commonly used to design circuits. One embodiment of VHDL is described in greater detail in "IEEE Standard VHDL Language Reference Manual," ANSI Std. 1076-1993, Published June 6, 1994. One embodiment of Verilog® is described in greater detail in IEEE Standard 1364-1995. These and other high-level IC description languages allow a circuit designer to design and simulate circuits by using high-level code to describe the structure and/or behavior of the circuit being designed.
Circuit design 200 is typically input to a synthesis tool 210, which generates netwlist 220. Other software tools can also be used to create netlists using customized design techniques. Netlist 220 describes the logical relationship of circuit elements to provide the desired functionality. Netlist 220 can then be used to develop the layout that will be used to fabricate an IC having the desired functionality. Netlist 220 can also be used for verification purposes.
Netlist 220 is input to layout tool 230, which can be an electronic design automation (EDA) tool, one embodiment of which is described in greater detail below, or any other tool that generates a circuit layout based on circuit design 200. Circuit layout 240 is generated by layout tool 230. Circuit layout 240 has multiple layers, determined based on circuit design 200 and the manufacturing process to be used, and can be represented in any appropriate format for describing a layout for circuit design 200.
Process model 250 receives circuit layout 240 and generates intensity pattern 260. In one embodiment process model 250 is a mathematical model that is based on the manufacturing process to be used to manufacture an integrated circuit based on circuit design 200. The mathematical model can be performed by, for example, a computer system having a processor that executes a sequence of instructions stored in memory that represent the mathematical model. Process models are known in the art and examples of process models and/or references to process models can be found in the papers cited above in the Background of the Invention.
Process model 250 generates intensity pattern 260 for a layer of the integrated circuit, which represents the intensity of light to which the physical integrated circuit will be exposed based on information related to the manufacturing process to be used. The intensity determines the exposure, and therefore, the size and shape of the integrated circuit structure. In one embodiment, intensity pattern 260 is a mathematical representation of the integrated circuit structure stored, for example, in a machine- readable storage medium.
Graphical processor 270 operates on intensity pattern 260 to generate intensity representation 275. Graphical processor 270 and intensity representation 275 are not necessary to practice the invention; however, intensity representation 275 can be useful in circuit design and OPC. Intensity representation 275 is any physical representation of intensity pattern 260, for example, a display on a computer screen, a printed contour plot, etc. In one embodiment, intensity representation 275 illustrates the integrated circuit layer with contour lines that represent constant intensity, or constant elevation. Graphical processor 270 is any device (e.g., a computer system with a display device and/or printer) that converts intensity pattern 260 to intensity representation 275.
VTR model 280 also operates on intensity pattern 260 to generate predicted realization of the circuit layer 285. One embodiment of VTR model 280 is described in greater detail below. In one embodiment, predicted realization of the circuit layer 285 provides a threshold line, Ilh , that represents a predicted boundary of the integrated circuit structure(s) on the layer processed.
In one embodiment, the threshold line, Ilh , is determined taking into consideration curvature information determined as described below with respect to Figure 3. In one embodiment, predicted realization of the circuit layer 285 also includes curvature information as discussed below.
Predicted realization of the circuit layer 285 is used to modify circuit layout 240. For example, if predicted realization of the circuit layer 285 indicates that the circuit layer will not provide an appropriate structure (e.g., line end shortening), circuit layout 240 can be modified (e.g., extend the line end) to compensate for the deficiency. Thus, predicted realization of the circuit structure 285 can be used as feedback to provide OPC for the integrated circuit design. The layout modification and modeling process can be repeated as necessary until predicted realization of the circuit structure 285 indicates a satisfactory design.
Once a satisfactory design is achieved, the corresponding circuit layout 240 is used to generate reticle 290. Reticle 290 can be generated in any manner known in the art. Reticle 290 is used in an integrated circuit manufacturing process to manufacture integrated circuit structure 295. Figure 3 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a first manner. In one embodiment, a two dimensional sampling pattern is used to determine slope of the model along the x-axis and curvature of the model along the y-axis. In an alternative embodiment, only curvature along the y-axis is measured. In another alternative embodiment, the angle between the line along which slope is determined and the line along which the curvature is determined are not perpendicular to each other.
While slope and curvature are discussed as being determined along one or more predetermined lines, the sampling points used in determining slope and/or curvature are not required to be linear. Representative integrated circuit structures are described herein with respect to x- and y-axes, which are traditionally horizontal and vertical axes, respectively; however, the slope and curvature samples can be taken along any orientation with respect to the integrated circuit structure.
In one embodiment, samples are taken at predetermined locations relative to the contour to determine slope along a first predetermined line (X) and curvature along a second predetermined line (Y). In one embodiment, slope is determined between adjacent sampling points along the first predetermined line; however, the sampling points used for determining slope are not all required to be on a common line. Similarly, in one embodiment, curvature is determined based the slope of a parabola fit to three sampling points on the second predetermined line; however, curvature can be determined in a different manner, for example, more than three points can be used, or curvature can be determined along a non-linear section.
Experience has shown use of curvature in determining the threshold value of an integrated circuit structure provides improved information compared to using slope alone, accordingly, the number of sampling points along the slope line (X) can be decreased to compensate for the increased number of sampling points used along the curvature line (Y). Therefore, little or no performance penalty is incurred for determining both slope and curvature as compared to determining slope only. In one embodiment, seven sampling points along the slope line are used to determine slope values and three sampling points along the curvature line are used to determine curvature; however, any number of points along either line can be used to determine slope and/or curvature. In an embodiment where slope is determined along the first predetermined line and curvature is determined along the second predetermined line, the threshold for the corresponding structure can be determined according to:
Figure imgf000010_0001
where represents the curvature of intensity representation of the integrated fy2 x- fixed circuit structure along the y-axis. In other words, the second derivative of a parabola that is fit to three or more points along the y-axis can be used to predict of the curvature intensity representation of the integrated circuit structure. The curvature information provides a more accurate representation of the integrated circuit structure and therefore a more accurate determination of the integrated circuit structure threshold. The parabola can be fit to the curvature sampling points in any manner known in the art.
The sampling points along the x-axis used for determining the slope of the intensity representation of the integrated circuit structure define a first line segment. In one embodiment seven sampling points are used along the x-axis; however, any number of sampling points can be used. In one embodiment, the points used for determining curvature define a second line segment perpendicular to the first line segment; however, a perpendicular orientation is not required. Many different sets points can be used to estimate the curvature of the intensity representation of the integrated circuit structure. For example, the curvature can be determined at a midpoint of the first line segment, at either end of the first line segment, at the point of maximum intensity, at the point of maximum slope, or at any other point along the first line segment. A grid pattern of sampling points can also be used to determine slope and/or curvature of the intensity representation of the integrated circuit structure.
Other types of curvature can be used rather than fitting a parabola to a set of three or more points and determining the second derivative of the points along the parabola. For example, Gaussian curvature can be used, the radius of a circle fitted to the intensity representation of the structure can be used, other types of curvature and other geometric shapes can also be used to determine curvature.
In one embodiment, information gained from the slope and curvature can be used to make corrections to the layout used for manufacturing the integrated circuit structure such that the structure resulting from the manufacturing process more closely resembles the intended resulting structures than it would otherwise. In one embodiment, circuit layout structures are segmented. The various segments of the circuit layout are modified to facilitate closer realization of the intended structures.
Segmenting an integrated circuit layout involves inserting additional vertices to create smaller sections of edges, or edge fragments. Predefined rules generally define where vertices should be added. For example, vertices are usually added so that there is no more than a maximum edge segment length between vertices. Vertices can also be added near particular types of vertices, such as adding vertices near corner vertices so that a corner is comprised of two short edge fragments.
If more vertices are added, more precise edge placement corrections can be made, but more OPC computations are performed. That is, increasing the granularity of edge segments increases the potential OPC accuracy, but decreases speed. Densely filled areas are likely to need more intricate edge placement correction than sparsely filled areas, so more vertices may be added to densely filled areas than to sparsely filled areas.
In one embodiment, design layout segment placement is modified, if necessary, in response to the threshold determined based on the curvature of the contour representation of the integrated circuit structure. For example, a line end segment of a layout can be moved so that the threshold of the modeled integrated circuit structure corresponds more closely to the end of the design layout.
Figures 4A-4F illustrate exemplary sampling patterns suitable for use with the invention. Figure 4A illustrates a sampling pattern where the curvature line segment is located at the midpoint of the slope line segment. Figure 4B illustrates a sampling pattern where the curvature line segment is located at the endpoint of the slope line segment. Figure 4C illustrates a sampling pattern where the curvature line segment is located at a point between the end point and the midpoint. Figure 4D illustrates a grid sampling pattern. Figure 4E illustrates a sampling pattern where the curvature line segment is located at the point of maximum intensity along the slope line segment. Figure 4F illustrates a sampling pattern where the curvature line segment is located at the point of maximum slope along the slope line segment. Other sampling patterns can also be used.
lθ- Figure 5 illustrates one embodiment of a contour representation of a simulation result corresponding to an integrated circuit structure layout upon which curvature can be measured in a second manner. In one embodiment, curvature is measured along a contour line, C. In such an embodiment, the intensity threshold can be measured as:
Figure imgf000012_0001
where represents the curvature of the contour of the integrated circuit fy2 \ l= fixed structure along a constant intensity contour. The curvature information can be used for OPC as described above.
Figure 6 illustrates an electronic design automation (EDA) tool that can be incorporated with the invention. As illustrated, EDA tool suite 600 includes simulation tool 602 incorporated with the teachings of the present invention as described earlier (e.g., VTR model 280 of Figure 2). Additionally, EDA tool suite 600 includes other tool modules 604. Examples of these other tool modules 602 include but not limited to synthesis module, layout verification module and so forth.
Figure 7 illustrates one embodiment of a computer system suitable for use to practice the invention. As shown, computer system 700 includes processor 702 and memory 704 coupled to each other via system bus 706. Coupled to system bus 706 are non-volatile mass storage 708, such as hard disks, floppy disk, and so forth, input/output devices 710, such as keyboard, displays, and so forth, and communication interfaces 712, such as modem, LAN interfaces, and so forth. Each of these elements perform its conventional functions known in the art.
In particular, system memory 704 and non-volatile mass storage 708 are employed to store a working copy and a permanent copy of the programming instructions implementing the above described teachings of the present invention. System memory 704 and non-volatile mass storage 706 may also be employed to store the IC designs. The permanent copy of the programming instructions to practice the present invention may be loaded into non-volatile mass storage 708 in the factory, or in the field, using distribution source/medium 714 and optionally, communication interfaces 712. Examples of distribution medium 714 include recordable medium such as tapes, CDROM, DVD, and so forth. In one embodiment, the programming instructions are part of a collection of programming instructions implementing EDA tool 600 of Fig. 6. The constitution of elements 702-714 are well known, and accordingly will not be further described.
Figure 8 a flow chart corresponding to one embodiment of OPC based on curvature. In one embodiment the process of Figure 8 is performed by an EDA tool based on an integrated circuit design layout. In an alternative embodiment, the process of Figure 8 can be performed by a non-EDA application.
A simulation result such as an image of an integrated circuit structure layout is generated at 810. Generating the simulation result can be accomplished in any manner known in the art. Alternatively, a previously generated integrated circuit intensity pattern can be used instead.
Sampling points are determined at 820. In one embodiment, a set of sampling points (e.g., Figs 4A-4F) are applied to the contour of each design layout segment. In other words, samples are taken according to the chosen sampling pattern for the contour of each segment. In one embodiment, the x-axis sampling points described above are perpendicular to the contour of the design layout segment and the y-axis sampling points are parallel to or coincident with the contour of the layout segment. In alternative embodiments, sampling points are not necessarily orthogonal as described above, for example, the x-axis can be at an angle of 45° with respect to the contour of the layout segment.
Slope is determined at 830. In one embodiment, both the point of maximum intensity and the steepest slope (i.e., the pair of sampling points on the contour representation having the greatest slope therebetween) are determined. Curvature is determined at 840. Curvature can be determined according to any manner described above.
OPC is performed at 850. In one embodiment, layout for line segments can be modified to compensate for optical effects (e.g., line end shortening) that result in an integrated circuit structure closer to the designed integrated structure using the determined slope and curvature. The process of Figure 8 can be repeated for the modified integrated circuit layout to improve results further.
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMSWhat is claimed is:
1. A method comprising: determining a curvature of a simulation result of an integrated circuit structure; and modifying a layout of the integrated circuit structure based, at least in part, on the curvature.
2. The method of claim 1 further comprising generating an intensity pattern corresponding to the integrated circuit structure, wherein the intensity pattern has contours indicating constant intensity.
3. The method of claim 1 wherein the curvature is determined along a contour.
4. The method of claim 1 wherein the curvature is generated based on the intensity pattern contours.
5. The method of claim 4 further comprising determining a slope of the integrated circuit structure along a predetermined line segment.
6. The method of claim 5 wherein the slope is determined based on a predicted elevation at a predetermined number of sampling points.
7. The method of claim 5 wherein the curvature is determined at a maximum slope of the integrated circuit structure along the predetermined line segment.
8. The method of claim 5 wherein the curvature is determined at a point of maximum intensity along the predetermined line segment.
9. The method of claim 5 wherein the curvature is determined at approximately at a midpoint of the predetermined line segment.
10. The method of claim 5 wherein the curvature is determined at approximately an end point of the predetermined line segment.
1 1. The method of claim 5 wherein the curvature is determined along a second line segment oriented at a predetermined angle with respect to the predetermined line segment.
12. The method of claim 11 wherein the predetermined angle is approximately 90 degrees.
13. The method of claim 11 wherein the predetermined angle is greater than 90 degrees.
14. The method of claim 11 wherein the predetermined angle is less than 90 degrees.
15. The method of claim 1 wherein the curvature is determined at approximately an end point of the integrated circuit structure as designed.
16. The method of claim 1 wherein the curvature is determined as a second derivative of a parabola including three or more sampling points.
17. The method of claim 1 wherein the curvature is determined as a logarithm of a second derivative of a parabola including three or more sampling points.
18. The method of claim 1 wherein modifying a design of the integrated circuit based on the curvature comprises: segmenting the design of the integrated circuit; and modifying placement of one or more segments based, at least in part, on the curvature.
19. A medium having stored thereon sequences of instructions to implement an integrated circuit structure modeling application comprising sequences of instructions that, when executed by one or more processors, cause an electronic device to: determine a curvature of a simulation result of an integrated circuit structure; and modify a layout of the integrated circuit structure based, at least in part, on the curvature.
20. The medium of claim 19 wherein the curvature is determined along a pattern intensity contour.
21. The medium of claim 19 wherein the curvature is generated based on the pattern intensity contours.
22. The medium of claim 19 further comprising sequences of instructions that, when executed, cause the one or more electronic devices to determine a slope of the integrated circuit structure along a predetermined line segment.
23. The medium of claim 22 wherein the slope is determined based on a modeled elevation at a predetermined number of sampling points.
24. The medium of claim 22 wherein the curvature is determined at a maximum slope of the integrated circuit structure along the predetermined line segment.
25. The medium of claim 22 wherein the curvature is determined at a point of maximum intensity along the predetermined line segment.
26. The medium of claim 22 wherein the curvature is determined at approximately at a midpoint of the predetermined line segment.
27. The medium of claim 22 wherein the curvature is determined at approximately an end point of the predetermined line segment.
28. The medium of claim 22 wherein the curvature is determined along a second line segment oriented at a predetermined angle with respect to the predetermined line segment.
29. The medium of claim 28 wherein the predetermined angle is approximately 90 degrees.
30. The medium of claim 28 wherein the predetermined angle is greater than 90 degrees.
31. The medium of claim 28 wherein the predetermined angle is less than 90 degrees.
32. The medium of claim 19 wherein the curvature is determined at approximately an end point of the integrated circuit structure as designed.
33. The medium of claim 19 wherein the curvature is determined as a second derivative of a parabola including three or more sampling points.
34. The medium of claim 19 wherein the curvature is determined as a logarithm of a second derivative of a parabola including three or more sampling points.
35. The medium of claim 19 wherein modifying a design of the integrated circuit based on the curvature comprises: segmenting the design of the integrated circuit; and modifying placement of one or more segments based, at least in part, on the curvature.
36. A reticle for manufacturing an integrated circuit structure, the reticle comprising at least one area to define the integrated circuit structure, the area being defined by a modified integrated circuit layout, wherein the modified integrated circuit layout is determined based, at least in part, on a predicted structure of an original integrated circuit layout, and further wherein the original integrated circuit layout is modified based, at least in part, on a curvature of the predicted structure to result in the modified integrated circuit layout.
37. The reticle of claim 36 wherein the at least one area to define the integrated circuit structure comprises a transparent area.
38. The reticle of claim 36 wherein the at least one area to define the integrated circuit structure comprises an opaque area.
39. The reticle of claim 36, wherein the original integrated circuit layout is modified based, at least in part, on a curvature and a slope of the predicted structure to result in the modified integrated circuit layout.
40. The reticle of claim 36, wherein the original integrated circuit layout and the modified integrated circuit layout are segmented, and further wherein one or more segments of the modified integrated circuit layout are repositioned with corresponding segments of the original integrated circuit layout based on the curvature.
41. A method comprising : estimating contours of a structure, where the contours represent constant elevation; estimating a curvature of the structure based, at least in part, on elevation information corresponding to the estimated contours of the structure; and estimating a boundary of the structure based, at least in part, on the curvature.
42. The method of claim 41 wherein the structure comprises a structure on a layer of an integrated circuit.
PCT/US2000/033481 1999-12-07 2000-12-07 Method and apparatus for structure prediction based on model curvature WO2001042964A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU20820/01A AU2082001A (en) 1999-12-07 2000-12-07 Method and apparatus for structure prediction based on model curvature

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/457,410 US6643616B1 (en) 1999-12-07 1999-12-07 Integrated device structure prediction based on model curvature
US09/457,410 1999-12-07

Publications (2)

Publication Number Publication Date
WO2001042964A2 true WO2001042964A2 (en) 2001-06-14
WO2001042964A3 WO2001042964A3 (en) 2002-03-14

Family

ID=23816619

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/033481 WO2001042964A2 (en) 1999-12-07 2000-12-07 Method and apparatus for structure prediction based on model curvature

Country Status (3)

Country Link
US (2) US6643616B1 (en)
AU (1) AU2082001A (en)
WO (1) WO2001042964A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1522889A2 (en) * 2003-10-10 2005-04-13 Synopsys, Inc. Method and apparatus for generating an OPC segmentation
WO2007097838A2 (en) * 2006-02-21 2007-08-30 Mentor Graphics Corporation Grid-based resist simulation

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7412676B2 (en) * 2000-06-13 2008-08-12 Nicolas B Cobb Integrated OPC verification tool
US6425113B1 (en) * 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US7392168B2 (en) * 2001-03-13 2008-06-24 Yuri Granik Method of compensating for etch effects in photolithographic processing
US6813757B2 (en) * 2001-10-25 2004-11-02 Texas Instruments Incorporated Method for evaluating a mask pattern on a substrate
US7293249B2 (en) * 2002-01-31 2007-11-06 Juan Andres Torres Robles Contrast based resolution enhancement for photolithographic processing
US6854104B2 (en) * 2002-11-27 2005-02-08 Lsi Logic Corporation First approximation for OPC significant speed-up
US6928634B2 (en) * 2003-01-02 2005-08-09 Yuri Granik Matrix optical process correction
US20050015233A1 (en) * 2003-07-17 2005-01-20 International Business Machines Corporation Method for computing partially coherent aerial imagery
US8036869B2 (en) * 2003-09-30 2011-10-11 Tokyo Electron Limited System and method for using first-principles simulation to control a semiconductor manufacturing process via a simulation result or a derived empirical model
US8296687B2 (en) * 2003-09-30 2012-10-23 Tokyo Electron Limited System and method for using first-principles simulation to analyze a process performed by a semiconductor processing tool
US8073667B2 (en) * 2003-09-30 2011-12-06 Tokyo Electron Limited System and method for using first-principles simulation to control a semiconductor manufacturing process
US8014991B2 (en) * 2003-09-30 2011-09-06 Tokyo Electron Limited System and method for using first-principles simulation to characterize a semiconductor manufacturing process
US8032348B2 (en) * 2003-09-30 2011-10-04 Tokyo Electron Limited System and method for using first-principles simulation to facilitate a semiconductor manufacturing process
US6978438B1 (en) * 2003-10-01 2005-12-20 Advanced Micro Devices, Inc. Optical proximity correction (OPC) technique using generalized figure of merit for photolithograhic processing
US7366342B2 (en) * 2003-10-27 2008-04-29 International Business Machines Corporation Simultaneous computation of multiple points on one or multiple cut lines
US7073162B2 (en) * 2003-10-31 2006-07-04 Mentor Graphics Corporation Site control for OPC
US7861207B2 (en) 2004-02-25 2010-12-28 Mentor Graphics Corporation Fragmentation point and simulation site adjustment for resolution enhancement techniques
US7080349B1 (en) * 2004-04-05 2006-07-18 Advanced Micro Devices, Inc. Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
EP1747520B1 (en) 2004-05-07 2018-10-24 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands
US7071085B1 (en) 2004-05-25 2006-07-04 Advanced Micro Devices, Inc. Predefined critical spaces in IC patterning to reduce line end pull back
US7015148B1 (en) 2004-05-25 2006-03-21 Advanced Micro Devices, Inc. Reduce line end pull back by exposing and etching space after mask one trim and etch
US7240305B2 (en) * 2004-06-02 2007-07-03 Lippincott George P OPC conflict identification and edge priority system
US7472576B1 (en) 2004-11-17 2009-01-06 State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Portland State University Nanometrology device standards for scanning probe microscopes and processes for their fabrication and use
US7493587B2 (en) * 2005-03-02 2009-02-17 James Word Chromeless phase shifting mask for integrated circuits using interior region
US8037429B2 (en) * 2005-03-02 2011-10-11 Mentor Graphics Corporation Model-based SRAF insertion
US7434199B2 (en) * 2005-09-27 2008-10-07 Nicolas Bailey Cobb Dense OPC
US7325225B2 (en) * 2005-10-05 2008-01-29 Yasushi Tanaka Method and apparatus for reducing OPC model errors
US7546574B2 (en) 2005-12-02 2009-06-09 Gauda, Inc. Optical proximity correction on hardware or software platforms with graphical processing units
US7506285B2 (en) 2006-02-17 2009-03-17 Mohamed Al-Imam Multi-dimensional analysis for predicting RET model accuracy
US7712068B2 (en) 2006-02-17 2010-05-04 Zhuoxiang Ren Computation of electrical properties of an IC layout
US7360199B2 (en) 2006-05-26 2008-04-15 International Business Machines Corporation Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC)
US7546573B1 (en) 2006-06-06 2009-06-09 Kla-Tencor Corporation Semiconductor device pattern generation
US8056022B2 (en) 2006-11-09 2011-11-08 Mentor Graphics Corporation Analysis optimizer
US7966585B2 (en) 2006-12-13 2011-06-21 Mentor Graphics Corporation Selective shielding for multiple exposure masks
US7802226B2 (en) * 2007-01-08 2010-09-21 Mentor Graphics Corporation Data preparation for multiple mask printing
US7739650B2 (en) * 2007-02-09 2010-06-15 Juan Andres Torres Robles Pre-bias optical proximity correction
US7799487B2 (en) 2007-02-09 2010-09-21 Ayman Yehia Hamouda Dual metric OPC
US8544064B2 (en) * 2007-02-09 2013-09-24 Sony Corporation Techniques for automatic registration of appliances
JP4328811B2 (en) * 2007-02-27 2009-09-09 キヤノン株式会社 Resist pattern shape prediction method, program, and computer
US7596775B2 (en) * 2007-05-22 2009-09-29 United Microelectronics Corp. Method for determining a standard cell for IC design
US8713483B2 (en) 2007-06-05 2014-04-29 Mentor Graphics Corporation IC layout parsing for multiple masks
US7805699B2 (en) * 2007-10-11 2010-09-28 Mentor Graphics Corporation Shape-based photolithographic model calibration
US8566755B2 (en) * 2007-11-26 2013-10-22 Macronix International Co., Ltd. Method of correcting photomask patterns
JP2010034402A (en) * 2008-07-30 2010-02-12 Toshiba Corp Method of estimating pattern form
US8006203B2 (en) * 2008-08-28 2011-08-23 Synopsys, Inc. Bulk image modeling for optical proximity correction
CN101750878B (en) * 2008-12-22 2011-12-07 中芯国际集成电路制造(上海)有限公司 optical proximity correction method
US8122387B2 (en) * 2009-06-11 2012-02-21 International Business Macines Corporation Optimizing integrated circuit chip designs for optical proximity correction
EP2752367B1 (en) 2010-01-28 2016-04-27 Avery Dennison Corporation Label applicator belt system
JP5286337B2 (en) * 2010-08-30 2013-09-11 株式会社日立ハイテクノロジーズ Semiconductor manufacturing apparatus management apparatus and computer program
US9355201B2 (en) 2012-08-17 2016-05-31 Mentor Graphics Corporation Density-based integrated circuit design adjustment
US20140129184A1 (en) * 2012-11-08 2014-05-08 Avery Dennison Corporation Systems, Methods, and Media for Labeling Three Dimensional Surfaces
US10185799B2 (en) * 2014-04-22 2019-01-22 Mentor Graphics Corporation Verification of photonic integrated circuits
US10444734B2 (en) 2014-08-22 2019-10-15 Mentor Graphics Corporation Manufacture of non-rectilinear features
CN106483758B (en) * 2015-09-02 2019-08-20 无锡华润上华科技有限公司 Optical proximity effect modification method and system
KR20200028088A (en) * 2018-09-06 2020-03-16 삼성전자주식회사 Dissection method for layout patterns in semiconductor device and optical proximity correction method including the same
US11054748B2 (en) 2018-09-21 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy insertion for improving throughput of electron beam lithography
CN110471251A (en) * 2019-07-15 2019-11-19 苏州悦谱半导体有限公司 A kind of OPC modification method based on model

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815685A (en) * 1994-09-16 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Apparatus and method for correcting light proximity effects by predicting mask performance
US5825647A (en) * 1995-03-13 1998-10-20 Sony Corporation Correction method and correction apparatus of mask pattern

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6269472B1 (en) * 1996-02-27 2001-07-31 Lsi Logic Corporation Optical proximity correction method and apparatus
US6370679B1 (en) * 1997-09-17 2002-04-09 Numerical Technologies, Inc. Data hierarchy layout correction and verification method and apparatus
US6301967B1 (en) * 1998-02-03 2001-10-16 The Trustees Of The Stevens Institute Of Technology Method and apparatus for acoustic detection and location of defects in structures or ice on structures
US6033814A (en) * 1998-02-26 2000-03-07 Micron Technology, Inc. Method for multiple process parameter matching
EP0980542A4 (en) * 1998-03-17 2006-03-01 Asml Masktools Bv Method of patterning sub-0.25 lambda line features with high transmission, "attenuated" phase shift masks
US6226781B1 (en) * 1998-08-12 2001-05-01 Advanced Micro Devices, Inc. Modifying a design layer of an integrated circuit using overlying and underlying design layers
US6120952A (en) 1998-10-01 2000-09-19 Micron Technology, Inc. Methods of reducing proximity effects in lithographic processes
US6263299B1 (en) * 1999-01-19 2001-07-17 Lsi Logic Corporation Geometric aerial image simulation
US6249904B1 (en) * 1999-04-30 2001-06-19 Nicolas Bailey Cobb Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion
US6301697B1 (en) * 1999-04-30 2001-10-09 Nicolas B. Cobb Streamlined IC mask layout optical and process correction through correction reuse
US6080527A (en) * 1999-11-18 2000-06-27 United Microelectronics Corp. Optical proximity correction of L and T shaped patterns on negative photoresist
US6649309B2 (en) * 2001-07-03 2003-11-18 International Business Machines Corporation Method for correcting optical proximity effects in a lithographic process using the radius of curvature of shapes on a mask
US7861207B2 (en) * 2004-02-25 2010-12-28 Mentor Graphics Corporation Fragmentation point and simulation site adjustment for resolution enhancement techniques

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5815685A (en) * 1994-09-16 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Apparatus and method for correcting light proximity effects by predicting mask performance
US5825647A (en) * 1995-03-13 1998-10-20 Sony Corporation Correction method and correction apparatus of mask pattern

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1522889A2 (en) * 2003-10-10 2005-04-13 Synopsys, Inc. Method and apparatus for generating an OPC segmentation
EP1522889A3 (en) * 2003-10-10 2006-04-26 Synopsys, Inc. Method and apparatus for generating an OPC segmentation
US7451068B2 (en) 2003-10-10 2008-11-11 Synopsys, Inc. Method and apparatus for generating an OPC segmentation based on modeled intensity gradients
WO2007097838A2 (en) * 2006-02-21 2007-08-30 Mentor Graphics Corporation Grid-based resist simulation
WO2007097838A3 (en) * 2006-02-21 2007-10-18 Mentor Graphics Corp Grid-based resist simulation
US7378202B2 (en) 2006-02-21 2008-05-27 Mentor Graphics Corporation Grid-based resist simulation

Also Published As

Publication number Publication date
US20040088149A1 (en) 2004-05-06
WO2001042964A3 (en) 2002-03-14
US6643616B1 (en) 2003-11-04
AU2082001A (en) 2001-06-18
US7324930B2 (en) 2008-01-29

Similar Documents

Publication Publication Date Title
US6643616B1 (en) Integrated device structure prediction based on model curvature
EP1299824B1 (en) Convergence technique for model-based optical and proximity correction
US6516459B1 (en) Integrated circuit design correction using fragment correspondence
US6745372B2 (en) Method and apparatus for facilitating process-compliant layout optimization
EP1677221B1 (en) Method and apparatus for placing assist features in a layout
US7886262B2 (en) System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization
US6973633B2 (en) Caching of lithography and etch simulation results
JP4104574B2 (en) Improved method and apparatus for sub-micron IC design using edge fragment tagging to correct edge placement distortion
US6505327B2 (en) Generating an instance-based representation of a design hierarchy
JP4822330B2 (en) Integrated verification and manufacturing adaptation tools
US7155699B2 (en) Streamlined IC mask layout optical and process correction through correction reuse
US6282696B1 (en) Performing optical proximity correction with the aid of design rule checkers
US7337421B2 (en) Method and system for managing design corrections for optical and process effects based on feature tolerances
US7000208B2 (en) Repetition recognition using segments
US20060228041A1 (en) Optical lithography verification process
US20100269084A1 (en) Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography
JP2011514654A (en) Improvement of uniformity for semiconductor pattern forming work
US8429572B2 (en) Method and system for implementing controlled breaks between features using sub-resolution assist features
US10732499B2 (en) Method and system for cross-tile OPC consistency
Awad et al. A fast process-variation-aware mask optimization algorithm with a novel intensity modeling
US20230408901A1 (en) Optical proximity correction for free form shapes
Kachwala et al. Integrating RET and mask manufacturability in designs for local interconnect for sub-100-nm trenches

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP