WO2001043186A1 - Body contacted silicon-on-insulator (soi) structure and method of fabrication - Google Patents

Body contacted silicon-on-insulator (soi) structure and method of fabrication Download PDF

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Publication number
WO2001043186A1
WO2001043186A1 PCT/US2000/032923 US0032923W WO0143186A1 WO 2001043186 A1 WO2001043186 A1 WO 2001043186A1 US 0032923 W US0032923 W US 0032923W WO 0143186 A1 WO0143186 A1 WO 0143186A1
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Prior art keywords
region
semiconductor body
bulk
semiconductor
sidewalls
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PCT/US2000/032923
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French (fr)
Inventor
Young-Jin Park
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Infineon Technologies North America Corp.
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Publication of WO2001043186A1 publication Critical patent/WO2001043186A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Definitions

  • the method comprises the steps of: masking a top portion of the semiconductor body with a first masking layer to define at least one area thereof which is to become the region; etching trenches in at least one portion of the semiconductor body defined by the mask which partially separates the semiconductor body into two portions with one portion being the bulk and the other portion being the region being formed which comprises sidewalls and a top surface; forming a second masking layer on the sidewalls of the region; etching the trenches so as to laterally extend same so as to define a bottom surface of the region while leaving at least one portion of the bottom surface in contact with the bulk of the semiconductor body therebelow; forming an electrically insulating layer on exposed portions of the bulk and region so as to electrically isolate the region from the bulk except for a common portion of both; and filling the trenches with an insulating material.
  • FIG. 1 shows a semiconductor structure in accordance with the present invention
  • FIGS. 8, 9, and 10 show a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of a semiconductor structure comprising a transistor in accordance with the present invention

Abstract

A semiconductor structure includes a substrate (body) with a plurality of regions which are each dielectrically isolated on all sidewalls and on portions of bottom surfaces thereof from each other and from the substrate except for a portion of the bottom surface of each region which is common with the substrate. The structure is fabricated from a semiconductor substrate whose bulk is of one conductivity type. The substrate is first masked to define the plurality of regions and then subjected to an etch which defines sidewalls of each of the regions. The bottoms of each of the etched sidewalls are then subject to a lateral etch to define a bottom surface for each region with a portion of the bottom surface of each region left non-etched and in contact with the substrate. The resulting semiconductor structure achieves most of the advantage of a conventional SOI structure without the disadvantage of the floating body effect or the need to bias each region by making a separate top surface contact to same.

Description

BODY CONTACTED SILICON-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FABRICATION
Field of the Invention
This invention relates to integrated circuits manufactured using a Silicon-On-lnsulator (SOI) like technology, and more particularly, to a SOI like structure and a method of fabrication thereof. Background of the Invention
Integrated circuits composed of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) have become the workhorse of the semiconductor industry. These integrated circuits contain from two to several million MOSFETs fabricated on a common semiconductor body. An individual MOSFET comprises a pair of regions of one conductivity type which have been formed in a semiconductor body and which are spaced apart by an intermediate portion of the semiconductor body which is of the opposite semiconductor type. Current flow between electrodes attached to these two spaced apart regions is controlled by an electrode (gate) positioned at a top surface adjacent the intermediate region which is electrically insulated therefrom by a thin layer of silicon dioxide that is formed by oxidizing a surface layer of the intermediate region. In operation, a voltage applied to the gate of sufficient magnitude and polarity to invert the conductivity type of the intermediate region gives rise to a conductive channel between the two spaced regions in which current flows when a suitable voltage is established by electrode connections to the two spaced apart regions. The two spaced apart regions are usually identified as the source and drain of the field effect transistor. The intermediate region between the source and drain is usually identified as the channel region.
It is well known that, unless suitable precautions are taken, unwanted, parasitic current can, and will, flow between various elements of the integrated circuit. Parasitic current can flow between the source and drain region. It may not be controlled by the gate potential. Parasitic current can also flow between the source and drain regions of adjacent but separate transistors, and again is not controlled by the potential applied to the gates of the various transistors.
Various methods are in common use to reduce the magnitude of, or in some cases completely suppress, the various parasitic currents which can flow in an integrated circuit. One such method is to diffuse into the surface region of the semiconductor body, exterior to the source, drain and channel regions, impurities which increase the impurity concentration of the exterior regions such that the conductivity type of same can not be easily inverted. Such a diffusion is known as a "channel stop" or "chanstop" diffusion. In these regions, the potential required to invert the conductivity type of the surface of the semiconductor body is greater than such potential in the channel region of the transistor, and is usually designed to be greater than the maximum potential applied to the integrated circuit.
Another method of reducing or suppressing the various parasitic currents is to form in the region exterior to the channel region an oxide whose thickness is greater than the thickness of the oxide formed under the gate electrode in the intermediate or channel region of the transistor. Again, in these regions, the potential at the top surface of the thicker oxide required to invert the surface of the semiconductor body will be greater than such potential in the channel region of the transistor, and is usually designed to be greater than the maximum potential applied to the integrated circuit.
Often, these two methods are combined in the effort to reduce or suppress the parasitic currents. Other methods which have been applied include the use of trenches filled with insulating material which are fabricated so as to completely surround and isolate each transistor, and the use of a field-shield, which is a conducting electrode formed over the region exterior to the source, drain channel region of the transistor, and which is connected to the lowest power supply potential applied to the integrated circuit. Such methods of reducing or suppressing the parasitic currents are further discussed in textbooks such as "Silicon Processing for the VLSI Era, Volume II, page 66, S. Wolf.
All of the above methods incur some expense or limitations, including increased manufacturing cost, increased processing complexity, and reduced or impaired circuit performance.
A device which limits parasitic current which is of a completely different nature than those described above is the Silicon-On-lnsulator (SOI) device. In this device, the end result is that each individual transistor is completely encased in a protective insulating material which completely surrounds the transistor, thus preventing any parasitic current flow between adjacent transistors through a common substrate.
In one form of SOI, semiconductor films are deposited on an insulating substrate, islands of semiconductor film are defined, and the semiconductor film is completely removed from the region between the islands. This region is subsequently filled with an insulating material, and individual transistors are formed in the islands. Small sub-circuits consisting of a small number of transistors can also be formed in a given island of semiconductor material.
In another form of SOI, an insulating layer is formed on the surface of a semiconductor body, openings are formed in this insulating layer, and a film of semiconductor material is deposited on the insulating layer, contacting the semiconductor body through the holes formed in the insulating layer. Islands of the semiconductor film are defined, and the semiconductor film is completely removed from the region between the islands. This region is subsequently filled with an insulating material, and individual transistors are formed in the islands. Small sub-circuits consisting of a small number of transistors can also b formed in a given island of semiconductor material.
In yet another form of SOI, the starting material is a silicon semiconductor body on the surface of which isolated islands of silicon are formed by oxidizing the silicon surrounding and underneath the islands. This latter method is preferred in many cases because the starting material is semiconductor substrates which are of the same type as are being used for the manufacture of other types of integrated circuit, and also because the semiconductor properties of the resulting islands are superior to that of semiconductor islands formed in a film of semiconductor material formed on the surface of an insulating substrate. Another advantage of this method of forming SOI integrated circuits is the subject of this invention.
One weakness of these SOI techniques is that the islands of semiconductor material are not connected to a reference potential of the power supply, such as either ground or the highest potential supplied by the power source. In the conventional methods of forming an integrated circuit, the semiconductor body, and in the case of CMOS integrated circuits, the "well" also, is connected to one of the power supply terminals. In previously describe forms of SOI, the semiconductor islands are not connected directly to a reference potential, but are left unconnected, or "floating". This leads to an effect known as the "floating body effect" (FBE). The deleterious effect of FBE on the performance of SOI integrated circuits is well known, and has been described for example, in the article "Floating-Body Effects in Partially Depleted SOI CMOS Circuits, Lu et al., IEEE Journal of Solid State Circuits, Vol. 32, No. 8, August 1997". The effects of the FBE on circuit performance include extra power consumption, degraded noise margin and stability of the circuits, and, in certain dynamic circuits, logic state errors. These effects arise in part because of capacitive coupling between the semiconductor island and adjacent signal carrying conductor lines. The effect of the FBE on individual transistor characteristics include degraded breakdown voltage, a lowering of the threshold voltage at high drain potential, and hysteresis and instability during dynamic operation.
Prior art solutions to this problem have included the introduction of additional layers of interconnection which allow the connection of each individual semiconductor island to an appropriate reference potential. This requires an increase in the size of the integrated circuit because of the area which must be devoted to the connection of each individual semiconductor island to the interconnection layer, and also can require an increase in the number of process steps required to fabricate the integrated circuit. Both of these lead to higher manufacturing cost, and the increase in size can lead to lower performance of the integrated circuit.
In another prior art solution to the problems caused by the Floating- Body Effect, the starting material is a SOI semiconductor body which is fabricated by starting with a silicon semiconductor body into which oxygen ions are deeply implanted. The silicon semiconductor body is then annealed at a sufficiently high temperature so that the implanted oxygen atoms interact with the silicon semiconductor body to form a layer of insulating silicon dioxide buried beneath a surface layer of semiconducting silicon. Islands of silicon can then be formed in this semiconductor body by masking the region where islands are to be formed with a suitable material such as silicon nitride, and then oxidizing the surface of the semiconductor body to form regions of silicon dioxide which extend from the surface down to meet the buried layer of silicon dioxide which was formed previously. This results in the formation of completely isolated islands of silicon.
A further variation of this technology is to control this oxidation such that the oxidized regions extending down from the surface do not meet the underlying buried oxide layer, but leave a thin film of silicon connecting the bottoms of all the silicon islands. This form of SOI is referred to as Body- Contacted Silicon-On-lnsulator (BC-SOl) and is described in an article entitled "1 Giga Bit SOI DRAM with Fully Bulk Compatible Process and Body- Contacted SOI MOSFET Structure", by Koh et al., Digest of Technical Papers, International Electron Device Meeting, 1997.
It is desirable to limit the Floating-Body Effect (FBE) and improve the performance of integrated circuits fabricated using SOI technology by providing a structural method of fabrication in which individual islands of semiconductor material formed on the surface of a SOI semiconductor substrate may be connected to a common reference potential without requiring process techniques or processing equipment not normally employed in the fabrication of conventional MOSFET integrated circuits. Summary of the Invention
We have found that the Floating-Body Effect (FBE) in Metal-Oxide- Semiconductor Field Effect Transistors (MOSFETs) fabricated using Silicon- On-lnsulator (SOI) technology whereby individual islands of semiconductor material formed on the surface of a semiconductor substrate can be eliminated by introducing a novel process of substrate wet etching and oxidation during the formation of the semiconductor islands.
The process starts with a silicon semiconductor substrate. A masking layer of silicon nitride above a thin layer of silicon dioxide defines where islands of silicon are to be formed. The silicon is anisotropically etched to form columns of silicon capped with the silicon oxide - silicon nitride mask material, and the sides of these columns are then coated with a layer of silicon nitride, using conventional technology for doing this. The silicon substrate is then isotropically etched so as to undercut the columns of silicon, leaving silicon islands supported on a thin column of silicon attached to the underlying silicon substrate. The silicon substrate is then subjected to an oxidizing environment to form a layer of silicon dioxide on the surface of the silicon substrate, the underside of the silicon island and the sides of the supporting silicon column. The layer of silicon nitride on the sides of the silicon island may be optionally removed before this step in the process. A layer of insulating material such as silicon oxide or silicon nitride is then formed in a manner which will completely fill the voided area under the silicon islands and the area between silicon islands up to and above the surface of the original silicon nitride masking layer. The silicon substrate is then planarized, down to and removing the original silicon nitride masking layer. This leaves a silicon substrate with islands of silicon exposed on the top surface, the islands being completely surrounded by a sea of insulating material, except for a thin column of silicon connecting each island to the underlying silicon substrate, forming a BC-SOl substrate without requiring any process techniques or processing equipment not normally employed in the fabrication of conventional MOSFET integrated circuits.
Viewed from one apparatus aspect, the present invention is directed to a semiconductor structure which comprises a semiconductor body and a semiconductor region. The semiconductor region has sidewalls and a bottom surface which intersect. The sidewalls of the semiconductor region are physically separated from the bulk portion of the semiconductor body. Portions of the bottom surface which begin at the intersection with the sidewalls and extend towards a central portion of the bottom surface are also physically separated from the bulk portion of the semiconductor body. A portion of the bottom surface of the region is in contact with the semiconductor body.
Viewed from another apparatus aspect, the present invention is directed to a semiconductor structure which comprises a semiconductor body and a semiconductor legion. The semiconductor body has a bulk portion of one conductivity type and a top surface. The semiconductor region is of the one conductivity type, is located in a portion of the semiconductor body, and has a top surface and having sidewalls and a bottom surface. Bottom portions of the sidewalls intersect the bottom surface and top portions of the sidewalls intersect the top surface of the semiconductor region. The sidewalls of the semiconductor region are dielectrically isolated from the bulk portion of the semiconductor body. Portions of the bottom surface are electrically isolated from the bulk portion of the semiconductor body with at least one portion of the bottom surface being in contact with the bulk of the semiconductor body.
Viewed from a process aspect, the present invention is directed to a method of forming in a semiconductor body having a bulk portion a region which is electrically isolated from the body except for a portion of a bottom surface thereof. The method comprises the steps of: defining a portion of a top surface of the semiconductor body which is to be the top surface of the region to be formed; removing portions of the bulk of the semiconductor body around the defined top surface of the region to be formed to form sidewalls which partially define the region to be formed; and removing portions of the bulk of the semiconductor body from lower portions of the sidewalls under the top surface area of the region being formed so as to define a bottom surface of the region while leaving a portion of the bulk of the semiconductor body in contact with the region.
Viewed from an other process aspect, the present invention is directed to a method of forming in a semiconductor body having a bulk portion of one conductivity type a region which is electrically isolated from the body except for a portion of a bottom surface thereof. The method comprises the steps of: masking a top surface of the semiconductor body so as to define a region to be formed; removing vertical portions of the bulk of the semiconductor body to define sidewalls which further define the region to be formed; removing lateral portions of the bulk at a bottom of the sidewalls so as to define a bottom surface of the region to be formed while leaving a portion of the bulk extending into the region to be formed; and filling the removed vertical and lateral portions with a material which electrically isolates the region from much of the bulk of the semiconductor body.
Viewed from still an other process aspect, the present invention is directed to a method of forming at least one region of one conductivity type in a semiconductor body of the same conductivity type with the region having sidewalls that are dielectrically isolated from the semiconductor body and having a bottom surface that is electrically isolated from the semiconductor body except for at least one portion thereof which contacts the semiconductor body. The method comprises the steps of: masking a top portion of the semiconductor body with a first masking layer to define at least one area thereof which is to become the region; etching trenches in at least one portion of the semiconductor body defined by the mask which partially separates the semiconductor body into two portions with one portion being the bulk and the other portion being the region being formed which comprises sidewalls and a top surface; forming a second masking layer on the sidewalls of the region; etching the trenches so as to laterally extend same so as to define a bottom surface of the region while leaving at least one portion of the bottom surface in contact with the bulk of the semiconductor body therebelow; forming an electrically insulating layer on exposed portions of the bulk and region so as to electrically isolate the region from the bulk except for a common portion of both; and filling the trenches with an insulating material.
The apparatus and method of the present invention will be better understood from the following drawings, detailed description, and claims. Brief Description of the Drawing
FIG. 1 shows a semiconductor structure in accordance with the present invention;
FIGS. 2, 3, and 4 illustrate a process for fabricating the structure of FIG. 1 in accordance with the present invention;
FIGS. 5, 6, and 7 show a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of a semiconductor structure comprising a transistor in accordance with the present invention;
FIGS. 8, 9, and 10 show a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of a semiconductor structure comprising a transistor in accordance with the present invention;
FIGS. 11 , 12, and 13 show a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of a semiconductor structure comprising a transistor in accordance with the present invention; and
FIG. 14 shows a cross-sectional view of a semiconductor structure in accordance with the present invention. Detailed Description
Referring now to FIG. 1 , there is shown a cross-sectional view of a semiconductor structure 10 in accordance with the present invention. Structure 10 comprises a semiconductor substrate 12 of one conductivity type within which are formed a plurality of semiconductor regions (islands), of which just two, 14a and 14b, are shown. Typically substrate 12 is silicon. Regions 14a and 14b are both of the same type of conductivity as substrate 12, and as will be shown herein below, are portions of substrate 12 before same is processed to form structure 10. Sidewalls 14aa and 14bb of regions 14a and 14b, respectively, are each lined with an insulator layer 16, typically silicon nitride. The space between adjacent layers 16 and that under all but a central portion 14aaa and 14bbb of regions 14a and 14b, respectively, is filled with an insulating (dielectric) material, typically silicon oxide. Regions 14a and 14b are thus electrically isolated from the each other and from substrate 12 except in regions 14aaa and 14bbb. This allows a bias potential applied to substrate 12 to be applied to regions 14a and 14b. This bias potential greatly reduces the "floating body effect" (FBE) which exists with conventional SOI structures in which each island electrically floats in potential. It also eliminates the need for an individual surface electrical contact to each region (island) which has been used with some SOI structures. This reduces the needed size of each of the regions.
Within each of the regions 14a and 14b can be formed a variety of different semiconductor components, including but not limited to metal-oxide- semiconductor transistors (MOS), complementary metal-oxide-semiconductor transistors (CMOS), bipolar transistors, resistors, capacitors, diodes, etc., which can form memory cells, logic circuits, or other types of circuits, etc.
A process to fabricate the structure 10 of FIG. 1 is illustrated in FIGS. 2, 3, and 4. FIG. 2 shows that starting with a semiconductor substrate 12 there is formed a silicon oxide layer 100 over a top surface of the substrate 12. A layer of silicon nitride 102 is then formed over the silicon oxide layer 100 and is patterned to leave openings 103 where the underlying layer 100 of silicon oxide is exposed.
The process continues, as is shown in FIG. 3, with an anisotropic etch which etches through the exposed portions of silicon oxide layer 100 and etches trenches 106 into substrate 12. A silicon nitride layer 104 is now formed on sidewalls of the layers 100 and 102 and the exposed sidewalls of the trenches 106 in substrate 12. Optionally, a thin layer of silicon oxide may be formed on any exposed silicon surface before layer 104 is formed.
The process continues, as is shown in FIG. 4, with an isotropic etch which removes semiconductor material at the bottom of each of the trenches in substrate 12 in both vertical and lateral directions so as to create a lateral cavity 106a in substrate 12 which extends all around the bottom of the vertical trenches 106 formed in substrate 12.
The process continues with an oxidation step which forms a layer of silicon oxide over all exposed semiconductor surfaces. Optionally, the silicon nitride layer 106 may be removed before or after this oxidation step. A layer of insulating (dielectric) material, such as silicon oxide, is then added to completely fill the trenches and lateral cavities and to coat the silicon nitride top layer 102. The insulating material is typically Chemical Vapor Deposited (CVD) silicon oxide carried out by using one of the processes consisting of the group of: a. thermally activated, b. low pressure CVD, c. plasma enhanced CVD, d. high density plasma CVD, and e. any combination of a., b., c, and d. The resulting structure is then planarized down to the original surface of the semiconductor substrate 12 to arrive at the structure shown in FIG. 1.
It is to be noted that the shape of the mask around each of the regions 14a and 14b to be formed can be varied. This results in the portion(s) of the regions 14a and 14b which are in direct contact with the substrate 12 varying. For example, the contact to the substrate 12 can be a central area below region 14a and could be two parallel contact areas separated by an electrically insulating layer therebetween for region 14b.
FIG. 5 shows a top view of a metal-oxide-semiconductor transistor (MOS), typically denoted as an Insulated Gate Field Effect Transistor (IGFET), which can be formed in region 14a in accordance with the present invention. FIG. 6 shows a sectional view taken through a dashed line 6-6 of FIG. 5; and FIG. 7 shows a sectional view of FIG. 5 taken through a dashed line 7-7 of FIG. 5. As shown in FIG. 5, the transistor has a source electrode 30, a drain electrode 32 and a gate electrode 34. A rectangular mask 36 is shown relative to electrodes 30, 32, and 34 and serves to define the surface width and length of region 14a (shown in FIGS. 6 and 7). A dashed rectangle 38 is shown separated from the sides of the mask 36 by a distance 40. The distance 40 corresponds to the distance that is etched below the region 14a (shown in FIGS. 6 and 7) and is then filled with an electrically isolating material.
FIG. 6 shows the gate electrode 34, a gate oxide layer 42, and the portion 14aaa of region 14a which is in direct contact with substrate 12. It is noted the width of portion 14aaa is reduced from the width of portion 14a by two times the distance 40.
FIG. 7 shows the electrodes 30, 32, and 34, a gate oxide layer 42, a drain region 44, and a source region 46. An insulating layer 19, typically silicon oxide, serves to isolate the electrodes 30, 32, and 34. The portion 14aaa of region 14a which is in direct contact with substrate 12 is reduced by twice distance 40 but is still substantially greater than the corresponding distance in the vertical direction. Thus the area 14aaa of region 14a which directly contacts substrate 12 is a rectangle whose length is considerably longer than its width.
FIG. 8 shows a top view of the same IGFET as is shown in FIGS. 5, 6, and 7, but the region 14a was defined using a mask 50 which has a dog bone shape as compared to the rectangular shape of the mask 30 of FIG. 5; FIG. 9 shows a cross-sectional view taken through a dashed line 9-9 of FIG. 8; and FIG. 10 shows a cross-sectional view of FIG. 8 taken through a dashed line 10-10 of FIG. 8. As shown in FIG. 10, the transistor has a source electrode 30, a drain electrode 32 and a gate electrode 34. The narrow portion of dog bone mask 50 has a width of less than twice the distance 40. If distance 40 is etched all around mask 40 then the parts of region under the narrow portions thereof will be completely etched away and filled with electrical insulation as is shown in FIGS. 9 and 10. Region 14a makes direct contact with two portions of substrate 12, a first portion 14aaa1 under source region 44 and a second portion 14aaa2 under drain region 46.
FIG. 11 shows a top view of the same IGFET as is shown in FIGS. 5, 6, 7, 8, 9, and 10, but fabricated using a mask 60 which has a reverse dog bone shape as compared to the dog bone shape of mask 50 of FIG. 8. By reverse dog bone shape is meant that the middle section is thicker than the end sections. FIG. 12 shows a cross-sectional view taken through a dashed line 12-12 of FIG. 11 ; and FIG. 13 shows a cross-sectional view of FIG. 11 through a dashed line 13-13 of FIG. 11. As shown in FIG. 11 , the transistor has a source electrode 30, a drain electrode 32, and a gate electrode 34. The narrow portion of dog bone mask 50 has a width of less than twice the distance 40. If distance 40 is etched all around mask 60, then the portion of region 14a under the narrow part thereof will be completely etched away and filled with an electrical insulator as is shown in FIGS. 12 and 13. Region 14a makes direct contact with substrate 12 over a lessor area than is the case for the embodiment of FIGS. 5, 6, and 7.
Referring now to FIG. 14, there is shown a semiconductor structure
199 in accordance with the present invention. Structure 199 comprises a semiconductor substrate (body) 200 having a top surface 201 and being of one conductivity type. In body 200 there are typically formed a plurality of semiconductor regions 202 which are of the same conductivity type as body
200 and are separated from each other by dielectric regions 204 which has vertical portions 204a and horizontal portions 204b. Horizontal portion 204b has a thickness t2. For illustrative purposes only one complete region 202 is shown having a thickness t1. The portion of substrate 200 which contacts region 202 is shown by the reference number 202aaa. This basic structure can be fabricated as is taught hereinabove. Within the complete region 202 shown are two IGFETS which share a common drain region 206 that is of the opposite conductivity than that of the region 202. A drain electrode 216 is coupled to drain region 206. Spaced apart from drain region 206 to the right side thereof is a source region 210 and spaced apart on the left side thereof is a source region 208. Overlying a portion of top surface 201 between drain region 206 and source region 208 is a gate oxide layer 212 which has a gate electrode 218 thereover. Overlying a portion of top surface 201 between drain region 206 and source region 210 is a gate oxide layer 214 which has a gate electrode 220 thereover. The thickness of the semiconductor region 202 is shown as t1 and the thickness of the horizontal portion 204b of the dielectric region 204 is shown as t2. In an illustrative example, a DRAM, a first cell capacitor (not shown) is coupled to source region 208 and a second cell capacitor (not shown) is coupled to source region 210 to form two memory cells within region 202. Typically the gate electrode 218 is coupled to one word line (not shown) of a memory array and gate electrode 220 is coupled to a second different word line of the same memory array. A bit line of the memory array is coupled to drain electrode 216. This results in two memory cells, each comprising an IGFET and a capacitor, existing in region 202.
When either of the transistors of structure 199 are biased such that the junctions of either the common drain 206 or either of the sources 208 and 210 are reversed biased, a depletion region (not shown) is formed in the portion of the semiconductor region 202 below the transistor. The thickness of the formed depletion region (not shown) depends on the thickness and doping concentration of semiconductor region 202, the magnitude of the voltage biasing the sources and drain, and the doping concentration of the sources and drain. The formed depletion regions can extend down to the top of region 204b. If the depletion region extends down close to the top surface of region 204b, the junction capacitance of sources regions 208 and 210 and drain region 206 is a function of the impurity concentration of essentially the entire thickness t1 of region 202. If the depletion region extends down to and touches the top of region 204b, the corresponding junction capacitance is the series combination of the capacitance associated with the entire thickness t1 of region 202 and the capacitance associated with the entire thickness t2 of region 204b. The capacitance of the series combination is lower than that of just the capacitance of the depletion region extending through most of thickness t1. If the depletion region does not reach through all of thickness t1 of region 202, then the location of region 202aaa does not affect the junction capacitance. If the depletion region does reach through all of thickness t1 of region 202, then by locating region 202aaa under the common drain 206, as compared to under one of the sources 208 and 210, the source junction capacitance is reduced. The thickness t1 can be selected along with the turn- on gate voltage level and the doping levels of the drain, source, and region 202 such that the depletion regions formed will intersect the top surface of the horizontal portion 204b of dielectric region 204.
The common region 202aaa of substrate 200 and region 202 can, by appropriate selection of the geometry of an etch limiting mask, be located anywhere desired under region 202. The performance of components located in region 202 can be optimized by the location of the common region 202aaa. In addition, there can be formed more than one common region 202aaa.
It is to be understood that the particular structures and processes described are merely illustrative of the general principles of the invention. Various modifications are possible without departing from the spirit and scope of the invention. For example, the semiconductor body could be of p-type or n-type conductivity or could be gallium arsinide and other dielectric materials than silicon oxide or silicon dioxide could be used to fill the trenches. Further, transistors having geometries which are different than those described can be used. Furthermore, the concepts described herein may be applied to other types of devices and transistors, such as, for example, bipolar transistors, and in general to the fabrication of all types of semiconductor devices where it is necessary to reduce the parasitic current flowing between various devices, and also to provide a known potential to the silicon material in which the device is fabricated.

Claims

What is Claimed is:
1. A semiconductor structure comprising: a semiconductor body; a semiconductor region having sidewalls and a bottom surface which intersect; the sidewalls of the semiconductor region being physically separated from the bulk portion of the semiconductor body; portions of the bottom surface which begin at the intersection with the sidewalls and extend towards a central portion of the bottom surface being physically separated from the bulk portion of the semiconductor body; and a portion of the bottom surface of the region being in contact with the semiconductor body.
2. A semiconductor structure comprising: a semiconductor body having a bulk portion of one conductivity type and a top surface; a semiconductor region of the one conductivity type located in a portion of the semiconductor body and having a top surface and having sidewalls and a bottom surface, bottom portions of the sidewalls intersecting the bottom surface and top portions of the sidewalls intersecting the top surface of the semiconductor region; the sidewalls of the semiconductor region being dielectrically isolated from the bulk portion of the semiconductor body; and portions of the bottom surface being electrically isolated from the bulk portion of the semiconductor body with at least one portion of the bottom surface being in contact with the bulk of the semiconductor body.
3. A method of forming in a semiconductor body having a bulk portion a region which is electrically isolated from the body except for a portion of a bottom surface thereof comprising the steps of: defining a portion of a top surface of the semiconductor body which is to be the top surface of the region to be formed; removing portions of the bulk of the semiconductor body around the defined top surface of the region to be formed to form sidewalls which partially define the region to be formed; and removing portions of the bulk of the semiconductor body from lower portions of the sidewalls under the top surface area of the region being formed so as to define a bottom surface of the region while leaving a portion of the bulk of the semiconductor body in contact with the region.
4. The method of claim 3 further comprising the step of filling the removed portions of the bulk of the semiconductor body with an electrically insulating material.
5. A method of forming in a semiconductor body having a bulk portion of one conductivity type a region which is electrically isolated from the body except for a portion of a bottom surface thereof comprising the steps of: masking a top surface of the semiconductor body so as to define a region to be formed; removing vertical portions of the bulk of the semiconductor body to define sidewalls which further define the region to be formed; removing lateral portions of the bulk at a bottom of the sidewalls so as to define a bottom surface of the region to be formed while leaving a portion of the bulk extending into the region to be formed; and filling the removed vertical and lateral portions with a material which electrically isolates the region from much of the bulk of the semiconductor body.
6. A method of forming at least one region of one conductivity type in a semiconductor body of the same conductivity type with the region having sidewalls that are die .ctrically isolated from the semiconductor body and having a bottom surface that is electrically isolated from the semiconductor body except for at least one portion thereof which contacts the semiconductor body, said method comprising the steps of: masking a top portion of the semiconductor body with a first masking layer to define at least one area thereof which is to become the region; etching trenches in at least one portion of the semiconductor body defined by the mask which partially separates the semiconductor body into two portions with one portion being the bulk and the other portion being the region being formed which comprises sidewalls and a top surface; forming a second masking layer on the sidewalls of the region; etching the trenches so as to laterally extend same so as to define a bottom surface of the region while leaving at least one portion of the bottom surface in contact with the bulk of the semiconductor body therebelow; forming an electrically insulating layer on exposed portions of the bulk and region so as to electrically isolate the region from the bulk except for a common portion of both; and filling the trenches with an insulating material.
7. The method of claim 6 wherein the insulating material is extended above the first masking layer and the top surface and then the first masking layer and a portion of the insulating material which extends above the top surface of the semiconductor body are both removed so as to planahze the resulting structure and expose a top surface of the region which comprises a portion of the original top surface of the semiconductor body.
8. The method of claim 6 wherein the mask layer which partially defines the region is selected from the group consisting of silicon dioxide, silicon nitride, and a combination of silicon dioxide and silicon nitride.
9. The method of claim 6 wherein the masking layer used on the sidewalls of the trenches is silicon nitride.
10. The method of claim 6 wherein the insulating material deposited is Chemical Vapor Deposited (CVD) silicon oxide carried out by using one of the processes consisting of the group of: a. thermally activated, b. low pressure CVD, c. plasma enhanced CVD, d. high density plasma CVD, and e. any combination of a., b., c, and d.
11. The method of claim 6 wherein multiple separated regions are formed.
12. The method of claim 6 wherein transistors are subsequently fabricated in the region formed.
13. The method of claim 12 wherein the regions formed may contain a plurality of transistors of different conductivity types.
14. The method of claim 6 wherein each of the regions formed may contain a plurality of transistors, diodes, capacitors, and resistors, and/or resistors.
PCT/US2000/032923 1999-12-13 2000-12-05 Body contacted silicon-on-insulator (soi) structure and method of fabrication WO2001043186A1 (en)

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EP1229579A2 (en) * 2001-01-25 2002-08-07 Chartered Semiconductor Manufacturing, Inc. Method to form a balloon shaped shallow trench isolation structure (STI) using a selective etching step
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CN104425338A (en) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 Method for improving the narrow width effect of shallow trench isolation structure

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