WO2001052226A3 - A liquid crystal display with pixels including latch circuits - Google Patents

A liquid crystal display with pixels including latch circuits Download PDF

Info

Publication number
WO2001052226A3
WO2001052226A3 PCT/GB2001/000096 GB0100096W WO0152226A3 WO 2001052226 A3 WO2001052226 A3 WO 2001052226A3 GB 0100096 W GB0100096 W GB 0100096W WO 0152226 A3 WO0152226 A3 WO 0152226A3
Authority
WO
WIPO (PCT)
Prior art keywords
latch means
data
significance
liquid crystal
crystal display
Prior art date
Application number
PCT/GB2001/000096
Other languages
French (fr)
Other versions
WO2001052226A2 (en
Inventor
David William Macintosh
Paul Barron Holmes
Martin John Birch
Original Assignee
Micropix Technologies Ltd
David William Macintosh
Paul Barron Holmes
Martin John Birch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micropix Technologies Ltd, David William Macintosh, Paul Barron Holmes, Martin John Birch filed Critical Micropix Technologies Ltd
Priority to AU2001225332A priority Critical patent/AU2001225332A1/en
Publication of WO2001052226A2 publication Critical patent/WO2001052226A2/en
Publication of WO2001052226A3 publication Critical patent/WO2001052226A3/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals

Abstract

A liquid crystal display comprises an array of pixels having associated logic integrated into a semiconductor back plane. The logic includes a plurality of first latch means (12,14), each having an output which is input to a multiplex latch means (19), the output of the multiplex latch means being displayed. One of the first latch means is selected to provide data to be loaded into the multiplex latch means, thereby enabling the first latch means to be updated with new data whilst other data is being displayed. In use, data bits having a first significance are viewed for a time which is longer than that for data bits having a lesser significance. The viewing time for the data bits having said first significance is divided into a plurality of shorter intervals, the other data bits being displayed in time slots interposed between successive intervals. Data having said first significance is stored in one of the first latch means, so that this data does not have to be reloaded for each interval.
PCT/GB2001/000096 2000-01-14 2001-01-11 A liquid crystal display with pixels including latch circuits WO2001052226A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001225332A AU2001225332A1 (en) 2000-01-14 2001-01-11 A liquid crystal display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0000715.3 2000-01-14
GB0000715A GB0000715D0 (en) 2000-01-14 2000-01-14 A liquid crystal display

Publications (2)

Publication Number Publication Date
WO2001052226A2 WO2001052226A2 (en) 2001-07-19
WO2001052226A3 true WO2001052226A3 (en) 2001-12-06

Family

ID=9883602

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/000096 WO2001052226A2 (en) 2000-01-14 2001-01-11 A liquid crystal display with pixels including latch circuits

Country Status (3)

Country Link
AU (1) AU2001225332A1 (en)
GB (1) GB0000715D0 (en)
WO (1) WO2001052226A2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0421772A2 (en) * 1989-10-06 1991-04-10 Canon Kabushiki Kaisha Display apparatus
EP0591683A1 (en) * 1992-09-04 1994-04-13 Canon Kabushiki Kaisha Display control apparatus
WO1999031651A1 (en) * 1997-12-18 1999-06-24 Intel Corporation Voltage signal modulation scheme
US5945972A (en) * 1995-11-30 1999-08-31 Kabushiki Kaisha Toshiba Display device
US5959598A (en) * 1995-07-20 1999-09-28 The Regents Of The University Of Colorado Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images
EP1026658A1 (en) * 1998-08-03 2000-08-09 Seiko Epson Corporation Electrooptic device, substrate therefor, electronic device, and projection display

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0421772A2 (en) * 1989-10-06 1991-04-10 Canon Kabushiki Kaisha Display apparatus
EP0591683A1 (en) * 1992-09-04 1994-04-13 Canon Kabushiki Kaisha Display control apparatus
US5959598A (en) * 1995-07-20 1999-09-28 The Regents Of The University Of Colorado Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images
US5945972A (en) * 1995-11-30 1999-08-31 Kabushiki Kaisha Toshiba Display device
WO1999031651A1 (en) * 1997-12-18 1999-06-24 Intel Corporation Voltage signal modulation scheme
EP1026658A1 (en) * 1998-08-03 2000-08-09 Seiko Epson Corporation Electrooptic device, substrate therefor, electronic device, and projection display

Also Published As

Publication number Publication date
AU2001225332A1 (en) 2001-07-24
GB0000715D0 (en) 2000-03-08
WO2001052226A2 (en) 2001-07-19

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