WO2001054348A1

WO2001054348A1 - Address translation table for fast atm protection switching

Info

Publication number: WO2001054348A1
Application number: PCT/US2001/001704
Authority: WO
Inventors: Dhadesugoor R. Vaman; Dongsoo S. Kim; Joonbum Byun
Original assignee: Megaxess, Inc.
Priority date: 2000-01-20
Filing date: 2001-01-18
Publication date: 2001-07-26
Also published as: AU2001230971A1

Abstract

A method and apparatus for fast ATM protection switching includes an ATM translation table that contains two pairs of address mapping entries, one for working entity (48) and one for protection entity (50). A Boolean variable indicates which entity is current (44). When a protection switching is needed, the microprocessor initiates a command to the ATM layer device by giving a group identifier or a representative connection identifier (34, 36, 38, 40). The digital logic algorithm traverses all entries in the group and modifies Boolean variables in the group without interfering with the microprocessor.

Description

ADDRESS TRANSLATION TABLE FOR FAST ATM PROTECTION SWITCHING

SPECIFICATION BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The present invention relates to a memory structure of the translation table in an asynchronous transfer mode (ATM) layer device and its supportive digital logic algorithm. This invention provides fast VP/VC (virtual path/virtual channel) group protection switching for ATM layer devices and supports hitless protection switching by minimizing the delay variance of protection switching time.

RELATED ART The International Telecommunications Union - Telecommunication

Standardization Sector's (ITU-T) draft 1.630 Recommendation provides mechanisms for ATM protection switching. The functionality of ATM protection switching is achieved by allocating the resources for protection entities. The resources are pre-assigned routes and pre-allocated bandwidths. Although the Recommendation addresses how to utilize the route resources, it does not specify how to implement the mechanisms. The protection switching operation must be completed as fast as possible to minimize to loss of information during the operation. Fast protection switching is essential to achieve a hitless protection switching operation. A virtual connection in an ATM network is established by modifying the virtual path identifier (VPI) and/or virtual channel identifier (VCI) in an ATM header at each ATM layer device, or simply a cell processor. Based on the identifiers, a switching fabric can route ATM cells to different network paths. The ATM layer device has the translation information for one-to-one mapping. To provide protection switching, a microprocessor changes the translation information. Because the table is not directly connected to the microprocessor to provide fast address translation for ATM cell flows, the microprocessor uses either a direct memory access (DMA) interface or some specialized interface that has little impact on the ATM cell flows. In the scale of several thousands, however, the microprocessor cannot avoid significant delay in translation time because of limited processing speed of the microprocessor and because of the limitation of bandwidth between the microprocessor and the ATM layer device. During the unintended delay, many ATM cells are lost because the route is already failed when the protection switching is required.

OBJECTS AND SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a method and apparatus for fast VP/VC switching for ATM layer devices.

It is an additional object of the present invention to provide a method and apparatus for supporting hitless protection switching.

It is even an additional object of the present invention to provide a method and apparatus which minimizes the delay variance of protection switching time.

It is still an additional object of the present invention to provide a method and apparatus which provides a memory translation table in an ATM layer device. These and other objects are achieved by the present invention, which provides an ATM translation table containing two pairs of address mapping entries, one for the working entity and one for the protection entity. A Boolean variable indicates which entity is a current entity. When a protection switching is needed, the microprocessor initiates a command to the ATM layer device by giving a group identifier (or a representative connection identifier). The digital logic algorithm traverses all entries in the group and modifies Boolean variables in the group without interfering with the microprocessor.

BRIEF DESCRIPTION OF THE DRAWINGS Other important objects and features of the invention will be apparent from the following Detailed Description of the Invention taken in connection with the accompanying drawings in which: FIG. 1 is a bock diagram of ingress and egress data flow in an ATM layer architecture;

FIGS. 2a and 2b are diagrams of the logical data structure of the destination target table and its projection for data traffic; and

FIG. 3 is a bock diagram of the architecture of the address translation table and its digital logic algorithm.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a general ATM layer architecture. In FIG. 1, microprocessor 12 is connected to virtual path identifier (VPI) and/or virtual channel identifier (VCI) modification unit 14. Under control of microprocessor 12, the unit 14 receives inputs from Physical Layer PHY at 16 and from SWITCH at 18. Unit 14 has outputs to PHY at 20 and to SWITCH at 22. Unit 14 contains ingress VP/VI lookups 24 and egress address translation from PHY 16 and to

PHY 20, respectively, and ingress address translation 28, egress VP/VC lookup

30, and address translation table 32. Ingress VP/VC lookup 24 is connected to input from PHY 16. The outputs of lookup 24 are connected to address translation table 32 and to ingress address translation 28. Ingress address translation 28 receives inputs from ingress VP VC lookup 24 and from address translation table 32. The output of ingress address translation 28 is connected to SWITCH 22. Egress VP/VC lookup 30 receives its input from SWITCH 18. The outputs of egress VP/VC lookup 30 are connected to egress address translation 26 and to address translation table 32. Egress address translation 26 receives inputs from egress VP/VC lookup 30 and from address translation table 32. The output of ingress VP/VC lookup 26 is connected to PHY 20.

Referring to FIG. 1, the left side is physical layer, 16, 20, and the right side is switch interface 22, 18. The upper portion is the ingress portion and the traffic flow is from the physical layer 16 to switch 22. The lower portion is the egress portion and the traffic flow is from switch 18 to a physical device 20. Ingress and egress traffic share address translation table 32 to exchange the address information. Actual cell traffic data travels along path A from Ingress VP/VC Lookup 24 to Ingress Address Translation 28. Travelling along Arrow B from 24 to 32 is the ATM address to find the information in an Address Translation Table 32, and then that new information is sent along Arrow C from 32 to 28 and then combined with the traffic cells from box 24. The same thing happens for egress traffic. FIGS. 2a and 2b show the logical data structure of destination target table and its projection for data traffic. In FIG. 2a, a protection address table (PAT) is used in conjunction with a digital logic algorithm to minimize interaction between the ATM layer device and the microprocessor for group protection switching. The PAT maintains information for both the working entity and the protection entity. The digital logic algorithm selects one of two entities indexed by a Boolean variable for ATM cells. The entries in the table are grouped. The microprocessor changes all Boolean variables in a group by indicating its group identifier (GI) or its representative connection identifier (CI). Each entry in the context parameter table conceptually has a functionality of one- to-two mapping for ingress traffic and two-to-one mapping for egress traffic. The decision whether to choose one mapping out of two is dependent on a Boolean bit variable called CURRENT. If CURRENT is 0(1), the current path is the protection entity (the working entity).

In FIG. 2a, the first and second groups 34 and 36 consist of three connections, but the third and forth groups 38 and 40 contain only one connection each. The number of connections are shown in the INDEX column 42. The next column 44 (CURRENT) is a Boolean value indicating which pair of translation address is used for ATM cell switching. The next column 46 (INCOMING TRANS) is the incoming address for ingress traffic, possibly containing physical link identifier, VPI and VCI. The next columns 48 (WORKING TRANS) and 50 (PROTECT TRANS) are the translation addresses for the working entity and the protection entity. Note that this logical structure assumes a symmetric VP/VC translation, which means that ingress traffic translation is x → y if and only if egress traffic translation is y — » . Even though the table contains both working and protection translation in one row, ATM data traffic looks for only one mapping depending on the Boolean variable. FIG. 2b shows the relationship between the setting of the CURRENT value for each index on INGRESS TRANS 52 and EGRESS TRANS 54. For example, as shown in FIG. 2b, the CURRENT field 44 in FIG. 2a at the first entry in 34 (GROUP 1) is 0, so that ingress traffic 52 has 30 → 130 mapping and egress traffic 54 has 130 → 30 mapping. The CURRENT field 44 at the index 42 (number 6) in FIG. 2a, 36 (GROUP 2) has the value of 1 ; therefore both ingress traffic 52 and egress traffic 54 has 36 → 36 mapping. FIG. 3 is a diagram of the architecture of an address translation table and its digital logic structure showing a hardware implementation of the invention. In FIG. 3, the index of the Context Translation Table 56 is computed by a separate mapping function called VP or VC table. The mapping function generates a connection identifier (CI) for the context parameter table. After finding one entry in the parameter table by using the CI, ingress traffic refers only ingress translation and ingress parameter, and egress traffic refers only egress translation and egress parameter. Henceforth, ingress and egress mappings do not need to be symmetric. When the table is initially configured, the entries can be grouped with the connection identifier in a circular linked list form. The hardware algorithm updates one entry to next by following the linked list.

The table 56 receives inputs from an Entry Selector and Update source 58. The outputs of the table are to a multiplexer 60. The multiplexer 60 receives an additional input from Entry Selector and Update source 58 and is connected to increment NEXTCI 62. FIFO 64, which is controlled by FIFO control 66, is connected to request register (RR) 68. The request register 68 has four parameters. Parameter CI 72 is connected to incrementer 62 and to an end- switching detector 70. Parameters DIR 74 and PROT 76 are connected to Entry Selector and Update source 58. Parameter IND 78 is connected to detector 70. The context parameter table 1 contains at least seven fields in each row as follows:

• ET Egress Translation

• WIT Working Ingress Translation • PIT Protection Ingress Translation

• EP Egress Parameter. This has (CURRENT, PATH) bits. The CURRENT bit indicates a dynamic status of the egress translation, 0 and 1 indicate that the current status is working connection or protection connection, respectively. The PATH bit indicates a static configuration of the egress translation. 0 indicates the egress translation set as working, and 1 indicates the egress translation configured as protection. • IP Ingress Parameter. This has a CURRENT bit, 0 indicates that WIT is current but 1 indicates that PIT is current

• NECI Next Egress Connection Indicator to make a group in the linked list for egress connection.

• NICI Next Ingress Connection Indicator to make a group in linked list for ingress connection.

The parameter table may include additional properties for traffic policing and flow control. The CT table described herein includes only those properties needed for fast protection switching. ET, WIT and PIT are the translation address containing a physical link identifier (PLI), a virtual path identifier (VPI) and a virtual circuit identifier (VCI).

EP is an egress switching parameter. This field contains (CURRENT, PATH) bits. The cell processor refers this value to decide whether it drops an egress ATM cell or not as follows:

IP is an ingress switching parameter. The CURRENT bit in this field is used for selecting one translation address from WIT or PIT for an ingress ATM cell. NECI and NICI are the index of the next entry. The entries are grouped using these fields as linked lists, separately for egress translation entries and for ingress translation entries. The last entry in a group indexes the first entry in a circular linked list. If a group has only one entry, the next index points to itself. Protection switching is performed by updating the CURRENT Boolean bit in EP and or IP. As shown in FIG. 3, the request register (RR) 68, of the modification contains four parameters, Connection Identifier (CI) 72, Direction (DIR) 74, Protection (PROT) 76, and Individual (IND) 78. DIR 74, indicates the target direction, egress (0) or ingress (1). PROT 76, indicates the protecting entity, protection entity (0) or working entity (1). IND 78, indicates whether the request is individual protection switching (1) or group protection switching (0) compliant to 1.630. The hardware algorithm for the fast group protection switching is as follows:

Algorithm: Update address translation table Input: Requests are pending in the FIFO buffer 64.

Request Register (RR) consists of Connection Identifier (CI), Direction (DIR), Protection (PROT) and Individual (IND). Method: while there is an entry in the FIFO do move the first entry in the buffer to RR. move RR.CI to NEXTCI. repeat find an entry in the Context Table (CT) with NEXTCI. if RR.DIR = EGRESS then CT.EP.CURRENT := RR.PROT

NEXTCI := CT.NECI else

CT.IP.CURRENT := RR.PROT

NEXTCI := CT.NICI endif until RR.IND = TRUE or RR.CI = NEXTCI end do

Having thus described the invention in detail, it is to be understood that the foregoing description is not intended to limit the spirit and scope thereof. What is desired to be protected by Letters Patent is set forth in the appended claims.

Claims

CLAIMS What is claimed is:

1. A method of providing fast ATM layer device protection switching comprising the steps of: providing an ATM translation table containing two pairs of address mapping entries, one for working entity and one for protection entity and having a Boolean variable indicating which entity is a current entity; when protection switching is required, initiating a command to the ATM layer device by giving a group identifier or a representative connection identifier; and traversing all entries in a group and modifying said Boolean variables in the group.

2. The method of claim 1 wherein said command is generated by a microprocessor.

3. The method of claim 2 wherein said Boolean variables in the group are modified without interfering with the microprocessor.

4. A method of providing fast ATM layer device protection switching comprising the steps of: providing a translation table in an ATM layer device containing routing information for both working entity and protection entity indexed by a Boolean variable; and when protection switching is required, initiating a command to the ATM layer device by giving a group identifier or a representative connection identifier.

5. The method of claim 4 wherein entries in said translation table are grouped for fast protection switching.

6. The method of claim 4 further including the step of modifying said translation table for group protection switching by digital logic.

7. The method of claim 4 wherein said command is a one-bit Boolean value per connection.

8. An apparatus for providing fast ATM layer device protection switching comprising: an ATM translation table containing two pairs of address mapping entries, one for working entity and one for protection entity and having a Boolean variable indicating which entity is a current entity; means connected to said translation table for initiating a command to the ATM layer device when protection switching is required, by giving a group identifier or a representative connection identifier; and means connected to said translation table for traversing all entries in a group and modifying said Boolean variables in the group.

9. The apparatus of claim 8 wherein said command is generated by a microprocessor.

10. An apparatus for providing fast ATM layer device protection switching comprising: a translation table in an ATM layer device, said translation table containing routing information for both working entity and protection entity indexed by a Boolean variable; means connected to said translation table for initiating a command to the ATM layer device when protection switching is required by giving a group identifier or a representative connection identifier.

11. The apparatus of claim 10 further including means connected to said translation table for traversing all entries in a group and for modifying Boolean variables in said group.