WO2001059819A1 - Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby - Google Patents
Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby Download PDFInfo
- Publication number
- WO2001059819A1 WO2001059819A1 PCT/US2000/040724 US0040724W WO0159819A1 WO 2001059819 A1 WO2001059819 A1 WO 2001059819A1 US 0040724 W US0040724 W US 0040724W WO 0159819 A1 WO0159819 A1 WO 0159819A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gallium nitride
- growing
- pyramids
- posts
- tops
- Prior art date
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
- H01L21/0265—Pendeoepitaxy
Definitions
- This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
- gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
- a major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable.
- This technique often is referred to as "Epitaxial Lateral Overgrowth" (ELO).
- ELO Epiaxial Lateral Overgrowth
- the layer of gallium nitride may be laterally grown until the gallium nitride coalesces on the mask to form a single layer on the mask.
- a second mask may be formed on the laterally overgrown gallium nitride layer, that includes at least one opening that is offset from the opening in the underlying mask. ELO then again is performed through the openings in the second mask to thereby overgrow a second low defect density continuous gallium nitride layer. Microelectronic devices then may be formed in this second overgrown layer.
- ELO of gallium nitride is described, for example, in the publications entitled Lateral Epitaxy of Low Defect Density GaN Layers Via OrganometalUc Vapor Phase Epitaxy to Nam et al., Appl. Phys. Lett. Vol. 71 , No.
- Lateral growth also preferably continues until the gallium nitride layer that is grown from the sidewalls laterally overgrows onto the tops of the posts.
- the top of the posts and/or the trench floors may be masked.
- Lateral growth from the sidewalls of trenches and/or posts also is referred to as "pendeoepitaxy" and is described, for example, in publications entitled Pendeo-Epitaxy: A New Approach for Lateral Growth of
- the present invention provides a substrate including non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non- gallium nitride sidewalls and non-gallium nitride tops, and the trenches include non- gallium floors. These substrates also may be referred to herein as "textured" substrates.
- gallium nitride is grown on the non-gallium nitride posts, including on the non-gallium nitride tops.
- gallium nitride pyramids are grown on the non-gallium nitride tops and gallium nitride then is grown on the gallium mtride pyramids.
- the gallium nitride pyramids preferably are grown at a first temperature and the gallium nitride preferably is grown on the pyramids at a second temperature that is higher than the first temperature.
- the first temperature preferably is about 1000°C or less and the second temperature preferably is about 1100°C or more.
- the same processing conditions preferably are used for both growth steps.
- the grown gallium nitride on the pyramids preferably coalesces to form a continuous gallium nitride layer.
- gallium nitride pyramids also may be simultaneously grown on the non-gallium mtride floors.
- a conformal gallium nitride layer also may be formed simultaneously on the sidewalls, between the gallium nitride pyramids on the non- gallium nitride tops and on the non-gallium nitride floors.
- the trenches Upon growing the gallium nitride on the pyramids, the trenches also may be simultaneously filled with gallium nitride.
- a conformal buffer layer may be formed on the substrate including on the non-gallium nitride sidewalls, the non-gallium nitride tops and the non-gallium nitride floors, prior to growing the gallium nitride pyramids.
- a conformal layer of aluminum nitride may be used.
- Gallium nitride semiconductor structures therefore may be fabricated, according to the present invention, by providing a textured substrate, including a plurality of non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non-gallium nitride sidewalls and non-gallium nitride tops, and the trenches include non-gallium nitride floors.
- the substrate preferably is free of masking materials on the non-gallium nitride floors and on the non-gallium nitride tops.
- Gallium nitride then is grown at a first temperature and the growth of gallium nitride then is continued at a second temperature that is higher than the first temperature. Growth at the second temperature preferably continues until the gallium nitride forms a continuous gallium nitride layer on the substrate.
- Gallium nitride semiconductor structures preferably comprise a textured substrate including a plurality of non-gallium nitride posts that define trenches therebetween, the non-gallium nitride posts including non- gallium nitride sidewalls and non-gallium nitride tops, and the trenches including non- gallium nitride floors.
- a gallium nitride layer is provided on the non-gallium nitride posts including on the non-gallium nitride tops.
- the gallium nitride semiconductor structure preferably is free of a masking layer on the non-gallium nitride tops and on the non-gallium nitride floors.
- the present invention most preferably may be used to provide methods of fabricating gallium nitride semiconductor structures that need not include masking or interruptions during gallium nitride epitaxial growth. Accordingly, simplified processes for fabricating gallium nitride semiconductor structures may be provided, to thereby fulfill a need in the fledgling gallium nitride semiconductor industry.
- the present invention may be used to fabricate non-gallium nitride semiconductor structures wherein a textured substrate of a first material is provided and a second semiconductor material is grown on the posts including on the tops that comprise the first material.
- semiconductor structures may be provided including a textured substrate that comprises a first material and a layer of second semiconductor material on the posts that comprise the first material.
- Figures 1-6 are cross-sectional views of gallium nitride semiconductor structures during intermediate fabrication steps, according to the present invention.
- a substrate 100 also referred to as a "textured substrate” including a plurality of non-gallium nitride posts 100a that define trenches 100b therebetween.
- the non-gallium nitride posts 100a include non- gallium nitride sidewalls 100c and non-gallium nitride tops lOOd.
- the trenches 100b also include non-gallium nitride floors lOOe.
- the substrate 100 may be a monocrystalline substrate or a substrate including one or more monocrystalline layers thereon, from which the posts 100a and trenches 100b are defined.
- monocrystalline substrates and monocrystalline layers include, but are not limited to, monocrystalline silicon, silicon carbide and or sapphire.
- the posts 100a and trenches 100b may be defined using selective etching and/or selective epitaxial growth. Etching may be performed using standard dry or wet etching techniques, preferably using a mask, which then preferably is removed. The fabrication of a substrate including trenches and posts is well known to those having skill in the art and need not be described in detail herein.
- the trenches 100b preferably are sufficiently deep so that undesirable growth of poor quality gallium nitride from the trench floor lOOe will not interfere with growth of high quality gallium nitride, as will be described below.
- the posts 100a preferably are grown in the form of stripes that preferably are sufficiently narrow, for example less than or equal to one micron in width, so that small gallium nitride seed pyramids can be formed on the non-gallium nitride tops lOOd.
- the initial gallium nitride seed pyramids that form on the non-gallium nitride tops lOOd may have defects, so that the reduced size gallium nitride seed pyramids can reduce the total amount of initial defective gallium nitride seed material.
- the total mechanical stress on the pyramids due to the differences in coefficients of thermal expansion between the substrate, any conformal buffer layers and the grown gallium nitride also may be reduced, as well as the time to complete the pyramidal growth and initiate pendeoepitaxial growth as will be described below.
- the stripes preferably extend along the 1 100 direction of a sapphire or silicon carbide substrate 100 and along the 110 direction of a silicon substrate 100, to thereby expose the 1120 plane of the subsequently grown gallium mtride layer.
- the stripes should expose the 1120 plane of sapphire and silicon carbide substrates.
- the wafer flat is the 0001 direction.
- etching is performed parallel to the flat or the 0001 direction .
- the sidewalls 100c may not be orthogonal to the substrate 100, but rather may be oblique thereto.
- the posts 100a and trenches 100b may define elongated regions that are straight, V-shaped or have other shapes.
- the spaced apart posts 100a also may be referred to as “mesas”, “pedestals” or “columns”.
- the trenches 100b also may be referred to as "wells”.
- an optional conformal buffer layer 102 then may be formed on the substrate 100 including on the non-gallium nitride sidewalls 100c, the non-gallium nitride tops lOOd and the non-gallium nitride floors lOOe.
- the buffer layer may comprise silicon carbide and/or aluminum nitride.
- the buffer layer 102 may comprise high temperature aluminum nitride.
- the conformal buffer layer 102 may comprise low temperature gallium nitride and/or aluminum nitride.
- Other buffer layers may be used with these and other non-gallium nitride posts 100a.
- the fabrication of a buffer layer on a substrate is well known to those having skill in the art and need not be described in detail herein.
- gallium nitride is grown on the non-gallium nitride posts 100a including on the non-gallium nitride tops lOOd. More specifically, a gallium nitride layer 110 is formed, wherein the gallium nitride layer includes gallium nitride pyramids 110a on the non-gallium nitride tops lOOd. These pyramids 110a also may be referred to as "seed forms". It will be understood that the seed forms need not be pyramidal in shape but rather may have flash tops. As also shown in Figure 3, second gallium nitride pyramids 110b also may be formed simultaneously on the non-gallium nitride floors lOOe.
- a conformal region of gallium nitride 110c also may be formed simultaneously on the sidewalls 100c of the non-gallium nitride posts 100a.
- Growth of the gallium nitride layer 110 preferably is performed using metalorganic vapor phase epitaxy (MOVPE) of triethylgallium (TEG), for example at 13-39 ⁇ mol/min andNH 3 at 1500 seem in combination with 3000 seem H 2 diluent, at low temperature, preferably at about 1000°C or less. Additional details of MOCVD growth of gallium nitride may be found in the above-cited publications to Nam et al, Zheleva et al., Zheleva et al. and Linthicum et al. Other growth techniques also may be used.
- gallium nitride layer 110 preferably produces pyramidal gallium nitride seed forms 110a on the tops llOd of the gallium nitride posts 110a.
- One region is a relatively high defect density gallium nitride area that converges at the apex of the pyramid. The other region is nearly defect-free and encapsulates the pyramid. See, for example, the publication by Nam et al.
- the pyramids 110a on the tops lOOd of the non- gallium nitride posts 100a can form these same two regions.
- the growth parameters can be changed to enhance lateral growth of gallium nitride from the relatively defect free regions of the pyramids, and that can result in nearly defect-free gallium nitride epilayers, as will be described below.
- the pyramids preferably are formed at relatively low temperature, preferably about 1000°C or less using metalorganic vapor phase epitaxy, as was described above.
- the pyramids may be grown to have a width of about 2 ⁇ m and a height of about 2 ⁇ m on posts that are 1 ⁇ m wide.
- the interior portions 110a' of the pyramids 110a having a width of about 1 ⁇ m and a height of about 1 ⁇ m may have a high defect density of about 10 cm or more, whereas the outer portions 110a" of the pyramids 110a may be relatively low in defect, for example having defect density of about 10 5 cm "2 or less.
- the conformal layer 110c on the sidewalls 100c of the posts 100 a also may have a high defect density and the second pyramids 110b on the floor lOOe also may have high defect density, for example greater than about 10 cm " . It also will be understood that in Figure 3, masks need not be used prior to or during the growth of the gallium nitride layer 110.
- gallium mtride 120 then is preferentially laterally grown on the gallium mtride pyramids 110a. Moreover, as shown in Figure 4, vertical growth also may occur. It will be understood that, as used herein, the term “lateral” means a direction that is orthogonal to the sidewalls 100c. As used herein, the term “vertical” denotes a direction parallel to the sidewalls 100c.
- the crystal morphology may change as the temperature increases.
- a pyramidal cross-section may result as was shown in Figure 3.
- a rectangular cross- section may result.
- gallium nitride 120 is preferentially laterally grown from the outer portions 110" of the pyramids 110a. Similar to ELO or pendeoepitaxy of gallium nitride, growth from the low defect outer portions 110a" of the pyramids 110a may have a lower density of line and planar defects.
- growth preferably is allowed to continue until the gallium nitride layer 120 coalesces on the tops lOOd of the posts 100a to form a continuous gallium nitride semiconductor layer 130.
- the trenches 100b also preferably are filled with gallium nitride during this growth.
- the III-V precursor ratio also may be changed during metalorganic vapor phase epitaxy to increase lateral growth relative to the vertical growth. It will be understood that the III-V precursor ratio also may be changed during seed form growth, to produce pointed or flat top seed forms. In particular, lateral growth may be enhanced by increasing the ammonia (Group V) flux and/or decreasing the gallium (Group III) flux, such that the overall V/III ratio increases.
- gallium nitride layer 120 coalesces, vertical growth of the continuous gallium nitride layer 130 may be enhanced by decreasing the ammonia flux and/or by increasing the gallium flux, such that the overall VAII ratio decreases.
- the growth of gallium nitride shown in Figures 3-6 need not use a mask Accordingly, a low defect continuous gallium nitride layer 130 may be fabricated without the need to form a mask on a gallium nitride layer. Process simplification thereby may occur.
- the formation of the pyramids 110a and the subsequent formation of the gallium nitride layer 120 may be performed in a single growth chamber, preferably by increasing the temperature and by leaving the other process parameters unchanged. Simplified processing therefore also may be provided.
- low defect density gallium nitride semiconductor layers having defect density of about 10 cm " or less may be grown on substrates including silicon, silicon carbide and/or other materials. Growth masks may be eliminated, and high quality gallium nitride may be formed in one growth run.
- the gallium nitride seed pyramids 110a can confine the threading dislocations that stem from heteroepitaxial growth. Defect densities of less than about 10 5 cm '2 may be obtained within the volume of the laterally grown gallium nitride material.
- the maximum volume of the low defect density gallium nitride layer 130 need only be limited by the size of the substrate.
- gallium nitride structures comprise a substrate 100 including a plurality of non-gallium nitride posts 100a that define trenches 100b therebetween.
- the non-gallium nitride posts 100a include non-gallium nitride sidewalls 100c and non-gallium nitride tops lOOd.
- the trenches include non-gallium nitride floors lOOe.
- a gallium nitride layer 100 is included on the non-gallium nitride posts 100a including on the non-gallium nitride tops lOOd.
- the gallium nitride layer 110 preferably comprises gallium nitride pyramids 110a on the non-gallium nitride tops lOOd.
- Gallium nitride regions 120 may be provided on the gallium nitride pyramids 110a.
- Second gallium nitride pyramids 110b also may be provided on the non-gallium nitride floors lOOe.
- a conformal gallium nitride layer 110c also may be provided on the sidewalls 100c between the gallium nitride pyramids 110a and the second gallium nitride pyramids 110b.
- the gallium nitride regions 120 preferably form a continuous gallium nitride layer 130.
- the gallium nitride layer 110 also preferably fills the trenches.
- a conformal buffer layer 102 also may be provided on the substrate, wherein the gallium nitride layer 110 is on the conformal buffer layer 102 opposite the substrate 100.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001559046A JP4801306B2 (en) | 2000-02-09 | 2000-08-22 | Method for manufacturing gallium nitride semiconductor structure and gallium nitride semiconductor structure |
AU2001218182A AU2001218182A1 (en) | 2000-02-09 | 2000-08-22 | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US50105700A | 2000-02-09 | 2000-02-09 | |
US09/501,057 | 2000-02-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001059819A1 true WO2001059819A1 (en) | 2001-08-16 |
Family
ID=23991977
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/040724 WO2001059819A1 (en) | 2000-02-09 | 2000-08-22 | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby |
Country Status (5)
Country | Link |
---|---|
JP (2) | JP4801306B2 (en) |
KR (1) | KR100865600B1 (en) |
CN (1) | CN1248288C (en) |
AU (1) | AU2001218182A1 (en) |
WO (1) | WO2001059819A1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611002B2 (en) | 2001-02-23 | 2003-08-26 | Nitronex Corporation | Gallium nitride material devices and methods including backside vias |
US6617060B2 (en) | 2000-12-14 | 2003-09-09 | Nitronex Corporation | Gallium nitride materials and methods |
KR100454908B1 (en) * | 2002-02-09 | 2004-11-06 | 엘지전자 주식회사 | Method for manufacturing GaN substrate |
US6956250B2 (en) | 2001-02-23 | 2005-10-18 | Nitronex Corporation | Gallium nitride materials including thermally conductive regions |
US7233028B2 (en) | 2001-02-23 | 2007-06-19 | Nitronex Corporation | Gallium nitride material devices and methods of forming the same |
US7361576B2 (en) | 2005-05-31 | 2008-04-22 | The Regents Of The University Of California | Defect reduction of non-polar and semi-polar III-Nitrides with sidewall lateral epitaxial overgrowth (SLEO) |
US7655090B2 (en) | 2000-08-04 | 2010-02-02 | The Regents Of The University Of California | Method of controlling stress in gallium nitride films deposited on substrates |
US8835902B2 (en) | 2010-12-16 | 2014-09-16 | Samsung Electronics Co., Ltd. | Nano-structured light-emitting devices |
US9209021B2 (en) | 2013-05-31 | 2015-12-08 | Toyoda Gosei Co., Ltd. | Method for producing Group III nitride semiconductor and Group III nitride semiconductor |
US9318326B2 (en) | 2010-04-27 | 2016-04-19 | Pilegrowth Tech S.R.L. | Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication |
US9837494B2 (en) | 2012-03-30 | 2017-12-05 | Toyoda Gosei Co., Ltd. | Production method for group III nitride semiconductor and group III nitride semiconductor |
US10700023B2 (en) | 2016-05-18 | 2020-06-30 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
US11367674B2 (en) | 2016-08-10 | 2022-06-21 | Macom Technology Solutions Holdings, Inc. | High power transistors |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4513446B2 (en) * | 2004-07-23 | 2010-07-28 | 豊田合成株式会社 | Crystal growth method of semiconductor crystal |
CN100365767C (en) * | 2004-09-17 | 2008-01-30 | 同济大学 | Substrate processing method for improving gallium nitride base material epitaxial layer quality |
JP4744245B2 (en) * | 2004-11-05 | 2011-08-10 | シャープ株式会社 | Nitride semiconductor device |
JP4793824B2 (en) * | 2006-08-28 | 2011-10-12 | シャープ株式会社 | Method for forming nitride semiconductor layer |
JP5003719B2 (en) * | 2009-05-07 | 2012-08-15 | 豊田合成株式会社 | Semiconductor device and crystal growth substrate |
JP6485299B2 (en) * | 2015-06-05 | 2019-03-20 | 豊田合成株式会社 | Semiconductor device, method for manufacturing the same, and power conversion device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0884767A2 (en) * | 1997-06-13 | 1998-12-16 | André Strittmatter | Method of epitaxy of gallium nitride on silicon substrates |
WO1999018617A1 (en) * | 1997-10-07 | 1999-04-15 | Cree, Inc. | Group iii nitride photonic devices on silicon carbide substrates with conductive buffer interlayer structure |
WO1999044224A1 (en) * | 1998-02-27 | 1999-09-02 | North Carolina State University | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2569099B2 (en) * | 1987-12-25 | 1997-01-08 | 株式会社日立製作所 | Epitaxial growth method |
JPH05234900A (en) * | 1992-02-19 | 1993-09-10 | Nec Corp | Manufacture of semiconductor device |
JP3930161B2 (en) * | 1997-08-29 | 2007-06-13 | 株式会社東芝 | Nitride-based semiconductor device, light-emitting device, and manufacturing method thereof |
JP4005701B2 (en) * | 1998-06-24 | 2007-11-14 | シャープ株式会社 | Method of forming nitrogen compound semiconductor film and nitrogen compound semiconductor element |
JP4352473B2 (en) * | 1998-06-26 | 2009-10-28 | ソニー株式会社 | Manufacturing method of semiconductor device |
JP2000031068A (en) * | 1998-07-14 | 2000-01-28 | Mitsubishi Cable Ind Ltd | SUBSTRATE FOR GaN CRYSTAL GROWTH |
JP3471685B2 (en) * | 1999-03-17 | 2003-12-02 | 三菱電線工業株式会社 | Semiconductor substrate and manufacturing method thereof |
JP3471700B2 (en) * | 1999-03-17 | 2003-12-02 | 三菱電線工業株式会社 | Semiconductor substrate |
-
2000
- 2000-08-22 CN CNB00818903XA patent/CN1248288C/en not_active Expired - Lifetime
- 2000-08-22 AU AU2001218182A patent/AU2001218182A1/en not_active Abandoned
- 2000-08-22 JP JP2001559046A patent/JP4801306B2/en not_active Expired - Lifetime
- 2000-08-22 WO PCT/US2000/040724 patent/WO2001059819A1/en active Application Filing
- 2000-08-22 KR KR1020027010250A patent/KR100865600B1/en active IP Right Grant
-
2010
- 2010-09-24 JP JP2010213073A patent/JP5323792B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0884767A2 (en) * | 1997-06-13 | 1998-12-16 | André Strittmatter | Method of epitaxy of gallium nitride on silicon substrates |
WO1999018617A1 (en) * | 1997-10-07 | 1999-04-15 | Cree, Inc. | Group iii nitride photonic devices on silicon carbide substrates with conductive buffer interlayer structure |
WO1999044224A1 (en) * | 1998-02-27 | 1999-09-02 | North Carolina State University | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through masks, and gallium nitride semiconductor structures fabricated thereby |
Non-Patent Citations (1)
Title |
---|
ZENG K C ET AL: "OPTICAL PROPERTIES OF GAN PYRAMIDS", APPLIED PHYSICS LETTERS,US,AMERICAN INSTITUTE OF PHYSICS. NEW YORK, vol. 74, no. 9, 1 March 1999 (1999-03-01), pages 1227 - 1229, XP000805887, ISSN: 0003-6951 * |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7816764B2 (en) | 2000-08-04 | 2010-10-19 | The Regents Of The University Of California | Method of controlling stress in gallium nitride films deposited on substrates |
US9691712B2 (en) | 2000-08-04 | 2017-06-27 | The Regents Of The University Of California | Method of controlling stress in group-III nitride films deposited on substrates |
US7655090B2 (en) | 2000-08-04 | 2010-02-02 | The Regents Of The University Of California | Method of controlling stress in gallium nitride films deposited on substrates |
US7687888B2 (en) | 2000-08-04 | 2010-03-30 | The Regents Of The University Of California | Method of controlling stress in gallium nitride films deposited on substrates |
US9129977B2 (en) | 2000-08-04 | 2015-09-08 | The Regents Of The University Of California | Method of controlling stress in group-III nitride films deposited on substrates |
US8525230B2 (en) | 2000-08-04 | 2013-09-03 | The Regents Of The University Of California | Field-effect transistor with compositionally graded nitride layer on a silicaon substrate |
US6617060B2 (en) | 2000-12-14 | 2003-09-09 | Nitronex Corporation | Gallium nitride materials and methods |
US6649287B2 (en) | 2000-12-14 | 2003-11-18 | Nitronex Corporation | Gallium nitride materials and methods |
US8105921B2 (en) | 2000-12-14 | 2012-01-31 | International Rectifier Corporation | Gallium nitride materials and methods |
US6956250B2 (en) | 2001-02-23 | 2005-10-18 | Nitronex Corporation | Gallium nitride materials including thermally conductive regions |
US7233028B2 (en) | 2001-02-23 | 2007-06-19 | Nitronex Corporation | Gallium nitride material devices and methods of forming the same |
US6611002B2 (en) | 2001-02-23 | 2003-08-26 | Nitronex Corporation | Gallium nitride material devices and methods including backside vias |
KR100454908B1 (en) * | 2002-02-09 | 2004-11-06 | 엘지전자 주식회사 | Method for manufacturing GaN substrate |
US7955983B2 (en) | 2005-05-31 | 2011-06-07 | The Regents Of The University Of California | Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO) |
US7361576B2 (en) | 2005-05-31 | 2008-04-22 | The Regents Of The University Of California | Defect reduction of non-polar and semi-polar III-Nitrides with sidewall lateral epitaxial overgrowth (SLEO) |
US9318326B2 (en) | 2010-04-27 | 2016-04-19 | Pilegrowth Tech S.R.L. | Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication |
US8835902B2 (en) | 2010-12-16 | 2014-09-16 | Samsung Electronics Co., Ltd. | Nano-structured light-emitting devices |
US9837494B2 (en) | 2012-03-30 | 2017-12-05 | Toyoda Gosei Co., Ltd. | Production method for group III nitride semiconductor and group III nitride semiconductor |
US9209021B2 (en) | 2013-05-31 | 2015-12-08 | Toyoda Gosei Co., Ltd. | Method for producing Group III nitride semiconductor and Group III nitride semiconductor |
US10700023B2 (en) | 2016-05-18 | 2020-06-30 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
US11367674B2 (en) | 2016-08-10 | 2022-06-21 | Macom Technology Solutions Holdings, Inc. | High power transistors |
US11862536B2 (en) | 2016-08-10 | 2024-01-02 | Macom Technology Solutions Holdings, Inc. | High power transistors |
Also Published As
Publication number | Publication date |
---|---|
JP2003526907A (en) | 2003-09-09 |
KR100865600B1 (en) | 2008-10-27 |
JP4801306B2 (en) | 2011-10-26 |
JP2010283398A (en) | 2010-12-16 |
JP5323792B2 (en) | 2013-10-23 |
CN1248288C (en) | 2006-03-29 |
AU2001218182A1 (en) | 2001-08-20 |
CN1451173A (en) | 2003-10-22 |
KR20020086511A (en) | 2002-11-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6403451B1 (en) | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts | |
JP5323792B2 (en) | Method for manufacturing gallium nitride semiconductor structure, method for manufacturing semiconductor structure, and semiconductor structure | |
US6521514B1 (en) | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates | |
EP1138063B1 (en) | Fabrication of gallium nitride layers by lateral growth | |
JP3886341B2 (en) | Method for manufacturing gallium nitride crystal substrate and gallium nitride crystal substrate | |
US7732306B2 (en) | Methods for producing improved epitaxial materials | |
US6051849A (en) | Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer | |
JP4581490B2 (en) | III-V group nitride semiconductor free-standing substrate manufacturing method and III-V group nitride semiconductor manufacturing method | |
JP4088111B2 (en) | Porous substrate and manufacturing method thereof, GaN-based semiconductor multilayer substrate and manufacturing method thereof | |
US20020031851A1 (en) | Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby | |
US20010039102A1 (en) | Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby | |
US20010009167A1 (en) | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through offset masks | |
JP4356208B2 (en) | Vapor phase growth method of nitride semiconductor | |
KR102062381B1 (en) | Method of growing nitride semiconductor layer and fabrication nitride semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 2001 559046 Kind code of ref document: A Format of ref document f/p: F |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020027010250 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 00818903X Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020027010250 Country of ref document: KR |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
122 | Ep: pct application non-entry in european phase |