WO2001063991A1 - Carte a circuits imprimes multicouche et procede de production d'une carte a circuits imprimes multicouche - Google Patents
Carte a circuits imprimes multicouche et procede de production d'une carte a circuits imprimes multicouche Download PDFInfo
- Publication number
- WO2001063991A1 WO2001063991A1 PCT/JP2001/000177 JP0100177W WO0163991A1 WO 2001063991 A1 WO2001063991 A1 WO 2001063991A1 JP 0100177 W JP0100177 W JP 0100177W WO 0163991 A1 WO0163991 A1 WO 0163991A1
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- layer
- printed wiring
- wiring board
- multilayer printed
- substrate
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board incorporating electronic components such as an IC chip and a method for manufacturing a multilayer printed wiring board.
- the IC chip was electrically connected to the printed wiring board by mounting methods such as wire bonding, TAB, and flip chip.
- an IC chip is die-bonded to a printed wiring board with an adhesive, and the pads of the printed wiring board and the pads of the IC chip are connected by wires such as gold wires, and then the IC chip and the wires are protected.
- a sealing resin such as a thermosetting resin or a thermoplastic resin has been applied.
- connection lead components wires, leads, and bumps
- thermoplastic resin such as epoxy resin to protect the IC chip
- the resin is filled with air bubbles, the air bubbles will be the starting point, This will lead to destruction of lead components, corrosion of IC pads, and reduced reliability.
- thermoplastic resin it is necessary to create a resin loading plunger and mold for each part. Even in the case of resin, it is necessary to select a resin in consideration of materials such as lead components and solder resist, and this has led to higher costs in each case.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer printed wiring board and a multilayer printed wiring that can be directly electrically connected to an IC chip without using a lead component.
- the purpose is to propose a manufacturing method of the board.
- an opening and a through hole are provided on a resin insulating substrate, electronic components such as an IC chip are built in in advance, an interlayer insulating layer is laminated, and a die pad on the IC chip is formed. Then, via holes are formed by photoetching or laser to form a conductive circuit as a conductive layer, and then the interlayer insulating layer and the conductive layer are repeated to form a multilayer printed wiring board, thereby providing a sealing resin.
- a structure was devised in which electrical connection with the IC chip could be established by leadless, without using a chip.
- the present inventor has provided an opening, a through hole, and a zigzag portion on a resin insulating substrate, preliminarily built-in electronic components such as an IC chip, laminated an interlayer insulating layer, and placed a die pad on the IC chip.
- electronic components such as an IC chip, laminated an interlayer insulating layer, and placed a die pad on the IC chip.
- via holes by photoetching or laser to form conductive circuits that are conductive layers
- the interlayer insulating layer and conductive layer are repeated, and IC chips are also used on the surface layer of the multilayer printed wiring board.
- a cache memory is embedded in the built-in IC chip, and an IC chip having an arithmetic function is mounted on the surface layer, thereby manufacturing a low-yield cache memory separately from the IC chip.
- the cache memory can be arranged close to each other.
- the present inventors have provided an opening, a through-hole, or a zully portion in a resin insulating substrate to accommodate electronic components such as an IC chip in advance, and to provide at least a die pad of the IC chip with a die pad.
- transition layer having a two-layer structure.
- An interlayer insulating layer is laminated on the transition layer, and the IC
- a via hole is formed by photo-etching or laser on the via hole, which is the transition layer of the chip, to form a conductive circuit, which is a conductive layer.
- the interlayer insulating layer and the conductive layer are repeated to form a multilayer print.
- electrical connection with the IC chip can be established by re-dressing without using a sealing resin.
- the transition layer is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer is also flattened and the film thickness becomes uniform. Further, the above-described transition layer can maintain the shape stability even when an upper via hole is formed.
- the reason for providing the transition layer on the pad of the IC chip is as follows. First, when the die pad becomes fine and small, it becomes difficult to form a via. Therefore, a transition layer is provided to facilitate the alignment. If a transition layer is provided, a build-up layer can be formed stably even at a die pad pitch of 150 Aim or less and a pad size of 20 // m or less. If the via of the interlayer insulating layer is formed by photoetching with the die pad on which the transition layer is not formed, if the via diameter is larger than the die pad diameter, the via bottom residue is removed and the surface of the interlayer resin insulating layer is roughened. Dissolves and damages the polyimide layer, which is the protective layer on the die pad surface.
- vias can be reliably connected to the die pad even if the die pad pitch becomes 150 ⁇ or less and the pad size becomes 20 ⁇ m or less. To improve the connectivity and reliability with the vias. Furthermore, by interposing a larger diameter transition layer on the pad of the IC chip, it can be immersed in an acid or an etching solution during a post-process such as desmearing or plating, or subjected to various annealing processes. There is no danger of dissolving or damaging the die pad and IC protective film.
- BGAs solder bumps
- PGAs conductive connection pins
- this configuration can shorten the wiring length and reduce the loop inductance as compared with the case of connection by the conventional mounting method.
- transition layer defined in the present invention will be described.
- the transition layer means an intermediate intermediate layer provided for directly connecting the IC chip, which is a semiconductor element, to the printed wiring board without using the conventional IC chip mounting technology.
- it is formed of two or more metal layers. Or, make it larger than the die pad of the IC chip, which is a semiconductor device.
- the electrical connection and alignment are improved, and via holes can be processed by laser or photoetching without damaging the die pad. Therefore, embedding, storing, storing, and connecting the IC chip to the printed wiring board can be ensured.
- Examples of the resin substrate for incorporating electronic components such as IC chips used in the present invention include epoxy resin, BT resin, phenol resin, and the like, a resin in which a reinforcing material such as glass epoxy resin is impregnated with a core material, or an epoxy resin.
- a laminate in which a pre-preda impregnated with a resin is laminated is used, but a laminate generally used for a printed wiring board can be used.
- a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, and a resin film can be used. However, if a temperature of 350 ° C or more is applied, the resin will be dissolved and carbonized. In addition, ceramic cannot be used because of poor formability.
- a cavity for accommodating an electronic component such as an IC chip is formed on a resin insulating substrate such as a core substrate in advance, and the IC chip is joined with an adhesive or the like to the one in which a through hole, an opening, and an opening are formed.
- a conductive metal film (first thin film layer) is formed on the entire surface of the core substrate containing the IC chip by vapor deposition, sputtering, etc.
- the metals are tin, Chromium, titanium, nickel, zinc, cobalt, gold, copper, etc. are good.
- the thickness is preferably between 0.001 and 2.0 // m. If it is less than 0.001 / 1 / m, it cannot be uniformly laminated on the entire surface. It was difficult to form anything exceeding 2.0 ⁇ , and the effect was not enhanced. In particular, 0.0 1 to 1. ⁇ ⁇ is desirable.
- chromium a thickness of 0.1 / xm is desirable.
- the die pad is covered with the first thin film layer, so that the adhesion between the transition layer and the IC chip at the interface between the die pad and the die pad can be improved.
- the first thin film layer can be connected to the IC chip by a lead-free mounting method. This is because the use of chromium, nickel, and titanium prevents moisture from entering the interface and provides excellent metal adhesion.
- the thickness of chromium and titanium should be such that cracks do not occur in the sputtered layer and that the metal adheres to the upper layer.
- a positioning mark is formed on the core substrate with reference to the positioning mark of the IC chip.
- a second thin film layer is formed on the first thin film layer by sputtering, vapor deposition, or electroless plating. Its metals include nickel, copper, gold, and silver. It is preferable to use copper because the electrical characteristics, economy, and the thick layer to be formed later are mainly copper.
- the reason for providing the second thin film layer here is that the first thin film layer cannot take a lead for electrolytic plating for forming a thick layer described later.
- the second thin film layer 36 is used as a thick lead.
- the thickness is preferably in the range of 0.01 to 5 / im. 0. If it is less than O l xm, it cannot play the role of a lead.If it exceeds 5 ⁇ , the lower first thin film layer will be shaved more during etching, leaving gaps, and moisture will easily enter. This is because the reliability decreases.
- the types of metals formed include copper, nickel, gold, silver, zinc, and iron.
- the thickness is preferably in the range of 1 to 20 ⁇ m. If it is thinner than 1 m, the connection reliability with the upper via hole decreases, If the thickness is too large, an undercut occurs at the time of etching, and a gap is generated at the interface between the formed transition layer and the via hole.
- the first thin film layer may be directly attached on the first thin film layer, or may be stacked in multiple layers.
- an etching resist is formed based on the positioning marks on the core substrate, exposed and developed to expose the metal other than the transition layer, and etching is performed.
- the first thin film layer is formed on the die pad of the IC chip.
- a transition layer including a second thin film layer and a thick layer is formed.
- the transition layer is thickened on the metal film by electroless or electrolytic plating.
- the types of plating that are formed include copper, nickel, gold, silver, zinc, and iron. It is preferable to use copper because electrical properties, economy, and a conductor layer that is a build-up formed later is mainly copper.
- the thickness is preferably in the range of 1 to 20; zm. If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via. After that, an etching resist is formed, exposed and developed to expose the metal other than the transition layer, and then etched to form a transition layer on the pad of the IC chip.
- the present inventors accommodate the IC chip in the recess formed in the core substrate, and stack the interlayer resin insulating layer and the conductive circuit on the core substrate, thereby forming the IC chip in the package substrate. It was devised to incorporate.
- a metal film is formed on the entire surface of the core substrate in which the IC chip is housed, thereby covering or protecting the pads of the IC chip, which is an electronic component.
- a transition is formed on the pad. The formation of the layer establishes an electrical connection between the pad and the via hole in the interlayer resin insulation layer.
- the metal film is applied to the entire surface, so that the positioning mark formed on the IC chip is hidden, so that the substrate cannot be aligned with a mask or a laser device on which wiring is drawn. As a result, a positional shift between the pad of the IC chip and the via hole may occur, and electrical connection may not be established. As expected.
- the present invention has been made in order to solve the above-described problems, and an object of the present invention is to propose a method of manufacturing a multilayer printed wiring board that can appropriately connect to an integrated IC chip.
- the purpose is to do.
- a method for manufacturing a multilayer printed wiring board comprising: at least the following steps (a) to (c):
- a positioning mark is formed on a substrate containing the electronic component based on the positioning mark of the electronic component, and processing or forming is performed based on the positioning mark of the substrate. For this reason, via holes can be formed in the interlayer resin insulating layer on the substrate so that the positions are accurately aligned with the electronic components.
- the processing in this case means all the components formed on the IC chip or the substrate as the electronic component.
- a transition layer on an IC chip pad for example, recognition characters (alphabet, numbers, etc.), positioning marks, and the like.
- the formation in this case means everything that is formed on the interlayer resin insulating layer (which does not include a reinforcing material such as glass cloth) provided on the core substrate. For example, via holes, wiring, recognition characters (alphabet, numbers, etc.), positioning marks, etc.
- a method for producing a multilayer printed wiring board comprising the following steps (a) to (d):
- a positioning mark is drilled with a laser on a substrate that houses the electronic component, and a metal film is formed on the positioning mark drilled with the laser, and then the positioning mark of the substrate is formed. Processing or forming is performed based on the results. For this reason, a via hole can be formed in the interlayer resin insulation layer on the substrate so that the position is accurately matched with the electronic component.
- the metal film is formed on the positioning mark formed by the laser, the positioning mark can be easily recognized by the reflection type, and accurate positioning can be performed.
- a method for producing a multilayer printed wiring board comprising: at least the following steps (a) to (e):
- a positioning mark is formed on a substrate containing the electronic component based on the positioning mark of the electronic component, a metal film is formed on the positioning mark, and then processing or formation is performed based on the positioning mark on the substrate. For this reason, via holes can be formed in the interlayer insulating layer on the substrate so that the positions are accurately aligned with the electronic components.
- the metal film is also formed on the positioning mark drilled by the laser, even if an interlayer insulating layer is formed on the positioning mark, if the image recognition is performed by the reflection method, the positioning mark can be easily recognized. Can be positioned accurately.
- the present inventor has provided an opening and a through hole counterbored portion on a resin insulating substrate.
- an electronic component such as an IC chip was previously built in, an interlayer insulating layer was laminated, and a via was provided on the pad of the IC chip by photoetching or laser to form a conductive circuit as a conductive layer.
- a via was provided on the pad of the IC chip by photoetching or laser to form a conductive circuit as a conductive layer.
- the pads of the IC chip are generally made of aluminum or the like, and are oxidized in the manufacturing process, and an oxide film is formed on the surface. For this reason, it was found that the connection resistance of the pad was increased by the oxide film formed on the surface, and it was not possible to obtain an appropriate electrical connection to the IC chip. Also, it was found that if an oxide film remained on the die pad, the adhesion between the pad and the transition layer was insufficient, and reliability could not be satisfied.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multi-layer printed wiring board and a multi-layer printed circuit that can appropriately and electrically connect to an IC chip in a leadless manner.
- the purpose is to propose a method for manufacturing wiring boards.
- the method for producing a multilayer printed wiring board according to claim 17 is characterized by including at least the following steps (a) to (e): Receiving parts;
- the IC chip since the IC chip is accommodated in the substrate, it is possible to establish electrical connection with the IC chip in a leadless manner. Furthermore, since the oxide film is removed on the connection surface of the die pad of electronic components such as IC chips, the electrical resistance of the die pad can be reduced and the conductivity can be increased. In addition, by providing a transition layer on the IC chip portion, the IC chip portion is flattened. The interlayer insulating layer is also flattened, and the film thickness becomes uniform. In addition, shape stability can be maintained when forming the upper via hole. It is desirable to remove the film completely.
- the conductivity of the die pad of the IC chip can be increased by completely removing the oxide film by either reverse sputtering or plasma treatment.
- an oxide gas on the die pad surface is reverse-sputtered by using an inert gas such as argon as a sputtering gas to completely remove the oxide film.
- an inert gas such as argon
- the substrate is placed in a vacuum apparatus, and plasma is released in oxygen, nitrogen, carbon dioxide, or carbon tetrafluoride to remove the oxide film on the die pad surface.
- a transition layer for connecting to a via hole of a lowermost interlayer insulating layer is formed,
- a technical feature is that the coating on the surface of the die pad is removed. According to claim 20, since the IC chip is accommodated in the substrate, electrical connection with the IC chip can be established with a leadless. Furthermore, since the oxide film is removed on the connection surface of the die pad of electronic components such as IC chips, the electrical resistance of the die pad can be reduced and the conductivity can be increased. Also, by providing the transition layer in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer is also flattened and the film thickness is uniform. In addition, shape stability can be maintained when forming the upper via hole. The film should be completely removed. BRIEF DESCRIPTION OF THE FIGURES
- FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to a first embodiment of the present invention.
- FIG. 2 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment.
- FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment.
- FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment.
- FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment.
- FIG. 6 is a sectional view of the multilayer printed wiring board according to the first embodiment.
- FIG. 7 (A) is an enlarged view of the transition layer in FIG. 3 (A), (B) is a view on arrow B in FIG. 7 (A), (C), (D) and (E) are explanatory diagrams of modified examples of the transition layer.
- FIG. 8 (A) is a perspective view of the multilayer printed wiring board according to the first embodiment, and (B) is an enlarged view illustrating a part of the multilayer printed wiring board.
- FIG. 9A is a perspective view of a multilayer printed wiring board according to a first modification of the first embodiment, and FIG. 9B is an enlarged view showing a part of the multilayer printed wiring board.
- FIG. 10 is a cross-sectional view of a multilayer printed wiring board according to a second modification of the first embodiment.
- FIG. 11 is a sectional view of a multilayer printed wiring board according to a third modification of the first embodiment.
- FIG. 12 is a sectional view of a multilayer printed wiring board according to a fourth modification of the first embodiment.
- FIG. 13 is a manufacturing process diagram of the multilayer printed wiring board according to the second embodiment.
- FIG. 14 is a manufacturing process diagram of the multilayer printed wiring board according to the second embodiment.
- FIG. 15 is a manufacturing process diagram of the multilayer printed wiring board according to the second embodiment.
- FIG. 16 is a manufacturing process diagram of the multilayer printed wiring board according to the second embodiment.
- FIG. 17 is a manufacturing process diagram of the multilayer printed wiring board according to the second embodiment.
- FIG. 18 is a cross-sectional view of the multilayer printed wiring board according to the second embodiment.
- FIG. 19 (A) is a plan view of the core substrate in FIG. 13 (D), and (B) Is a plan view of FIG. 13 (E).
- FIG. 20 (A) is a plan view of the core substrate before the photomask film is mounted, and (B) is a plan view of the core substrate in the state where the photomask film is mounted.
- FIG. 21 is a cross-sectional view of a multilayer printed wiring board according to a first modification of the second embodiment.
- FIG. 22 is a manufacturing process diagram of the multilayer printed wiring board according to the third embodiment.
- FIG. 23 is a manufacturing process diagram of the multilayer printed wiring board according to the third embodiment.
- FIG. 24 is a manufacturing process diagram of the multilayer printed wiring board according to the third embodiment.
- FIG. 25 is a manufacturing process diagram of the multilayer printed wiring board according to the third embodiment.
- FIG. 26 is a cross-sectional view of the multilayer printed wiring board according to the third embodiment.
- (A) is an explanatory view showing the die pad portion in FIG. 22 (C) in an enlarged manner
- (B) is an enlarged view of the die pad portion in FIG. 23 (A).
- (C) is an explanatory view showing an enlarged die pad portion in FIG. 24 (A).
- FIG. 28 is a cross-sectional view of a multilayer printed wiring board according to a first modification of the third embodiment.
- FIG. 29 is an enlarged view of a die pad portion according to a first modification of the third embodiment, wherein (A) is a view showing a state before an oxide film removal treatment, and (B) is a view showing FIG. 3C is a view showing a state after an oxide film removing process, and FIG. 4C is a view showing a state after a transition layer is formed on a die pad.
- FIG. 30 shows the multilayer printed wiring boards of the third embodiment and the comparative example in four items: 1) cross-sectional state, 2) measured resistance value, 3) cross-sectional state after reliability test, and 4) measured resistance value.
- 9 is a table showing the results of evaluations performed on the above.
- the multilayer printed wiring board 10 includes a core substrate 30 for accommodating an IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via holes 60 and conductor circuits 58 are formed in the interlayer resin insulation layer 50, and via holes 160 and conductor circuits 158 are formed in the interlayer resin insulation layer 150.
- the IC chip 20 is covered with a passivation film 24, and a die pad 24 constituting an input / output terminal is provided in an opening of the passivation film 24.
- a transition layer 38 is formed on the aluminum die pad 24.
- the transition layer 38 has a three-layer structure of a first thin film layer 33, a second thin film layer 36, and a thick film 37.
- a solder resist layer 70 is provided on interlayer resin insulating layer 150.
- the conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a BGA 76 for connection to an external substrate (not shown) such as a data board or a mother board.
- an IC chip 20 is built in the core substrate 30 in advance, and a transition layer 38 is provided on the die pad 24 of the IC chip 20. I have. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be obtained without using lead components or sealing resin.
- the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened, and the thickness of the S layer becomes uniform. . Further, the transition layer can maintain the shape stability even when the upper via hole 60 is formed.
- a copper transition layer 38 on the die pad 24 resin residue on the die pad 24 can be prevented, and it can be immersed in an acid, an oxidizing agent, or an etching solution during a later process. Also, discoloration and dissolution of the die pad 24 do not occur even after various annealing processes. This improves the connectivity and reliability between the die pad of the IC chip and the via hole. Further, by interposing a transition layer 38 having a diameter of 60 tm or more on the die pad 24 having a diameter of about 40 ⁇ , a via hole having a diameter of 60 ⁇ m can be reliably connected.
- a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterbore processing (see FIG. 1 (B)).
- the concave portion is formed by zigzag processing.
- a core substrate having an accommodating portion can be formed by bonding an insulating resin substrate having an opening and a resin insulating substrate having no opening.
- the adhesive material 34 is applied to the concave portion 32 using a printing machine. At this time, potting may be performed in addition to coating. Next, the IC chip 20 is placed on the adhesive material 34 (see FIG. 1 (C)).
- (A) As the metal, tin, chromium, titanium, nickel, zinc, cobanoleto, gold, and copper are good.
- the use of nickel, chromium, or titanium can suppress moisture penetration at the force interface, and is suitable for film formation and electrical characteristics.
- the thickness is preferably between 0.01 and 2.0 / X m, and more preferably between 0.01 and 1.0 m.
- chromium a thickness of 0.1 lm is desirable.
- the die pad 24 is covered by the first thin film layer 33, so that the adhesion between the transition layer and the IC chip at the interface with the die pad 24 can be increased.
- the first thin film layer 33 allows connection with the IC chip by a lead-free mounting method.
- the use of chromium, titanium, and nickel can prevent moisture from entering the interface and have high metal adhesion.
- a second thin film layer 36 is formed on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 2 (B)).
- the metals are nickel, copper, There are gold and silver. It is preferable to use copper because the electrical characteristics, the economics, and the conductor layer, which is a build-up formed later, are mainly copper.
- the reason for providing the second thin film layer is that the first thin film layer cannot take a lead for electrolytic plating for forming a thick layer described later.
- the second thin film layer 36 is used as a thick lead. Its thickness should be in the range of 0.01 to 5 ⁇ . In particular, it is preferably between 0.1 and 3 m, which is most suitable for covering and leading the first thin film layer. If it is less than 0.01 ⁇ m, it cannot serve as a lead, and if it exceeds 5 m, the lower first thin film layer will be more shaved off during etching, creating a gap, making it easier for moisture to enter. This is because reliability decreases. Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.
- a resist is applied, exposed and developed, and a plating resist 35 is provided so as to provide an opening above the die pad of the IC chip.
- Electrolytic plating is performed under the following conditions, and the electrolytic plated film (thickness) is formed. (Film) 37 is provided (Fig. 2 (C)).
- the electroless second thin film layer 36 and the first thin film layer 33 under the plating resist 35 are removed by etching to form a transition layer 38 on the die pad 24 of the IC chip.
- the transition layer is formed by a plating resist, but after an electrolytic plating film is uniformly formed on the electroless second thin film layer 36, an etching resist is formed to expose the film. It is also possible to form a transition layer on the die pad of the IC chip by performing light and development to expose the metal other than the transition layer and to perform etching.
- the thickness of the electrolytic plating film is preferably in the range of 1 to 20 / xn. If the thickness is larger than that, an undercut occurs during etching, and a gap may be generated at the interface between the formed transition layer and the via hole.
- FIG. 7 (A) is an enlarged view of the transition layer 38 in FIG. 3 (A)
- FIG. 7 (B) is a view taken in the direction of arrow B in FIG. 7 (A).
- the transition layer 38 has a three-layer structure of a first thin film layer 33, a second thin film layer 36, and a thick film 37. As shown in Fig. 7 (A), the transition is formed in a circular shape. Instead, the transition is made into an elliptical shape as shown in Fig. 7 (C), and as shown in Fig. 7 (D). It is also possible to form a rectangle and an oval shape as shown in Fig. 7 (E).
- thermosetting resin sheet having a thickness of 50 mu m by vacuum crimp lamination at a pressure 5KgZcm 2 while raising the temperature to a temperature 50 to 1 50 ° C, the interlayer ⁇ fat insulating layer 50 (See Fig. 3 (B)).
- the degree of vacuum during vacuum compression is 10 mmHg.
- a via hole opening 48 having a diameter of 80 m is provided in the interlayer resin insulation layer 50 (see FIG. 3 (C)).
- Use chromic acid to remove the resin residue in opening 48 By providing the copper transition layer 38 on the die pad 24, resin residue on the die pad 24 can be prevented, thereby improving the connectivity and reliability between the die pad 24 and via holes 60 described later.
- the via hole opening 48 having a diameter of 60 ⁇ m can be reliably connected.
- the resin residue is removed using permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma.
- a roughened surface 50 ⁇ of the interlayer resin insulating layer 50 is provided (see FIG. 3 (D)).
- the roughened surface 50 ⁇ is preferably formed in the range of 0.05 to 5.
- 50 gZ 1 of sodium permanganate solution is immersed in a temperature of 60 ° C. for 5 to 25 minutes to provide 1 to 5 ⁇ rough surface.
- a roughened surface 50 ⁇ can be formed on the surface of the interlayer resin insulating layer 50 by performing plasma processing using SV-4540 manufactured by Japan Vacuum Engineering Co., Ltd. At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 20 OW, gas pressure 0.6 Pa, and temperature 70 ° C.
- a metal layer 52 is provided on the interlayer resin insulation layer 50 on which the rough surface 50 is formed (see FIG. 4 (A)).
- the metal layer 52 is formed by electroless plating.
- a metal layer which is a plating film in the range of 0.1 to 5 / m is obtained by applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 50 in advance and immersing it in the electroless plating solution for 5 to 60 minutes. 52 will be provided.
- a catalyst such as palladium
- sputtering using Ni and Cu as targets was performed at a pressure of 0.6 Pa, a temperature of 80 ° C, a power of 200 W, and an hour. This is performed under the condition of 5 minutes, so that the Ni / Cu metal layer 52 can be formed on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the formed NiZCu metal layer 52 is 0.2 ⁇ .
- a metal film can be formed by vapor deposition, electrodeposition, or the like.
- electroless plating after forming a thin layer by a physical method such as sputtering, vapor deposition, or electrodeposition.
- a physical method such as sputtering, vapor deposition, or electrodeposition.
- Paste A commercially available photosensitive dry film, and ⁇ chromium glass mask was exposed at 4 Om jZcm 2, developed with 0.8% carbonate Natoriumu
- a plating resist 54 having a thickness of 25 m is provided.
- electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 18 zm (see FIG. 4 (B)).
- the additive in the aqueous solution for electroplating is Capparaside HL manufactured by Atotech Japan.
- the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide.
- a conductor circuit 58 having a thickness of 16 zm and a via hole 60 comprising a metal layer 52 and an electrolytic plating film 56 are formed, and a rough surface 58 is formed by an etching solution containing a cupric complex and an organic acid. 60 strands are formed (see Fig. 4 (C)).
- a roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
- Michler's ketone (manufactured by Kanto Chemical Co., Ltd.) is added in an amount of 0.2 part by weight to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa * s at 25 ° C.
- the viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) using rotor No. 4 at 60 rpm and rotor No. 3 at 6 rpm.
- solder resist composition is applied to the substrate 30 at a thickness of 20 xm, and dried at 70 for 20 minutes and at 70 for 30 minutes.
- the pattern is brought into close contact with a photomask having a thickness of 5mm, which is drawn on the solder resist layer 70 is exposed by one of 000m jZcm 2 UV and developed with DMTG solution, land diameter 620 111, the opening diameter 460 m openings 71 (See Fig. 5 (B)).
- a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form the BGA 76.
- a multilayer printed wiring board 10 having a built-in IC chip 20 and a BGA 76 can be obtained (see FIG. 6).
- a PGA conductive connection pin
- thermosetting resin sheet is used for the interlayer resin insulating layers 50 and 150.
- This thermosetting resin sheet contains a sparingly soluble resin, soluble green particles, a curing agent, and other components. Each is described below.
- the epoxy resin that can be used in the thermosetting resin sheet of the first embodiment is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a hardly soluble resin). ).
- the terms “sparingly soluble” and “soluble” used in the first embodiment refer to those having a relatively fast dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time. For convenience, it is called “soluble”, and those with a relatively slow dissolution rate are called “poorly soluble” for convenience.
- soluble particles examples include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent.
- soluble resin particles resin particles soluble in an acid or an oxidizing agent
- soluble inorganic particles inorganic particles soluble in an acid or an oxidizing agent
- metal particles soluble in the agent hereinafter referred to as “soluble metal particles”
- the shape of the soluble particles is not particularly limited, and examples thereof include a spherical shape and a crushed shape. Further, the shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.
- the average particle size of the soluble particles is desirably 0.1 to 10 ⁇ m. As long as the particle diameter is within the above range, two or more kinds of particles having different particle diameters may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 ⁇ and soluble particles having an average particle size of 1 to 3 ⁇ . As a result, a more complicated roughened surface can be formed, and the adhesion to the conductor circuit is excellent.
- the particle size of the soluble particles is the length of the longest portion of the soluble particles.
- the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When the soluble resin particles are immersed in a solution containing an acid or an oxidizing agent, they have a higher dissolution rate than the hardly soluble resin. It is not particularly limited. Specific examples of the soluble resin particles include, for example, those composed of an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluororesin, and the like. Or a mixture of two or more resins.
- resin particles made of rubber can be used as the soluble resin particles.
- the above rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, polyurethane-modified, (meth) atalonitrile-modified, and (meth) acrylonitrile.butadiene rubber containing a carboxyl group. .
- the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used.
- Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
- Examples of the aluminum compound include alumina, aluminum hydroxide, and the like.
- Examples of the calcium compound include calcium carbonate and calcium hydroxide.
- Examples of the force rim compound include carbon dioxide lime.
- Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
- soluble metal particles examples include particles made of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. In addition, these soluble metal particles may be used even if the surface layer is covered with a resin or the like in order to secure insulation. Good.
- the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted with the poorly soluble resin, and cracks occur in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulating layer and the conductor circuit.
- the hardly soluble resin is not particularly limited as long as it can retain the shape of the rough surface when forming the rough surface using an acid or an oxidizing agent in the interlayer resin insulating layer, for example, examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Also, photosensitive resins obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in the interlayer resin insulating layer by using exposure and development processes.
- thermosetting resin those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.
- the hardly soluble resin examples include, for example, an epoxy resin, a phenol resin, a phenoxy resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Thermosetting resins, thermoplastic resins, and composites thereof may be used.
- an epoxy resin having two or more epoxy groups in one molecule is more preferable.
- it is also excellent in heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and the metal layer peels off. Because it is difficult.
- epoxy resin for example, cresono lenovolac epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol monovolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, Naphthalene-type epoxy resin, dicyclopentene-type epoxy resin, phenols and fragrance having phenolic hydroxyl group Epoxides of condensates with group aldehydes, tridalidyl isocyanurate, alicyclic epoxy resins and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.
- the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It can form a rough surface with unevenness of uniform roughness.Even if a via hole or through hole is formed in the resin film, the adhesion of the metal layer of the conductor circuit formed on it can be ensured. Because it can be. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. As a result, the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, so that the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.
- the amount of the soluble particles dispersed in the poorly soluble resin is desirably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, a soluble surface using an acid or an oxidizing agent may be used. When the raw particles are dissolved, they may be dissolved to the deep part of the resin film, and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film may not be maintained, which may cause a short circuit.
- the resin film desirably contains a curing agent, other components, and the like in addition to the soluble particles and the poorly soluble resin.
- the curing agent examples include an imidazole-based curing agent, an amine-based curing agent, a guanidine-based curing agent, an epoxy product of these curing agents, those obtained by subjecting these curing agents to microcapsenolay, and triphenylenolephosphine.
- organic phosphine compounds such as tetraphenylinolephosphonium and tetraphenylborate.
- the content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. If the content is less than 0.05% by weight, the resin film is insufficiently cured, so that the degree of penetration of acid or oxidizing agent into the resin film increases, and the insulation of the resin film may be impaired. Meanwhile, 10 weight. If the ratio exceeds / 0 , an excessive amount of the curing agent component may modify the resin composition, leading to a reduction in reliability. Sometimes.
- Examples of the other components include a filler such as an inorganic compound or a resin which does not affect the formation of the roughened surface.
- examples of the inorganic compound include silica, alumina, and dolomite.
- examples of the resin include polyamide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin. And the like.
- the resin film may contain a solvent.
- the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, ethinole acetate acetate, butyl acetate, aromatic hydrocarbons such as cellosolve acetate, toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.
- the resin film After attaching the resin film, the resin film is opened by a laser to open a via hole in the interlayer resin insulating layer. Then, it is immersed in an acid or an oxidizing agent to form a roughened layer on the interlayer resin insulating layer.
- an acid a strong acid such as sulfuric acid, phosphoric acid, hydrochloric acid, or formic acid can be used.
- the oxidizing agent chromic acid, chromic sulfuric acid, permanganate hydrochloride, or the like can be used.
- the roughened layer is formed on the surface of the interlayer resin insulating layer by dissolving or dropping the soluble particles.
- electroless plating is performed.
- a resist is applied on the electroless plating film to form a non-formed portion of the plating resist through exposure and development.
- the non-formed portion was subjected to electrolytic plating, the resist was stripped, and the electroless plated film on the interlayer resin insulating layer was removed by etching to form via holes and conductive circuits.
- FIG. 8 (A) is a perspective view of the multilayer printed wiring board 10 according to the first embodiment
- FIG. 8 (B) is an enlarged view of a part of the multilayer printed wiring board 10.
- solder bumps (boulder array) 76 are arranged on the entire surface of the substrate in a staggered lattice pattern.
- the BGA 76 is also formed on the IC chip 20 so that the IC chip The wiring length from 20 can be shortened.
- FIG. 9 (A) is a perspective view of a multilayer printed wiring board 10 according to a first modification of the first embodiment
- FIG. 9 (B) shows a part of the multilayer printed wiring board 10.
- FIG. 8 On the surface of the multilayer printed wiring board 10 of the modified example, solder bumps (ball grid arrays) 76 are arranged at four corners except on the IC chip 20 in a staggered pattern.
- solder bumps (ball grid arrays) 76 are arranged at four corners except on the IC chip 20 in a staggered pattern.
- the BGA 76 is less susceptible to thermal and electromagnetic effects from the IC chip by avoiding the area above the IC chip 20.
- the second modification is almost the same as the first embodiment, but is configured in a PGA system in which connection is established via conductive connection pins 96 as shown in FIG.
- the IC chip is accommodated in the concave portion 32 provided with the counterbore in the core substrate 30.
- the IC chip 20 is accommodated in the through hole 32 formed in the core substrate 30.
- the heat sink can be directly attached to the back surface of the IC chip 20, there is an advantage that the IC chip 20 can be cooled efficiently.
- the IC chip is accommodated in the multilayer printed wiring board.
- the IC chip 20 is housed in the multilayer printed wiring board, and the IC chip 120 is mounted on the surface.
- a cache memory that generates a relatively small amount of heat is used, and as the IC chip 120 on the surface, a CPU for calculation is arranged.
- the die pad 24 of the IC chip 20 and the die pad 124 of the IC chip 120 are composed of a transition layer 38—via hole 60—conductor circuit 58—via hole 160—conductor circuit 158—BGA Connected via 7 6 U.
- the die pad 1 24 of the IC chip 120 and the pad 92 of the data board 90 are BGA 76 U—conductor circuit 1 58 1 via hole 160 0—conductor circuit 58 8 via Honore 6 0—Through hole 1 3 6—Via hole 6 0—Conductor circuit 5 8 1 Via hole 1 6 0—Conductor circuit 1 5 8—Connected via BGA 76 U.
- the IC chip 120 and the cache memory 20 close while manufacturing the cache memory 20 with a low yield separately from the IC chip 120 for the CPU.
- high-speed operation of the IC chip becomes possible.
- this fourth modified example by mounting an IC chip and mounting it on the surface, electronic components such as IC chips having different functions can be mounted, and a more sophisticated multilayer printed wiring board can be mounted. Obtainable.
- connection between the IC chip and the printed wiring board can be established without the intervention of a lead component. Therefore, resin sealing is not required. In addition, since there is no problem caused by the lead components or the sealing resin, the connectivity and reliability are improved. In addition, since the die pad of the IC chip is directly connected to the conductive layer of the printed wiring board, the electrical characteristics can be improved.
- the wiring length from the IC chip to the substrate to the external substrate can be shortened, and there is an effect that the loop inductance can be reduced.
- FIG. 18 showing a cross section of the multilayer printed wiring board 210.
- the multilayer printed wiring board 210 is composed of a core board 230 containing an IC chip 220, an interlayer resin insulation layer 250, and an interlayer resin insulation layer 350. Become. Via holes 260 and conductor circuits 258 are formed in interlayer resin insulation layer 250, and via holes 360 and conductor circuits 358 are formed in interlayer resin insulation layer 350. .
- the IC chip 222 is covered with a passivation film 222, A die pad 224 constituting an input / output terminal and a positioning mark 223 are provided in the opening of the partition film 224. On the pad 224, a transition layer 238 mainly made of copper is formed.
- solder resist layer 270 On the interlayer resin insulation layer 350, a solder resist layer 270 is provided. BGA 276 for connection to an external substrate (not shown) such as a daughter board or a mother board is provided in the conductor circuit 358 below the opening 2 71 of the solder resist layer 270.
- an IC chip 220 is built in the core board 230 in advance, and a transition layer is formed in the pad 222 of the IC chip 220. 3 8 are arranged. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be achieved without using lead components or a sealing resin.
- a positioning mark 2 31 is formed on the core substrate 230 with reference to the positioning mark 2 23 of the IC chip 220, and a via hole 260 is aligned with the positioning mark 2 31.
- the via hole 260 is accurately positioned on the pad 222 of the IC chip 220, and the pad 222 and the via hole 260 can be reliably connected.
- an insulating resin substrate (co-substrate) 230 in which a prepreg obtained by impregnating a resin such as epoxy with a core material such as glass cloth is used as a starting material (see FIG. 13 (A)).
- a concave portion 232 for accommodating an IC chip is formed on one surface of the core substrate 230 by zigzag processing (see FIG. 13B).
- FIG. 19 (A) is a plan view of the IC chip 220 and the core substrate 230 shown in FIG. 13 (D).
- the IC chip 220 accommodated in the concave portion 232 of the core substrate 230 cannot be accurately positioned with respect to the core substrate due to the processing accuracy of the concave portion and the interposition of the adhesive material 234.
- FIG. 13 (E) A plan view of the IC chip 220 and the core substrate 230 shown in FIG. 13 (E) is shown in FIG. 19 (B).
- a conductive metal film 233 on the entire surface (FIG. 14 (A) ).
- the metal at least one kind of metal such as tin, chromium, titanium, nickel, zinc, konole, gold, and copper is formed. In some cases, different metals may be formed in two or more layers.
- the thickness is preferably between 0.001 and 2.0 ⁇ m. In particular, it is preferably 0.01 to 1.0 ⁇ m.
- a plating film 236 may be formed on the metal film 233 by electroless plating, electrolytic plating, or a combination thereof (FIG. 14 (B)).
- the types of plating that can be formed include copper, nickel, gold, silver, zinc, and iron. It is preferable to use copper because the conductor layer, which is a build-up layer formed later, is mainly made of copper.
- the thickness should be in the range of 0.01 to 5. If it is less than 0.01 / xm, a plating film cannot be formed on the entire surface. A desirable range is from 0.1 to 3. O / zm. It can also be formed by sputtering or vapor deposition.
- a resist 235 ⁇ is applied, and a mask 239 on which a pattern 239a and a positioning mark 239b corresponding to the node 224 are drawn is placed (FIG. 14 (C)).
- the positioning of this mask 235 Light is irradiated from above so that the positioning mark through hole 231a of the core substrate 230 enters the mark 239b, and the reflected light from the positioning mark 231 is imaged by the camera 289.
- the copper plating film 236 is also formed on the positioning mark 231, the reflected light easily passes through the resist 235 ⁇ , and the alignment between the substrate and the mask can be easily performed.
- Exposure and development are performed to form a plating resist 235 so as to provide an opening above the pad 224 of the IC chip, and electrolytic plating is performed to form an electrolytic plating film 237 (FIG. 14 (D)).
- electrolytic plating is performed to form an electrolytic plating film 237 (FIG. 14 (D)).
- the electroless plating film 236 and the metal film 233 under the resist resist 235 are removed to form a transition layer 238 on the IC chip pad 224 and a recess 231a.
- the positioning mark 231 is formed (FIG. 14 (E)).
- a roughened surface 238 is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 238 (FIG. 15).
- a roughened surface can also be formed using electroless plating or redox treatment.
- thermosetting resin sheet as that of the first embodiment is vacuum-press-laminated on the substrate having undergone the above steps, and an interlayer resin insulating layer 250 is provided (see FIG. 15 (B)).
- the alignment is performed by transmitting an image of the positioning mark 231 by the camera 280 through the interlayer resin insulation layer 250 and using a CO 2 gas laser having a wavelength of 10.4 / xm to obtain a beam diameter of 5 mm.
- a pulse width of 5.0 ⁇ s a mask hole diameter of 0.5 mm, and one shot, an opening 248 for a via hole with a diameter of 80 ⁇ m is provided in the interlayer resin insulation layer 250 (Fig. 15 (C ))).
- FIG. 20 (A) is a plan view of the core substrate 230 before the photomask film 253 is mounted, and FIG. Fig. 20 (B) shows a state where the Ilum 253 is placed.
- the position of the mask 253 is determined by irradiating light from above so that the positioning mark 231 of the core substrate 230 enters the positioning mark 253 b drawn in a ring shape. This is performed while imaging the reflected light.
- the plating film 237 is formed on the positioning mark 231, the reflected light easily passes through the interlayer resin insulating layer 250 and the film 254 ⁇ , and positioning can be performed accurately.
- the copper plating film 237 constituting the positioning mark 231 was roughened as described above, this roughening process may not be performed, or the roughening process may be performed in order to increase the surface reflectance. After the surface treatment, the surface can be smoothed with a chemical, a laser, or the like.
- electrolytic plating is performed under the same conditions as in the first embodiment to form an electrolytic plating film 256 having a thickness of 15 ⁇ m (see FIG. 16 (D)).
- the metal layer 252 under the plating resist is dissolved and removed by etching, and a 16 ⁇ thick metal layer 252 and an electrolytic plating film 256 are formed.
- the conductor circuit 258 and the via hole 260 are formed, and the roughened surfaces 258 ⁇ and 260 ⁇ are formed by the etching solution (see FIG. 17 ( ⁇ )).
- solder resist composition as in the first embodiment is applied to the substrate 230 at a thickness of 20 ⁇ , and after drying, a photomask is brought into close contact with the solder resist layer 270 and exposed. Then, it is developed with a DMTG solution to form an opening 271 having a diameter of 200 ⁇ (see FIG. 17 (C)).
- the substrate on which the solder resist layer (organic resin insulating layer) 270 is formed is immersed in an electroless nickel plating solution to form a nickel plating layer 272 having a thickness of 5 ⁇ in the opening 271. Furthermore, the substrate is immersed in an electroless plating solution, By forming a plating layer 274 having a thickness of 0.03 / xm on the nickel plating layer 272, a solder pad 275 is formed on the conductor circuit 358 (Fig. 17 ( D)). (20) Thereafter, a solder paste is printed on the opening 271 of the solder resist layer 270 and reflowed at 200 ° C. to form a BGA 276. This makes it possible to obtain a multilayer printed wiring board 210 having a BGA 276 with a built-in IC chip 220 (see FIG. 18). In exchange for 80 eight? ⁇
- the IC chip is accommodated in the multilayer printed wiring board.
- the IC chip 220 is accommodated in the multilayer printed wiring board, and the IC chip 320 is mounted on the surface.
- a cache memory that generates a relatively small amount of heat is used as the built-in IC chip 220, and a CPU for calculation is mounted as the IC chip 320 on the front surface.
- the through holes 3 3 5 constituting the through holes 3 36 of the core substrate 230 are formed with reference to the positioning marks 2 31 of the core substrate. .
- FIG. 26 shows a cross section of the multilayer printed wiring board 410.
- the multilayer printed wiring board 410 includes a core board 430 containing an IC chip 420, an interlayer resin insulation layer 450, and an interlayer resin insulation layer 550. Become. Via holes 460 and conductor circuits 458 are formed in interlayer resin insulation layer 450, and via holes 560 and conductor circuits 558 are formed in interlayer resin insulation layer 550. .
- the IC chip 420 is covered with an IC protection film (passivation + polyimide) 422, and an aluminum die pad 42 constituting an input / output terminal is formed in an opening of the IC protection film 422. 4 are arranged. On the surface of the die pad 4 2 4 An oxide film 4 2 6 is formed. A transition layer 438 is formed on the die pad 424, and the oxide film 426 on the contact surface between the die pad 424 and the transition layer 438 is removed.
- IC protection film passivation + polyimide
- solder resist layer 470 On the interlayer resin insulating layer 550, a solder resist layer 470 is provided.
- the conductive circuit 558 below the opening 471 of the solder resist layer 470 has solder bumps 476 for connecting to an external board such as a daughter board or motherboard (not shown), or conductive not shown. Connection pins are provided.
- the IC chip 420 is built in the core substrate 43 in advance, and the transition layer 438 is provided on the die pad 424 of the IC chip 420. Have been established. For this reason, alignment at the time of forming a via hole is easy, and a build-up layer can be formed stably with a die pad pitch of 150 ⁇ or less and a pad size of 20 ⁇ or less. If a via hole of the interlayer insulating layer is formed by photoetching with the die pad having no transition layer formed thereon, if the via hole diameter is larger than the die pad diameter, the residue at the bottom of the via hole is removed and the interlayer resin is removed.
- the polyimide layer which is the protective layer on the die pad surface, is melted and damaged during the desmearing process performed as the surface roughening process of the insulating layer.
- the via hole diameter is larger than the die pad diameter
- the die pad, the passivation, and the polyimide layer (IC protective film) are destroyed by the laser.
- the pad of the IC chip is very small and the diameter of the via hole becomes larger than the size of the die pad, it is very difficult to align the photo etching method and the laser method, and connection failure between the die pad and the via hole frequently occurs.
- the transition layer 438 on the die pad 424 the die pad pitch is less than 150 / m.
- the via hole 460 can be securely connected on the die pad 424.
- the connection and reliability between the pad 4 2 4 and the via hole 4 6 0 are improved.
- the die pad and the die pad can be immersed in an acid or an etching solution during a post-process such as desmearing or a plating process, or even after various annealing processes. There is no danger of dissolving or damaging the IC protective film (passivation, polyimide layer).
- the oxide film 4 2 formed on the surface of the aluminum die pad 4 2 4 6 Force The contact surface between the die pad 4 2 4 and the transition layer 4 3 8 has been removed by the oxide film removal treatment described later, so the electrical resistance of the die pad 4 2 4 can be reduced and the conductivity can be increased. Becomes
- a concave portion 432 for accommodating an IC chip is formed on one surface of the core substrate 4300 by zigzag processing (see FIG. 22 (B)).
- FIG. 27 (A) shows an enlarged explanatory view of the die pad 424 portion of the IC chip 420.
- the core substrate 430 can be made smooth.
- the core substrate 430 accommodating the IC chip 420 is placed in a sputtering apparatus in a vacuum state, and argon gas, which is an inert gas, is used as a sputtering gas. Reverse sputtering is performed using the exposed oxide film 426 as a target to remove the exposed oxide film 426 (see FIG. 23 (A)).
- FIG. 27 (B) shows an enlarged explanatory view of the die pad 424 portion of the IC chip 420. As a result, the electric resistance of the die pad 424 can be reduced, the conductivity can be increased, and the adhesion to the transition layer can be improved.
- reverse sputtering is used as the oxide film removal processing, but plasma processing can be used instead of reverse sputtering.
- plasma processing place the substrate in a vacuum-equipped apparatus and use oxygen, nitrogen, or carbon dioxide.
- a plasma is released in carbon tetrafluoride to remove the oxide film on the die pad surface.
- the surface of the die pad can be treated with acid to remove the oxide film. It is preferable to use phosphoric acid for the oxide film removal treatment.
- the oxide film is removed.
- D Metal film 433 is made of a metal such as tin, chromium, titanium, nickel, zinc, konole, gold, or copper. It is better to form more than one layer.
- the thickness is preferably in the range of 0.000 :! to 2.0 / im. In particular, 0.01 to 1.0 im is preferable.
- the thickness of chromium should be such that cracks do not occur in the sputtered layer and that the adhesion to the copper sputtered layer is sufficient.
- the oxide film is again formed on the pad surface. Without this, the conductivity between the die pad 424 of the IC chip and the transition layer 438 can be increased.
- a plating film 4336 may be formed on the metal film 433 by electroless plating, electrolytic plating, or a composite plating thereof (see FIG. 23 (C)).
- the types of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics, and the fact that the conductive layer, which is a build-up that will be formed later, is mainly made of copper.
- the thickness is preferably in the range of 0.01 to 5 ⁇ m. In particular, 0.1 to 3 ⁇ is desirable. It can also be formed by sputtering or vapor deposition. Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding with metals and electrical conductivity.
- FIG. 27 (C) is an enlarged explanatory view of the die pad 424 portion of the IC chip 420.
- the transition layer 438 is formed by a mask resist, but after the electrolytic plating film 437 is uniformly formed on the electroless plating film 436, an etching resist is formed. It is also possible to form a transition layer 438 on the die pad 424 of the IC chip 420 by exposing and developing to expose the metal other than the transition layer and performing etching.
- the thickness of the electrolytic plating film 437 is preferably in the range of 1 to 20 m. If the thickness is larger than that, an under force may occur during the etching, and a gap may be generated at the interface between the formed transition layer and the via hole.
- an etching solution is sprayed on the substrate by spraying to form a roughened surface 438 ⁇ by etching the surface of the transition layer 438 (see FIG. 24 (2)).
- a roughened surface can also be formed using electroless plating or redox treatment.
- thermosetting resin sheet is vacuum-laminated on the substrate having undergone the above steps in the same manner as in the first embodiment to provide an interlayer resin insulating layer 450 (see FIG. 24 (C)).
- an interlayer resin insulating layer 4 5 0 Baiahoru-opening port 4 4 8 at C_ ⁇ 2 gas laser (second 4 diagram (D) refer).
- the resin residue in the opening 448 may be removed using an oxidizing agent such as chromic acid or permanganic acid.
- Providing a copper transition layer 438 on the die pad 4 2 4 facilitates alignment when forming via holes, ensures that via holes are connected on the die pad 4 2 4, and connects pads to via holes. Improve performance and reliability. Thereby, the build-up layer can be formed stably.
- the die pad 424 and IC protective film (passivation, polyimide layer) 422 are immersed in an etching solution or subjected to various annealing processes. There is no danger of melting or damage. In this case, the residue on the lunar surface was removed using permanganate, but desmear treatment using oxygen plasma is also possible.
- the surface of the interlayer resin insulating layer 450 is roughened to form a roughened surface 450 ⁇ (see FIG. 25 ( ⁇ )). Note that the roughing step can be omitted.
- FIG. 28 shows a cross section of the multilayer printed wiring board 5110.
- FIG. 29 is an enlarged view of the die pad 424.
- FIG. 29 ( ⁇ ) shows an oxide film removed treatment.
- FIG. 29 ( ⁇ ) shows the state after the oxide film removal processing, and
- FIG. 29 (C) shows the state of forming the transition layer 438 on the die pad 424.
- FIG. in the third embodiment described above the case where BG # is provided has been described.
- the first modification of the third embodiment is almost the same as the third embodiment, but is configured as a PGA system in which connection is made via conductive connection pins 496 as shown in FIG.
- FIG. 29 (C) a transition layer 4 3 8 composed of a metal film 4 3 3, an electroless plating film 4 36, and an electrolytic plating film 4 3 7 is formed on the die pad 4 2 4. Is formed.
- the electric resistance of the die head 426 can be reduced, and the conductivity can be increased.
- a multilayer layer was obtained by forming a transition layer in the same manner as in the third embodiment except that the film was not removed.
- the multi-layer printed wiring boards of the third embodiment and the comparative example were evaluated for a total of four items: 1) cross-sectional state, measured resistance, 3) cross-sectional state after reliability test, and 4) measured resistance. Is shown in the table in FIG.
- the section was cut and cut, and the presence or absence of an oxide film on the pad was observed with a microscope (X100).
- connection resistance was measured.
- the measured value is the average of 20 points measured.
- the cross section after the heat cycle test 100 cycles of (13 OC / 3 min) (-600; CZ 3 min) as one cycle) was performed. Cut and check for oxide film on the pad, and
- connection resistance was reduced after the heat cycle test was performed (100 cycles were performed with one cycle of (3 min at 130) + (3 min at -600 ° C)). It was measured. The measured value is the average of the measured values at 20 force points.
- the multilayer printed wiring board of the third embodiment does not have an oxide film and has a small connection resistance, so that there is no problem in electrical connection. won. Deterioration was small after the reliability test. By the way, even after the heat cycle test was repeated for 2000 cycles, the resistance value did not increase so much.
- the oxide film remained, the connection resistance was large, and there were some places where no electrical connection could be made in some cases .: After the reliability test, the tendency was more remarkable.
Description
Claims
Priority Applications (14)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/181,682 US6909054B2 (en) | 2000-02-25 | 2001-01-12 | Multilayer printed wiring board and method for producing multilayer printed wiring board |
DE60128656T DE60128656T2 (de) | 2000-02-25 | 2001-01-12 | Mehrschichtige leiterplatte und verfahren zu ihrer herstellung |
EP01900747A EP1259103B1 (en) | 2000-02-25 | 2001-01-12 | Multilayer printed wiring board and method for producing multilayer printed wiring board |
KR1020027011073A KR100890534B1 (ko) | 2000-02-25 | 2001-01-12 | 다층프린트배선판 및 다층프린트배선판의 제조방법 |
US10/793,515 US7435910B2 (en) | 2000-02-25 | 2004-03-04 | Multilayer printed circuit board |
US11/757,750 US7842887B2 (en) | 2000-02-25 | 2007-06-04 | Multilayer printed circuit board |
US12/034,581 US7888606B2 (en) | 2000-02-25 | 2008-02-20 | Multilayer printed circuit board |
US12/034,586 US7884286B2 (en) | 2000-02-25 | 2008-02-20 | Multilayer printed circuit board |
US12/034,572 US7888605B2 (en) | 2000-02-25 | 2008-02-20 | Multilayer printed circuit board |
US12/103,414 US8186045B2 (en) | 2000-02-25 | 2008-04-15 | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
US12/273,939 US8079142B2 (en) | 2000-02-25 | 2008-11-19 | Printed circuit board manufacturing method |
US12/571,973 US8438727B2 (en) | 2000-02-25 | 2009-10-01 | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
US12/572,000 US8046914B2 (en) | 2000-02-25 | 2009-10-01 | Method for manufacturing multilayer printed circuit board |
US13/234,721 US8453323B2 (en) | 2000-02-25 | 2011-09-16 | Printed circuit board manufacturing method |
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US10/181,682 A-371-Of-International US6909054B2 (en) | 2000-02-25 | 2001-01-12 | Multilayer printed wiring board and method for producing multilayer printed wiring board |
US10181682 A-371-Of-International | 2001-01-12 | ||
US10/793,515 Continuation US7435910B2 (en) | 2000-02-25 | 2004-03-04 | Multilayer printed circuit board |
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EP (6) | EP1990831A3 (ja) |
KR (2) | KR100890534B1 (ja) |
CN (1) | CN100336426C (ja) |
DE (1) | DE60128656T2 (ja) |
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